xiemeng / Optek_sdk_131 · Commits

Commit 813de0b701d288ad2350025946d1bdf55728607e

Authored by WuYongKang
1 parent 31c42d6f

Revert "Increase the priority of Optek Link" 

This reverts commit 31c42d6f.
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Showing 14 changed files with 271 additions and 117 deletions
1 controller Lib release notes 1 controller Lib release notes
2 2
3 -V 1.53 on May 19 2021  
4 - support hfp in optek link slave  
5 -  
6 V 1.52 on December 8 2020 3 V 1.52 on December 8 2020
7 add function uint8_t ld_acl_get_slave_time_sync_init (void) 4 add function uint8_t ld_acl_get_slave_time_sync_init (void)
8 5
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@@ -180,11 +180,7 @@ void app_nav_rmt_convert_bt_hci(void) @@ -180,11 +180,7 @@ void app_nav_rmt_convert_bt_hci(void)
180 app_main_data.playing_stream_status = STREAM_WAITING_DATA; 180 app_main_data.playing_stream_status = STREAM_WAITING_DATA;
181 app_main_data.ui_background = app_nav_bt_hci_process; 181 app_main_data.ui_background = app_nav_bt_hci_process;
182 182
183 - if(app_main_data.share_link_role != SL_ROLE_SLAVE)  
184 - {  
185 - //uiBtHCI_relink();  
186 - app_timer_bt_reLinktTimer_time_set(3000);  
187 - } 183 + //uiBtHCI_relink();
188 184
189 if (app_main_data.share_link_role == SL_ROLE_SLAVE) 185 if (app_main_data.share_link_role == SL_ROLE_SLAVE)
190 { 186 {
@@ -255,15 +255,6 @@ U8 _app_flash_program_user_data(U32 addr, U32 *buf, U32 byte_len) @@ -255,15 +255,6 @@ U8 _app_flash_program_user_data(U32 addr, U32 *buf, U32 byte_len)
255 #if 1 255 #if 1
256 DBG_FlashAssert(addr >= FLASH_BASE_ADDR); 256 DBG_FlashAssert(addr >= FLASH_BASE_ADDR);
257 257
258 - #ifdef OPTEK_LINK_ENABLE  
259 - extern U8 optek_link_enable;  
260 - if (optek_link_enable)  
261 - {  
262 - optek_link_set_master_sleep_time(3*200,1);  
263 - delayms(75);  
264 - }  
265 - #endif  
266 -  
267 #if 1 258 #if 1
268 vTaskSuspendAll(); 259 vTaskSuspendAll();
269 //UART_INT_DISABLE( UART2_INT_MASK ); 260 //UART_INT_DISABLE( UART2_INT_MASK );
@@ -19,7 +19,7 @@ @@ -19,7 +19,7 @@
19 #include "app_ver.h" 19 #include "app_ver.h"
20 #include "flash_boot.h" 20 #include "flash_boot.h"
21 21
22 -const char sdk_version[] = "(BlueSea SDK)V1.2.D7 optek link SDK V1.2 20210525"; 22 +const char sdk_version[] = "(BlueSea SDK)V1.2.D7 optek link SDK V1.1 20210511";
23 23
24 const char project_ver_date[] = __DATE__; 24 const char project_ver_date[] = __DATE__;
25 const char project_time_date[] = __TIME__; 25 const char project_time_date[] = __TIME__;
@@ -111,10 +111,6 @@ void pcm_dec_init(void) @@ -111,10 +111,6 @@ void pcm_dec_init(void)
111 max_peak = 0; 111 max_peak = 0;
112 noice_cnt = 0; 112 noice_cnt = 0;
113 113
114 - #ifndef OPTEK_LINK_ENABLE  
115 - app_dac_receive_pcm_enable(TRUE);  
116 - #endif  
117 -  
118 inout_dma_sync_flag = FALSE; 114 inout_dma_sync_flag = FALSE;
119 } 115 }
120 116
@@ -127,6 +123,7 @@ extern volatile U8 master_rev_flag; @@ -127,6 +123,7 @@ extern volatile U8 master_rev_flag;
127 U8* wait_decode_data(void); 123 U8* wait_decode_data(void);
128 int pcm_dec_decode_frame(U8 **pout,U16 *plen) 124 int pcm_dec_decode_frame(U8 **pout,U16 *plen)
129 { 125 {
  126 +#ifdef OPL_MASTER_ENABLE
130 U8 *p; 127 U8 *p;
131 U16 size,i; 128 U16 size,i;
132 129
@@ -148,7 +145,55 @@ int pcm_dec_decode_frame(U8 **pout,U16 *plen) @@ -148,7 +145,55 @@ int pcm_dec_decode_frame(U8 **pout,U16 *plen)
148 //DBG_Printf("dma0:%d\r\n",DMA_0_COUNT); 145 //DBG_Printf("dma0:%d\r\n",DMA_0_COUNT);
149 return DECODE_SUCCESS; 146 return DECODE_SUCCESS;
150 } 147 }
151 - 148 +
  149 + /************sync with dma0************/
  150 +#if 0
  151 + if (inout_dma_sync_flag == FALSE)
  152 + {
  153 + U32 dma0_cnt = DMA_0_COUNT;
  154 + U32 in_out_offset;
  155 +
  156 + #ifdef OPL_MODE_TWO_WAY
  157 + in_out_offset = 180;
  158 + #else
  159 + in_out_offset = 64;
  160 + #endif
  161 + //i32 count = ((AD_PCM_BLOCK_SIZE/2-16) - dma0_cnt);
  162 + i32 count = ((AD_PCM_BLOCK_SIZE/2-in_out_offset) - dma0_cnt);
  163 +
  164 + discard_frame_cnt = 3;
  165 +
  166 + if (count < -8 || count > 8)
  167 + {
  168 + //adj_outsamples = count>>1;
  169 + memset(pDecOut,0,AD_PCM_BLOCK_SIZE*2);
  170 + //DBG_Printf("adj count1:%d\r\n",count);
  171 +
  172 + if (count > AD_PCM_BLOCK_SIZE/4)
  173 + {
  174 + count = AD_PCM_BLOCK_SIZE/4;
  175 + }
  176 + else if (count < (i32)(-in_out_offset))
  177 + {
  178 + count = (i32)(-in_out_offset);
  179 + }
  180 +
  181 + //DBG_Printf("adj count:%d\r\n",count);
  182 +
  183 + *pout = pDecOut;
  184 + *plen = AD_PCM_BLOCK_SIZE + (count/8)*16;
  185 +
  186 + DBG_Printf("adj count:%d\r\n");
  187 +
  188 + return DECODE_SUCCESS;
  189 + }
  190 + else
  191 + {
  192 + inout_dma_sync_flag = TRUE;
  193 + }
  194 + }
  195 +#endif
  196 + /************sync with dma0 end********/
152 197
153 if (p == NULL) 198 if (p == NULL)
154 { 199 {
@@ -160,7 +205,43 @@ int pcm_dec_decode_frame(U8 **pout,U16 *plen) @@ -160,7 +205,43 @@ int pcm_dec_decode_frame(U8 **pout,U16 *plen)
160 return DECODE_SUCCESS; 205 return DECODE_SUCCESS;
161 } 206 }
162 207
  208 + //csbm_put_tx_unencoded_data(p,AD_PCM_BLOCK_SIZE);
  209 +#else
  210 + U8 *p;
  211 + U16 size,i;
  212 + U16 discard_frame = 10;
  213 +
  214 + while(1)
  215 + {
  216 +
  217 +
  218 + p = wait_decode_data();
163 219
  220 + if (p == NULL)
  221 + continue;
  222 +
  223 + while(DMA_0_COUNT);
  224 +
  225 + optek_hifi2_16b_to_24b(pDecOut,p,AD_PCM_BLOCK_SIZE>>1);
  226 +
  227 + if (discard_frame)
  228 + {
  229 + discard_frame--;
  230 + if (discard_frame == 0)
  231 + {
  232 + DMA_0_SOURCE = (int *) pDecOut;//Source address
  233 + DMA_0_COUNT = AD_PCM_BLOCK_SIZE/2+16;
  234 + }
  235 + }
  236 + else
  237 + {
  238 + DMA_0_SOURCE = (int *) pDecOut;//Source address
  239 + DMA_0_COUNT = AD_PCM_BLOCK_SIZE/2;
  240 + }
  241 + if (wRequestDecodeFrameExit)
  242 + return DECODE_END;
  243 + }
  244 +#endif
164 #if 0 245 #if 0
165 peak = peak_level_meter_16bit(&peak_det_handle,pDecOut,AD_PCM_BLOCK_SIZE); 246 peak = peak_level_meter_16bit(&peak_det_handle,pDecOut,AD_PCM_BLOCK_SIZE);
166 247
@@ -102,7 +102,7 @@ @@ -102,7 +102,7 @@
102 102
103 #define RF_USE_OTK5288 103 #define RF_USE_OTK5288
104 104
105 -//#define BT_HFP_ENABLE //for calling 105 +#define BT_HFP_ENABLE //for calling
106 #define BT_RDA_RADIO 106 #define BT_RDA_RADIO
107 107
108 //#define BT_OUTOPLAY_ENABLE 108 //#define BT_OUTOPLAY_ENABLE
@@ -130,8 +130,8 @@ @@ -130,8 +130,8 @@
130 #define OPL_SLAVE_ENBALE 130 #define OPL_SLAVE_ENBALE
131 131
132 /*********Choose one*************/ 132 /*********Choose one*************/
133 -//#define OPL_MODE_SINGLE_WAY // use optek link lib:optek_link_5ms.a  
134 -#define OPL_MODE_TWO_WAY // use optek link lib:optek_link_5ms.a 133 +#define OPL_MODE_SINGLE_WAY // use optek link lib:optek_link_5ms.a
  134 +//#define OPL_MODE_TWO_WAY // use optek link lib:optek_link_5ms.a
135 //#define OPL_MODE_SWF // use optek link lib:optek_link_5ms_for_swf.a 135 //#define OPL_MODE_SWF // use optek link lib:optek_link_5ms_for_swf.a
136 136
137 #if (defined OPL_MODE_TWO_WAY || (defined OPL_MODE_SINGLE_WAY && defined OPL_MASTER_ENABLE)) 137 #if (defined OPL_MODE_TWO_WAY || (defined OPL_MODE_SINGLE_WAY && defined OPL_MASTER_ENABLE))
@@ -564,8 +564,6 @@ retry: @@ -564,8 +564,6 @@ retry:
564 #ifdef OPTEK_LINK_ENABLE 564 #ifdef OPTEK_LINK_ENABLE
565 if (app_main_data.share_link_role != SL_ROLE_BT) 565 if (app_main_data.share_link_role != SL_ROLE_BT)
566 { 566 {
567 - DBG_Printf("optek link ver:%s,build time:%s %s\r\n",optek_link_version_get(),optek_link_time_get(),optek_link_data_get());  
568 -  
569 optek_link_role_init(); 567 optek_link_role_init();
570 568
571 #ifdef LC3_ENCODE_ENABLE 569 #ifdef LC3_ENCODE_ENABLE
@@ -914,8 +912,7 @@ void BtHCI_disconn(u32 link_loss) @@ -914,8 +912,7 @@ void BtHCI_disconn(u32 link_loss)
914 bt_avrcp_tick = 0; 912 bt_avrcp_tick = 0;
915 bt_status.bt_main_status = enBT_DISCONNECTED; 913 bt_status.bt_main_status = enBT_DISCONNECTED;
916 bt_status.bt_avrcp_status = enBT_AVRCP_UNKNOWN; 914 bt_status.bt_avrcp_status = enBT_AVRCP_UNKNOWN;
917 -  
918 - 915 +
919 #if 0//def BT_ID3_DISPLAY_EANBLE 916 #if 0//def BT_ID3_DISPLAY_EANBLE
920 track_id3_ready = FALSE; 917 track_id3_ready = FALSE;
921 918
@@ -1677,7 +1674,6 @@ u16 bt_hci_conn_cb (u8 *btaddr) @@ -1677,7 +1674,6 @@ u16 bt_hci_conn_cb (u8 *btaddr)
1677 { 1674 {
1678 DBG_Printf("rev bt conn req\r\n"); 1675 DBG_Printf("rev bt conn req\r\n");
1679 app_bt_set_scan_enable_mode(enBT_BOTH_SCAN_DISABLE); 1676 app_bt_set_scan_enable_mode(enBT_BOTH_SCAN_DISABLE);
1680 -  
1681 return TRUE; 1677 return TRUE;
1682 } 1678 }
1683 1679
@@ -74,7 +74,7 @@ void hci_con_slv_bcst_ch_map_chg_evt_cb(struct hci_con_slv_bcst_ch_map_chg *ev) @@ -74,7 +74,7 @@ void hci_con_slv_bcst_ch_map_chg_evt_cb(struct hci_con_slv_bcst_ch_map_chg *ev)
74 74
75 #endif 75 #endif
76 76
77 -U8 optek_link_enable = FALSE; 77 +U8 csb_opened;
78 78
79 U8 is_csb_role(void) 79 U8 is_csb_role(void)
80 { 80 {
@@ -315,7 +315,7 @@ void csbm_put_tx_unencoded_data(short *ptr,U16 len) @@ -315,7 +315,7 @@ void csbm_put_tx_unencoded_data(short *ptr,U16 len)
315 #ifdef OPTEK_LINK_ENABLE 315 #ifdef OPTEK_LINK_ENABLE
316 if (app_main_data.share_link_role == SL_ROLE_MASTER) 316 if (app_main_data.share_link_role == SL_ROLE_MASTER)
317 { 317 {
318 - if (optek_link_enable == FALSE) 318 + if (csb_opened == FALSE)
319 return; 319 return;
320 } 320 }
321 321
@@ -865,8 +865,8 @@ u8 optek_link_tx_data_cb(u8 cpy, u8 *buf, u8 role, u8 ext_frame, u8 id) @@ -865,8 +865,8 @@ u8 optek_link_tx_data_cb(u8 cpy, u8 *buf, u8 role, u8 ext_frame, u8 id)
865 u8 len = 0; 865 u8 len = 0;
866 U8 packet_len; 866 U8 packet_len;
867 867
868 - //DBG_PIN_HIGH;  
869 - //DBG_PIN_LOW; 868 + //DBG_PIN_HIGH3;
  869 + //DBG_PIN_LOW3;
870 870
871 if (cpy == 1) 871 if (cpy == 1)
872 { 872 {
@@ -1000,7 +1000,7 @@ u8 optek_link_slave_conn_cb (u8 mode, u8 *slave_max_tx_len, u8 *slave_max_rx_len @@ -1000,7 +1000,7 @@ u8 optek_link_slave_conn_cb (u8 mode, u8 *slave_max_tx_len, u8 *slave_max_rx_len
1000 #if 1 1000 #if 1
1001 U8 ret = TRUE; 1001 U8 ret = TRUE;
1002 1002
1003 - //DBG_iPrintf("opl mode:%d\r\n",mode); 1003 + DBG_iPrintf("sr:%d\r\n",mode);
1004 if (conn_rej_count) 1004 if (conn_rej_count)
1005 { 1005 {
1006 conn_rej_count--; 1006 conn_rej_count--;
@@ -1124,63 +1124,98 @@ void optek_link_master_busy_ind (void) @@ -1124,63 +1124,98 @@ void optek_link_master_busy_ind (void)
1124 //DBG_Assert (0); 1124 //DBG_Assert (0);
1125 } 1125 }
1126 1126
1127 -void app_nav_optek_link_pairing(void) 1127 +#define OPTEK_LINK_MASTER_ROLE
  1128 +#define OPTEK_LINK_SLAVE_ROLE
  1129 +#define OPTEK_LINK_SCAN_ROLE
  1130 +
  1131 +void app_nav_csb_pairing(void)
1128 { 1132 {
1129 u8 succ; 1133 u8 succ;
1130 struct optek_link_setting_tag optek_link_setting_s; 1134 struct optek_link_setting_tag optek_link_setting_s;
1131 memset (&optek_link_setting_s,0,sizeof(optek_link_setting_s)); 1135 memset (&optek_link_setting_s,0,sizeof(optek_link_setting_s));
1132 1136
  1137 + DBG_Printf("PAIRING ENTER\n\r");
1133 if (app_main_data.share_link_role == SL_ROLE_MASTER) 1138 if (app_main_data.share_link_role == SL_ROLE_MASTER)
1134 - {  
1135 - U8 percentage = 2;// 1/percentage  
1136 - U16 time = 4000;// unit is packet time  
1137 -  
1138 - DBG_Printf("Master start pairing,percentage:1/%d,pairing time:%d\n\r",percentage,time);  
1139 - succ = optek_link_set_master_paring(1, percentage, time, OPTEK_LINK_H1); //enable master paring, 1/2, 5s  
1140 - }  
1141 - else if(app_main_data.share_link_role == SL_ROLE_SLAVE)  
1142 { 1139 {
1143 - DBG_Printf("slave start pairing\r\n"); 1140 +#ifdef OPTEK_LINK_MASTER_ROLE
  1141 +
  1142 + //DBG_Printf("master\n\r");
  1143 + succ = optek_link_set_master_paring(1, 2, 4000, OPTEK_LINK_H1); //enable master paring, 1/2, 5s
1144 1144
1145 - app_dac_receive_pcm_enable(FALSE);  
1146 - app_nav_bt_codec_reinit(); 1145 +#if 0
  1146 + DBG_Assert (succ == 1);
  1147 +
  1148 + optek_link_setting_s.role = OPTEK_LINK_MASTER;
  1149 +
  1150 + optek_link_setting_s.mode = TEST_MODE;
  1151 + optek_link_setting_s.max_rx_len = SLAVE_MAX_TX_LEN;
  1152 +
  1153 + optek_link_setting_s.btaddr = NULL; //for master role
  1154 + optek_link_setting_s.link_group = optek_link_group;
  1155 + optek_link_setting_s.window = 0;
  1156 + optek_link_setting_s.interval = 0;
  1157 + optek_link_setting_s.tx_power = OPTEK_LINK_POWER;
  1158 + optek_link_setting_s.paring_power = OPTEK_LINK_PARING_POWER;
  1159 +
  1160 + optek_link_setting_s.max_multi_rx_len = NULL;
  1161 +
  1162 + optek_link_setting_s.logic_addr = LOGIC_ADDR_DYNAMIC;
  1163 + optek_link_setting_s.slave_rx_all = 1;
  1164 + optek_link_setting_s.rx_skip_disable = 0;
  1165 +
  1166 + succ = optek_link_set (&optek_link_setting_s, OPTEK_LINK_H1);
  1167 + DBG_Assert (succ == 1);
  1168 +
  1169 + if (succ)
  1170 + {
  1171 + dma_and_tx_sync_req = TRUE;
  1172 + succ = kBtHCI_optek_link_enable(1, OPTEK_LINK_H1);
  1173 +
  1174 + }
  1175 + DBG_Assert (succ == 1);
  1176 +#endif
  1177 +#endif
  1178 + }
  1179 + else if(app_main_data.share_link_role == SL_ROLE_SLAVE)
  1180 + {
  1181 + #ifdef OPTEK_LINK_SCAN_ROLE
  1182 + app_dac_receive_pcm_enable(FALSE);
  1183 + app_nav_bt_codec_reinit();
  1184 + DBG_Printf("scan\n\r");
  1185 + optek_link_role_stop();
  1186 + delayms(50);
  1187 + optek_link_setting_s.role = OPTEK_LINK_SCAN;
1147 1188
1148 - optek_link_role_stop();  
1149 - delayms(50);  
1150 - optek_link_setting_s.role = OPTEK_LINK_SCAN; 1189 + optek_link_setting_s.mode = 0; //for slave and scan role
  1190 +
  1191 + optek_link_setting_s.btaddr = NULL; //for master role
  1192 + optek_link_setting_s.link_group = optek_link_group;
  1193 + optek_link_setting_s.window = 48;
  1194 + optek_link_setting_s.interval = 64;
  1195 + optek_link_setting_s.tx_power = OPTEK_LINK_POWER;
  1196 + optek_link_setting_s.paring_power = OPTEK_LINK_PARING_POWER;
  1197 + optek_link_setting_s.max_rx_len = 0;
1151 1198
1152 - optek_link_setting_s.mode = 0; //for slave and scan role  
1153 -  
1154 - optek_link_setting_s.btaddr = NULL; //for master role  
1155 - optek_link_setting_s.link_group = optek_link_group;  
1156 - optek_link_setting_s.window = 48;  
1157 - optek_link_setting_s.interval = 64;  
1158 - optek_link_setting_s.tx_power = OPTEK_LINK_POWER;  
1159 - optek_link_setting_s.paring_power = OPTEK_LINK_PARING_POWER;  
1160 - optek_link_setting_s.max_rx_len = 0; 1199 + optek_link_setting_s.max_multi_rx_len = NULL;
  1200 +
  1201 + succ = optek_link_set (&optek_link_setting_s, OPTEK_LINK_H1);
  1202 + DBG_Assert (succ == 1);
  1203 +
  1204 + if (succ)
  1205 + succ = kBtHCI_optek_link_enable(1, OPTEK_LINK_H1);
1161 1206
1162 - optek_link_setting_s.max_multi_rx_len = NULL;  
1163 -  
1164 - succ = optek_link_set (&optek_link_setting_s, OPTEK_LINK_H1);  
1165 - DBG_Assert (succ == 1);  
1166 -  
1167 - if (succ)  
1168 - succ = kBtHCI_optek_link_enable(1, OPTEK_LINK_H1); 1207 + DBG_Assert (succ == 1);
  1208 + #endif
1169 1209
1170 - DBG_Assert (succ == 1);  
1171 - optek_link_enable = TRUE;  
1172 - } 1210 + }
1173 } 1211 }
1174 1212
1175 void optek_link_role_stop(void) 1213 void optek_link_role_stop(void)
1176 { 1214 {
1177 - if (optek_link_enable)  
1178 - {  
1179 - DBG_Printf("optek_link_role_stop\n\r");  
1180 - kBtHCI_optek_link_enable(0, OPTEK_LINK_H1);  
1181 - optek_link_enable = FALSE;  
1182 - delayms(50);  
1183 - } 1215 + DBG_Printf("optek_link_role_stop\n\r");
  1216 + kBtHCI_optek_link_enable(0, OPTEK_LINK_H1);
  1217 + csb_opened = FALSE;
  1218 + delayms(50);
1184 } 1219 }
1185 1220
1186 void optek_link_master_mode_sel2spr(U32 sample_rate) 1221 void optek_link_master_mode_sel2spr(U32 sample_rate)
@@ -1215,7 +1250,9 @@ void optek_link_master_enable(U32 sample_rate) @@ -1215,7 +1250,9 @@ void optek_link_master_enable(U32 sample_rate)
1215 1250
1216 if (app_main_data.share_link_role == SL_ROLE_MASTER) 1251 if (app_main_data.share_link_role == SL_ROLE_MASTER)
1217 { 1252 {
1218 - DBG_Printf("optek link master enable\n\r"); 1253 +#ifdef OPTEK_LINK_MASTER_ROLE
  1254 +
  1255 + DBG_Printf("master\n\r");
1219 1256
1220 optek_link_setting_s.role = OPTEK_LINK_MASTER; 1257 optek_link_setting_s.role = OPTEK_LINK_MASTER;
1221 1258
@@ -1235,6 +1272,12 @@ extern U8 req_mode,req_txlen,req_rxlen; @@ -1235,6 +1272,12 @@ extern U8 req_mode,req_txlen,req_rxlen;
1235 optek_link_setting_s.mode = req_mode; 1272 optek_link_setting_s.mode = req_mode;
1236 optek_link_setting_s.max_rx_len = req_rxlen; 1273 optek_link_setting_s.max_rx_len = req_rxlen;
1237 optek_link_setting_s.max_tx_len = req_txlen; 1274 optek_link_setting_s.max_tx_len = req_txlen;
  1275 +
  1276 + if (sample_rate != 48000)
  1277 + {
  1278 + DBG_Printf("ERR:not support tx sample rate:%d\r\n",sample_rate);
  1279 + DBG_Assert(FALSE);
  1280 + }
1238 #endif 1281 #endif
1239 1282
1240 1283
@@ -1265,27 +1308,71 @@ extern U8 req_mode,req_txlen,req_rxlen; @@ -1265,27 +1308,71 @@ extern U8 req_mode,req_txlen,req_rxlen;
1265 // succ = optek_link_set_master_paring(1, 2, 1000, OPTEK_LINK_H1); //enable master paring, 1/2, 5s 1308 // succ = optek_link_set_master_paring(1, 2, 1000, OPTEK_LINK_H1); //enable master paring, 1/2, 5s
1266 1309
1267 1310
1268 - DBG_Assert (succ == 1); 1311 + DBG_Assert (succ == 1);
  1312 +#endif
1269 } 1313 }
1270 } 1314 }
1271 1315
1272 void optek_link_role_init(void) 1316 void optek_link_role_init(void)
1273 { 1317 {
  1318 +// return;
  1319 + u8 succ;
  1320 + struct optek_link_setting_tag optek_link_setting_s;
  1321 + memset (&optek_link_setting_s,0,sizeof(optek_link_setting_s));
  1322 +
  1323 + //DBG_Printf("OPTEK LINK ROLE INIT\n\r");
  1324 + DBG_Printf("optek link ver:%s,build time:%s %s\r\n",optek_link_version_get(),optek_link_time_get(),optek_link_data_get());
  1325 +
1274 if (app_main_data.share_link_role == SL_ROLE_MASTER) 1326 if (app_main_data.share_link_role == SL_ROLE_MASTER)
1275 { 1327 {
1276 - if (optek_link_enable == FALSE) 1328 +#ifdef OPTEK_LINK_MASTER_ROLE
  1329 +
  1330 + DBG_Printf("master\n\r");
  1331 + optek_link_master_enable(48000);
  1332 + csb_opened = TRUE;
  1333 + return;
  1334 + DBG_Assert (succ == 1);
  1335 +
  1336 + optek_link_setting_s.role = OPTEK_LINK_MASTER;
  1337 +
  1338 + optek_link_setting_s.mode = TEST_MODE;
  1339 + optek_link_setting_s.max_rx_len = SLAVE_MAX_TX_LEN;
  1340 +
  1341 + optek_link_setting_s.btaddr = NULL; //for master role
  1342 + optek_link_setting_s.link_group = optek_link_group;
  1343 + optek_link_setting_s.window = 0;
  1344 + optek_link_setting_s.interval = 0;
  1345 + optek_link_setting_s.tx_power = OPTEK_LINK_POWER;
  1346 + optek_link_setting_s.paring_power = OPTEK_LINK_PARING_POWER;
  1347 +
  1348 + optek_link_setting_s.max_multi_rx_len = NULL;
  1349 +
  1350 + optek_link_setting_s.logic_addr = LOGIC_ADDR_DYNAMIC;
  1351 + optek_link_setting_s.slave_rx_all = 1;
  1352 + optek_link_setting_s.rx_skip_disable = 0;
  1353 +
  1354 + succ = optek_link_set (&optek_link_setting_s, OPTEK_LINK_H1);
  1355 + DBG_Assert (succ == 1);
  1356 +
  1357 + if (succ)
1277 { 1358 {
1278 - optek_link_master_enable(48000);  
1279 - optek_link_enable = TRUE;  
1280 - } 1359 + dma_and_tx_sync_req = TRUE;
  1360 + succ = kBtHCI_optek_link_enable(1, OPTEK_LINK_H1);
  1361 + }
  1362 +
  1363 + delayms(10);
  1364 + succ = optek_link_set_master_paring(1, 2, 1000, OPTEK_LINK_H1); //enable master paring, 1/2, 5s
  1365 +
  1366 +
  1367 + DBG_Assert (succ == 1);
  1368 +#endif
1281 } 1369 }
1282 - else if (app_main_data.share_link_role == SL_ROLE_SLAVE) 1370 +
  1371 + if (app_main_data.share_link_role == SL_ROLE_SLAVE)
1283 { 1372 {
1284 - u8 succ;  
1285 - struct optek_link_setting_tag optek_link_setting_s;  
1286 - memset (&optek_link_setting_s,0,sizeof(optek_link_setting_s)); 1373 + #ifdef OPTEK_LINK_SLAVE_ROLE
1287 1374
1288 - DBG_Printf("optek link slave enable\n\r"); 1375 + DBG_Printf("salver\n\r");
1289 1376
1290 if(bt_flash_is_optek_role_btaddr_present()) 1377 if(bt_flash_is_optek_role_btaddr_present())
1291 { 1378 {
@@ -1319,13 +1406,41 @@ void optek_link_role_init(void) @@ -1319,13 +1406,41 @@ void optek_link_role_init(void)
1319 succ = kBtHCI_optek_link_enable(1, OPTEK_LINK_H1); 1406 succ = kBtHCI_optek_link_enable(1, OPTEK_LINK_H1);
1320 1407
1321 DBG_Assert (succ == 1); 1408 DBG_Assert (succ == 1);
1322 -  
1323 - optek_link_enable = TRUE;  
1324 } 1409 }
1325 else 1410 else
1326 { 1411 {
1327 optek_link_role_stop(); 1412 optek_link_role_stop();
1328 } 1413 }
  1414 +
  1415 +
  1416 + #endif
  1417 +
  1418 + #if 0//def OPTEK_LINK_SCAN_ROLE
  1419 +
  1420 + optek_link_setting_s.role = OPTEK_LINK_SCAN;
  1421 +
  1422 + optek_link_setting_s.mode = 0; //for slave and scan role
  1423 +
  1424 + optek_link_setting_s.btaddr = NULL; //for master role
  1425 + optek_link_setting_s.link_group = optek_link_group;
  1426 + optek_link_setting_s.window = 48;
  1427 + optek_link_setting_s.interval = 64;
  1428 + optek_link_setting_s.tx_power = OPTEK_LINK_POWER;
  1429 + optek_link_setting_s.paring_power = OPTEK_LINK_PARING_POWER;
  1430 + optek_link_setting_s.max_rx_len = 0;
  1431 +
  1432 + optek_link_setting_s.max_multi_rx_len = NULL;
  1433 +
  1434 + succ = optek_link_set (&optek_link_setting_s, OPTEK_LINK_H1);
  1435 + DBG_Assert (succ == 1);
  1436 +
  1437 + if (succ)
  1438 + succ = kBtHCI_optek_link_enable(1, OPTEK_LINK_H1);
  1439 +
  1440 + DBG_Assert (succ == 1);
  1441 +
  1442 + #endif
  1443 +
1329 } 1444 }
1330 1445
1331 } 1446 }
@@ -1393,28 +1508,6 @@ void app_change_mode_req(u8 mode, u8 max_master_tx_len, u8 max_master_rx_len) @@ -1393,28 +1508,6 @@ void app_change_mode_req(u8 mode, u8 max_master_tx_len, u8 max_master_rx_len)
1393 req_rxlen = max_master_rx_len; 1508 req_rxlen = max_master_rx_len;
1394 } 1509 }
1395 1510
1396 -  
1397 -void app_sw_mode(void)  
1398 -{  
1399 - static U8 mode;  
1400 -  
1401 - app_cmd_DecoderExit();  
1402 -  
1403 - if (mode)  
1404 - {  
1405 - app_change_mode_req(BC_SF48K_PT5MS,100,6);  
1406 - }  
1407 - else  
1408 - {  
1409 - app_change_mode_req(GAME_HEADPHONE_PT_5MS_LP,100,50);  
1410 - }  
1411 - mode = !mode;  
1412 -  
1413 - app_media_mute_disable();  
1414 - uDecSend (DECODE_INIT, NULL);  
1415 - spk_out_sync_w_tx_status = SPK_AND_TX_SYNCING;  
1416 -}  
1417 -  
1418 void optek_link_cal_drift (void) 1511 void optek_link_cal_drift (void)
1419 { 1512 {
1420 u32 base_cnt_rxsync_1st; 1513 u32 base_cnt_rxsync_1st;
@@ -25,7 +25,7 @@ void csbm_tx_init(U16 sample_rate,U8 bt_src); @@ -25,7 +25,7 @@ void csbm_tx_init(U16 sample_rate,U8 bt_src);
25 void csbm_put_tx_unencoded_data(short *ptr,U16 len); 25 void csbm_put_tx_unencoded_data(short *ptr,U16 len);
26 void csbm_put_tx_encoded_data(short *ptr,U16 len); 26 void csbm_put_tx_encoded_data(short *ptr,U16 len);
27 void app_optek_link_role_sw(void); 27 void app_optek_link_role_sw(void);
28 -void app_nav_optek_link_pairing(void); 28 +void app_nav_csb_pairing(void);
29 void optek_link_master_enable(U32 sample_rate); 29 void optek_link_master_enable(U32 sample_rate);
30 void optek_link_role_stop(void); 30 void optek_link_role_stop(void);
31 void optek_link_master_mode_sel2spr(U32 sample_rate); 31 void optek_link_master_mode_sel2spr(U32 sample_rate);
@@ -19,7 +19,7 @@ static const KEY_AD_ENTRY oem_main_kbd_entry0[] = { @@ -19,7 +19,7 @@ static const KEY_AD_ENTRY oem_main_kbd_entry0[] = {
19 #if 1 19 #if 1
20 {(0x000 - 0x000), (0x000 + V_TOLERANCE ), APP_KEY_SOURCE}, //Source 20 {(0x000 - 0x000), (0x000 + V_TOLERANCE ), APP_KEY_SOURCE}, //Source
21 {(0x110 - V_TOLERANCE ), (0x110 + V_TOLERANCE ), APP_KEY_PLAY}, //Play/Pause 21 {(0x110 - V_TOLERANCE ), (0x110 + V_TOLERANCE ), APP_KEY_PLAY}, //Play/Pause
22 - {(0x230 - V_TOLERANCE ), (0x230 + V_TOLERANCE ), APP_KEY_STOP}, //STOP 22 + {(0x230 - V_TOLERANCE ), (0x230 + V_TOLERANCE ), APP_KEY_SOURCE}, //STOP
23 {(0x340 - V_TOLERANCE ), (0x340 + V_TOLERANCE ), APP_KEY_SKIPF}, //skipF 23 {(0x340 - V_TOLERANCE ), (0x340 + V_TOLERANCE ), APP_KEY_SKIPF}, //skipF
24 {(0x470 - V_TOLERANCE ), (0x470 + V_TOLERANCE ), APP_KEY_SKIPB}, //skipB 24 {(0x470 - V_TOLERANCE ), (0x470 + V_TOLERANCE ), APP_KEY_SKIPB}, //skipB
25 {(0x5A0 - V_TOLERANCE ), (0x5A0 + V_TOLERANCE ), APP_KEY_PLUS}, //Vol + 25 {(0x5A0 - V_TOLERANCE ), (0x5A0 + V_TOLERANCE ), APP_KEY_PLUS}, //Vol +
@@ -339,9 +339,9 @@ void app_window_prompt_2_window_init (void) @@ -339,9 +339,9 @@ void app_window_prompt_2_window_init (void)
339 const APP_NAV_KEY APP_NAV_AUX_KEY [] = 339 const APP_NAV_KEY APP_NAV_AUX_KEY [] =
340 { 340 {
341 #if (defined OPTEK_LINK_ENABLE) 341 #if (defined OPTEK_LINK_ENABLE)
342 - {APP_KEY_PLAY,NULL,app_nav_optek_link_pairing,2000,app_optek_link_role_sw}, 342 + {APP_KEY_PLAY,NULL,app_nav_csb_pairing,2000,app_optek_link_role_sw},
343 #else 343 #else
344 - {APP_KEY_PLAY,app_nav_optek_link_pairing,NULL,5000,enter_bt_test_mode}, 344 + {APP_KEY_PLAY,app_nav_csb_pairing,NULL,5000,enter_bt_test_mode},
345 #endif 345 #endif
346 346
347 {APP_KEY_STOP,NULL,NULL,2000,app_nav_upgrade_project}, 347 {APP_KEY_STOP,NULL,NULL,2000,app_nav_upgrade_project},
@@ -810,7 +810,7 @@ const APP_NAV_KEY APP_NAV_BT_HCI_KEY [] = @@ -810,7 +810,7 @@ const APP_NAV_KEY APP_NAV_BT_HCI_KEY [] =
810 { 810 {
811 // {APP_KEY_PLAY,app_nav_bt_hci_play,NULL,5000,enter_bt_test_mode}, 811 // {APP_KEY_PLAY,app_nav_bt_hci_play,NULL,5000,enter_bt_test_mode},
812 #if (defined OPTEK_LINK_ENABLE) 812 #if (defined OPTEK_LINK_ENABLE)
813 - {APP_KEY_PLAY,NULL,app_nav_optek_link_pairing,2000,app_optek_link_role_sw}, 813 + {APP_KEY_PLAY,NULL,app_nav_csb_pairing,2000,app_optek_link_role_sw},
814 #else 814 #else
815 {APP_KEY_PLAY,app_nav_bt_hci_play,NULL,5000,enter_bt_test_mode}, 815 {APP_KEY_PLAY,app_nav_bt_hci_play,NULL,5000,enter_bt_test_mode},
816 #endif 816 #endif
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