Commit 31c42d6ffef67e0b3627b378d19ff5af9015850e

Authored by luozhesi
1 parent 4d704d23

Increase the priority of Optek Link

1 1 controller Lib release notes
2 2
  3 +V 1.53 on May 19 2021
  4 + support hfp in optek link slave
  5 +
3 6 V 1.52 on December 8 2020
4 7 add function uint8_t ld_acl_get_slave_time_sync_init (void)
5 8
... ...
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... ... @@ -180,7 +180,11 @@ void app_nav_rmt_convert_bt_hci(void)
180 180 app_main_data.playing_stream_status = STREAM_WAITING_DATA;
181 181 app_main_data.ui_background = app_nav_bt_hci_process;
182 182
183   - //uiBtHCI_relink();
  183 + if(app_main_data.share_link_role != SL_ROLE_SLAVE)
  184 + {
  185 + //uiBtHCI_relink();
  186 + app_timer_bt_reLinktTimer_time_set(3000);
  187 + }
184 188
185 189 if (app_main_data.share_link_role == SL_ROLE_SLAVE)
186 190 {
... ...
... ... @@ -255,6 +255,15 @@ U8 _app_flash_program_user_data(U32 addr, U32 *buf, U32 byte_len)
255 255 #if 1
256 256 DBG_FlashAssert(addr >= FLASH_BASE_ADDR);
257 257
  258 + #ifdef OPTEK_LINK_ENABLE
  259 + extern U8 optek_link_enable;
  260 + if (optek_link_enable)
  261 + {
  262 + optek_link_set_master_sleep_time(3*200,1);
  263 + delayms(75);
  264 + }
  265 + #endif
  266 +
258 267 #if 1
259 268 vTaskSuspendAll();
260 269 //UART_INT_DISABLE( UART2_INT_MASK );
... ...
... ... @@ -19,7 +19,7 @@
19 19 #include "app_ver.h"
20 20 #include "flash_boot.h"
21 21
22   -const char sdk_version[] = "(BlueSea SDK)V1.2.D7 optek link SDK V1.1 20210511";
  22 +const char sdk_version[] = "(BlueSea SDK)V1.2.D7 optek link SDK V1.2 20210525";
23 23
24 24 const char project_ver_date[] = __DATE__;
25 25 const char project_time_date[] = __TIME__;
... ...
... ... @@ -111,6 +111,10 @@ void pcm_dec_init(void)
111 111 max_peak = 0;
112 112 noice_cnt = 0;
113 113
  114 + #ifndef OPTEK_LINK_ENABLE
  115 + app_dac_receive_pcm_enable(TRUE);
  116 + #endif
  117 +
114 118 inout_dma_sync_flag = FALSE;
115 119 }
116 120
... ... @@ -123,7 +127,6 @@ extern volatile U8 master_rev_flag;
123 127 U8* wait_decode_data(void);
124 128 int pcm_dec_decode_frame(U8 **pout,U16 *plen)
125 129 {
126   -#ifdef OPL_MASTER_ENABLE
127 130 U8 *p;
128 131 U16 size,i;
129 132
... ... @@ -145,55 +148,7 @@ int pcm_dec_decode_frame(U8 **pout,U16 *plen)
145 148 //DBG_Printf("dma0:%d\r\n",DMA_0_COUNT);
146 149 return DECODE_SUCCESS;
147 150 }
148   -
149   - /************sync with dma0************/
150   -#if 0
151   - if (inout_dma_sync_flag == FALSE)
152   - {
153   - U32 dma0_cnt = DMA_0_COUNT;
154   - U32 in_out_offset;
155   -
156   - #ifdef OPL_MODE_TWO_WAY
157   - in_out_offset = 180;
158   - #else
159   - in_out_offset = 64;
160   - #endif
161   - //i32 count = ((AD_PCM_BLOCK_SIZE/2-16) - dma0_cnt);
162   - i32 count = ((AD_PCM_BLOCK_SIZE/2-in_out_offset) - dma0_cnt);
163   -
164   - discard_frame_cnt = 3;
165   -
166   - if (count < -8 || count > 8)
167   - {
168   - //adj_outsamples = count>>1;
169   - memset(pDecOut,0,AD_PCM_BLOCK_SIZE*2);
170   - //DBG_Printf("adj count1:%d\r\n",count);
171   -
172   - if (count > AD_PCM_BLOCK_SIZE/4)
173   - {
174   - count = AD_PCM_BLOCK_SIZE/4;
175   - }
176   - else if (count < (i32)(-in_out_offset))
177   - {
178   - count = (i32)(-in_out_offset);
179   - }
180   -
181   - //DBG_Printf("adj count:%d\r\n",count);
182   -
183   - *pout = pDecOut;
184   - *plen = AD_PCM_BLOCK_SIZE + (count/8)*16;
185   -
186   - DBG_Printf("adj count:%d\r\n");
187   -
188   - return DECODE_SUCCESS;
189   - }
190   - else
191   - {
192   - inout_dma_sync_flag = TRUE;
193   - }
194   - }
195   -#endif
196   - /************sync with dma0 end********/
  151 +
197 152
198 153 if (p == NULL)
199 154 {
... ... @@ -205,43 +160,7 @@ int pcm_dec_decode_frame(U8 **pout,U16 *plen)
205 160 return DECODE_SUCCESS;
206 161 }
207 162
208   - //csbm_put_tx_unencoded_data(p,AD_PCM_BLOCK_SIZE);
209   -#else
210   - U8 *p;
211   - U16 size,i;
212   - U16 discard_frame = 10;
213   -
214   - while(1)
215   - {
216   -
217   -
218   - p = wait_decode_data();
219 163
220   - if (p == NULL)
221   - continue;
222   -
223   - while(DMA_0_COUNT);
224   -
225   - optek_hifi2_16b_to_24b(pDecOut,p,AD_PCM_BLOCK_SIZE>>1);
226   -
227   - if (discard_frame)
228   - {
229   - discard_frame--;
230   - if (discard_frame == 0)
231   - {
232   - DMA_0_SOURCE = (int *) pDecOut;//Source address
233   - DMA_0_COUNT = AD_PCM_BLOCK_SIZE/2+16;
234   - }
235   - }
236   - else
237   - {
238   - DMA_0_SOURCE = (int *) pDecOut;//Source address
239   - DMA_0_COUNT = AD_PCM_BLOCK_SIZE/2;
240   - }
241   - if (wRequestDecodeFrameExit)
242   - return DECODE_END;
243   - }
244   -#endif
245 164 #if 0
246 165 peak = peak_level_meter_16bit(&peak_det_handle,pDecOut,AD_PCM_BLOCK_SIZE);
247 166
... ...
... ... @@ -102,7 +102,7 @@
102 102
103 103 #define RF_USE_OTK5288
104 104
105   -#define BT_HFP_ENABLE //for calling
  105 +//#define BT_HFP_ENABLE //for calling
106 106 #define BT_RDA_RADIO
107 107
108 108 //#define BT_OUTOPLAY_ENABLE
... ... @@ -130,8 +130,8 @@
130 130 #define OPL_SLAVE_ENBALE
131 131
132 132 /*********Choose one*************/
133   -#define OPL_MODE_SINGLE_WAY // use optek link lib:optek_link_5ms.a
134   -//#define OPL_MODE_TWO_WAY // use optek link lib:optek_link_5ms.a
  133 +//#define OPL_MODE_SINGLE_WAY // use optek link lib:optek_link_5ms.a
  134 +#define OPL_MODE_TWO_WAY // use optek link lib:optek_link_5ms.a
135 135 //#define OPL_MODE_SWF // use optek link lib:optek_link_5ms_for_swf.a
136 136
137 137 #if (defined OPL_MODE_TWO_WAY || (defined OPL_MODE_SINGLE_WAY && defined OPL_MASTER_ENABLE))
... ...
... ... @@ -564,6 +564,8 @@ retry:
564 564 #ifdef OPTEK_LINK_ENABLE
565 565 if (app_main_data.share_link_role != SL_ROLE_BT)
566 566 {
  567 + DBG_Printf("optek link ver:%s,build time:%s %s\r\n",optek_link_version_get(),optek_link_time_get(),optek_link_data_get());
  568 +
567 569 optek_link_role_init();
568 570
569 571 #ifdef LC3_ENCODE_ENABLE
... ... @@ -912,7 +914,8 @@ void BtHCI_disconn(u32 link_loss)
912 914 bt_avrcp_tick = 0;
913 915 bt_status.bt_main_status = enBT_DISCONNECTED;
914 916 bt_status.bt_avrcp_status = enBT_AVRCP_UNKNOWN;
915   -
  917 +
  918 +
916 919 #if 0//def BT_ID3_DISPLAY_EANBLE
917 920 track_id3_ready = FALSE;
918 921
... ... @@ -1674,6 +1677,7 @@ u16 bt_hci_conn_cb (u8 *btaddr)
1674 1677 {
1675 1678 DBG_Printf("rev bt conn req\r\n");
1676 1679 app_bt_set_scan_enable_mode(enBT_BOTH_SCAN_DISABLE);
  1680 +
1677 1681 return TRUE;
1678 1682 }
1679 1683
... ...
... ... @@ -74,7 +74,7 @@ void hci_con_slv_bcst_ch_map_chg_evt_cb(struct hci_con_slv_bcst_ch_map_chg *ev)
74 74
75 75 #endif
76 76
77   -U8 csb_opened;
  77 +U8 optek_link_enable = FALSE;
78 78
79 79 U8 is_csb_role(void)
80 80 {
... ... @@ -315,7 +315,7 @@ void csbm_put_tx_unencoded_data(short *ptr,U16 len)
315 315 #ifdef OPTEK_LINK_ENABLE
316 316 if (app_main_data.share_link_role == SL_ROLE_MASTER)
317 317 {
318   - if (csb_opened == FALSE)
  318 + if (optek_link_enable == FALSE)
319 319 return;
320 320 }
321 321
... ... @@ -865,8 +865,8 @@ u8 optek_link_tx_data_cb(u8 cpy, u8 *buf, u8 role, u8 ext_frame, u8 id)
865 865 u8 len = 0;
866 866 U8 packet_len;
867 867
868   - //DBG_PIN_HIGH3;
869   - //DBG_PIN_LOW3;
  868 + //DBG_PIN_HIGH;
  869 + //DBG_PIN_LOW;
870 870
871 871 if (cpy == 1)
872 872 {
... ... @@ -1000,7 +1000,7 @@ u8 optek_link_slave_conn_cb (u8 mode, u8 *slave_max_tx_len, u8 *slave_max_rx_len
1000 1000 #if 1
1001 1001 U8 ret = TRUE;
1002 1002
1003   - DBG_iPrintf("sr:%d\r\n",mode);
  1003 + //DBG_iPrintf("opl mode:%d\r\n",mode);
1004 1004 if (conn_rej_count)
1005 1005 {
1006 1006 conn_rej_count--;
... ... @@ -1124,98 +1124,63 @@ void optek_link_master_busy_ind (void)
1124 1124 //DBG_Assert (0);
1125 1125 }
1126 1126
1127   -#define OPTEK_LINK_MASTER_ROLE
1128   -#define OPTEK_LINK_SLAVE_ROLE
1129   -#define OPTEK_LINK_SCAN_ROLE
1130   -
1131   -void app_nav_csb_pairing(void)
  1127 +void app_nav_optek_link_pairing(void)
1132 1128 {
1133 1129 u8 succ;
1134 1130 struct optek_link_setting_tag optek_link_setting_s;
1135 1131 memset (&optek_link_setting_s,0,sizeof(optek_link_setting_s));
1136 1132
1137   - DBG_Printf("PAIRING ENTER\n\r");
1138 1133 if (app_main_data.share_link_role == SL_ROLE_MASTER)
  1134 + {
  1135 + U8 percentage = 2;// 1/percentage
  1136 + U16 time = 4000;// unit is packet time
  1137 +
  1138 + DBG_Printf("Master start pairing,percentage:1/%d,pairing time:%d\n\r",percentage,time);
  1139 + succ = optek_link_set_master_paring(1, percentage, time, OPTEK_LINK_H1); //enable master paring, 1/2, 5s
  1140 + }
  1141 + else if(app_main_data.share_link_role == SL_ROLE_SLAVE)
1139 1142 {
1140   -#ifdef OPTEK_LINK_MASTER_ROLE
1141   -
1142   - //DBG_Printf("master\n\r");
1143   - succ = optek_link_set_master_paring(1, 2, 4000, OPTEK_LINK_H1); //enable master paring, 1/2, 5s
  1143 + DBG_Printf("slave start pairing\r\n");
1144 1144
1145   -#if 0
1146   - DBG_Assert (succ == 1);
1147   -
1148   - optek_link_setting_s.role = OPTEK_LINK_MASTER;
1149   -
1150   - optek_link_setting_s.mode = TEST_MODE;
1151   - optek_link_setting_s.max_rx_len = SLAVE_MAX_TX_LEN;
1152   -
1153   - optek_link_setting_s.btaddr = NULL; //for master role
1154   - optek_link_setting_s.link_group = optek_link_group;
1155   - optek_link_setting_s.window = 0;
1156   - optek_link_setting_s.interval = 0;
1157   - optek_link_setting_s.tx_power = OPTEK_LINK_POWER;
1158   - optek_link_setting_s.paring_power = OPTEK_LINK_PARING_POWER;
1159   -
1160   - optek_link_setting_s.max_multi_rx_len = NULL;
1161   -
1162   - optek_link_setting_s.logic_addr = LOGIC_ADDR_DYNAMIC;
1163   - optek_link_setting_s.slave_rx_all = 1;
1164   - optek_link_setting_s.rx_skip_disable = 0;
1165   -
1166   - succ = optek_link_set (&optek_link_setting_s, OPTEK_LINK_H1);
1167   - DBG_Assert (succ == 1);
1168   -
1169   - if (succ)
1170   - {
1171   - dma_and_tx_sync_req = TRUE;
1172   - succ = kBtHCI_optek_link_enable(1, OPTEK_LINK_H1);
1173   -
1174   - }
1175   - DBG_Assert (succ == 1);
1176   -#endif
1177   -#endif
1178   - }
1179   - else if(app_main_data.share_link_role == SL_ROLE_SLAVE)
1180   - {
1181   - #ifdef OPTEK_LINK_SCAN_ROLE
1182   - app_dac_receive_pcm_enable(FALSE);
1183   - app_nav_bt_codec_reinit();
1184   - DBG_Printf("scan\n\r");
1185   - optek_link_role_stop();
1186   - delayms(50);
1187   - optek_link_setting_s.role = OPTEK_LINK_SCAN;
  1145 + app_dac_receive_pcm_enable(FALSE);
  1146 + app_nav_bt_codec_reinit();
1188 1147
1189   - optek_link_setting_s.mode = 0; //for slave and scan role
1190   -
1191   - optek_link_setting_s.btaddr = NULL; //for master role
1192   - optek_link_setting_s.link_group = optek_link_group;
1193   - optek_link_setting_s.window = 48;
1194   - optek_link_setting_s.interval = 64;
1195   - optek_link_setting_s.tx_power = OPTEK_LINK_POWER;
1196   - optek_link_setting_s.paring_power = OPTEK_LINK_PARING_POWER;
1197   - optek_link_setting_s.max_rx_len = 0;
  1148 + optek_link_role_stop();
  1149 + delayms(50);
  1150 + optek_link_setting_s.role = OPTEK_LINK_SCAN;
1198 1151
1199   - optek_link_setting_s.max_multi_rx_len = NULL;
1200   -
1201   - succ = optek_link_set (&optek_link_setting_s, OPTEK_LINK_H1);
1202   - DBG_Assert (succ == 1);
1203   -
1204   - if (succ)
1205   - succ = kBtHCI_optek_link_enable(1, OPTEK_LINK_H1);
  1152 + optek_link_setting_s.mode = 0; //for slave and scan role
  1153 +
  1154 + optek_link_setting_s.btaddr = NULL; //for master role
  1155 + optek_link_setting_s.link_group = optek_link_group;
  1156 + optek_link_setting_s.window = 48;
  1157 + optek_link_setting_s.interval = 64;
  1158 + optek_link_setting_s.tx_power = OPTEK_LINK_POWER;
  1159 + optek_link_setting_s.paring_power = OPTEK_LINK_PARING_POWER;
  1160 + optek_link_setting_s.max_rx_len = 0;
1206 1161
1207   - DBG_Assert (succ == 1);
1208   - #endif
  1162 + optek_link_setting_s.max_multi_rx_len = NULL;
  1163 +
  1164 + succ = optek_link_set (&optek_link_setting_s, OPTEK_LINK_H1);
  1165 + DBG_Assert (succ == 1);
  1166 +
  1167 + if (succ)
  1168 + succ = kBtHCI_optek_link_enable(1, OPTEK_LINK_H1);
1209 1169
1210   - }
  1170 + DBG_Assert (succ == 1);
  1171 + optek_link_enable = TRUE;
  1172 + }
1211 1173 }
1212 1174
1213 1175 void optek_link_role_stop(void)
1214 1176 {
1215   - DBG_Printf("optek_link_role_stop\n\r");
1216   - kBtHCI_optek_link_enable(0, OPTEK_LINK_H1);
1217   - csb_opened = FALSE;
1218   - delayms(50);
  1177 + if (optek_link_enable)
  1178 + {
  1179 + DBG_Printf("optek_link_role_stop\n\r");
  1180 + kBtHCI_optek_link_enable(0, OPTEK_LINK_H1);
  1181 + optek_link_enable = FALSE;
  1182 + delayms(50);
  1183 + }
1219 1184 }
1220 1185
1221 1186 void optek_link_master_mode_sel2spr(U32 sample_rate)
... ... @@ -1250,9 +1215,7 @@ void optek_link_master_enable(U32 sample_rate)
1250 1215
1251 1216 if (app_main_data.share_link_role == SL_ROLE_MASTER)
1252 1217 {
1253   -#ifdef OPTEK_LINK_MASTER_ROLE
1254   -
1255   - DBG_Printf("master\n\r");
  1218 + DBG_Printf("optek link master enable\n\r");
1256 1219
1257 1220 optek_link_setting_s.role = OPTEK_LINK_MASTER;
1258 1221
... ... @@ -1272,12 +1235,6 @@ extern U8 req_mode,req_txlen,req_rxlen;
1272 1235 optek_link_setting_s.mode = req_mode;
1273 1236 optek_link_setting_s.max_rx_len = req_rxlen;
1274 1237 optek_link_setting_s.max_tx_len = req_txlen;
1275   -
1276   - if (sample_rate != 48000)
1277   - {
1278   - DBG_Printf("ERR:not support tx sample rate:%d\r\n",sample_rate);
1279   - DBG_Assert(FALSE);
1280   - }
1281 1238 #endif
1282 1239
1283 1240
... ... @@ -1308,71 +1265,27 @@ extern U8 req_mode,req_txlen,req_rxlen;
1308 1265 // succ = optek_link_set_master_paring(1, 2, 1000, OPTEK_LINK_H1); //enable master paring, 1/2, 5s
1309 1266
1310 1267
1311   - DBG_Assert (succ == 1);
1312   -#endif
  1268 + DBG_Assert (succ == 1);
1313 1269 }
1314 1270 }
1315 1271
1316 1272 void optek_link_role_init(void)
1317 1273 {
1318   -// return;
1319   - u8 succ;
1320   - struct optek_link_setting_tag optek_link_setting_s;
1321   - memset (&optek_link_setting_s,0,sizeof(optek_link_setting_s));
1322   -
1323   - //DBG_Printf("OPTEK LINK ROLE INIT\n\r");
1324   - DBG_Printf("optek link ver:%s,build time:%s %s\r\n",optek_link_version_get(),optek_link_time_get(),optek_link_data_get());
1325   -
1326 1274 if (app_main_data.share_link_role == SL_ROLE_MASTER)
1327 1275 {
1328   -#ifdef OPTEK_LINK_MASTER_ROLE
1329   -
1330   - DBG_Printf("master\n\r");
1331   - optek_link_master_enable(48000);
1332   - csb_opened = TRUE;
1333   - return;
1334   - DBG_Assert (succ == 1);
1335   -
1336   - optek_link_setting_s.role = OPTEK_LINK_MASTER;
1337   -
1338   - optek_link_setting_s.mode = TEST_MODE;
1339   - optek_link_setting_s.max_rx_len = SLAVE_MAX_TX_LEN;
1340   -
1341   - optek_link_setting_s.btaddr = NULL; //for master role
1342   - optek_link_setting_s.link_group = optek_link_group;
1343   - optek_link_setting_s.window = 0;
1344   - optek_link_setting_s.interval = 0;
1345   - optek_link_setting_s.tx_power = OPTEK_LINK_POWER;
1346   - optek_link_setting_s.paring_power = OPTEK_LINK_PARING_POWER;
1347   -
1348   - optek_link_setting_s.max_multi_rx_len = NULL;
1349   -
1350   - optek_link_setting_s.logic_addr = LOGIC_ADDR_DYNAMIC;
1351   - optek_link_setting_s.slave_rx_all = 1;
1352   - optek_link_setting_s.rx_skip_disable = 0;
1353   -
1354   - succ = optek_link_set (&optek_link_setting_s, OPTEK_LINK_H1);
1355   - DBG_Assert (succ == 1);
1356   -
1357   - if (succ)
  1276 + if (optek_link_enable == FALSE)
1358 1277 {
1359   - dma_and_tx_sync_req = TRUE;
1360   - succ = kBtHCI_optek_link_enable(1, OPTEK_LINK_H1);
1361   - }
1362   -
1363   - delayms(10);
1364   - succ = optek_link_set_master_paring(1, 2, 1000, OPTEK_LINK_H1); //enable master paring, 1/2, 5s
1365   -
1366   -
1367   - DBG_Assert (succ == 1);
1368   -#endif
  1278 + optek_link_master_enable(48000);
  1279 + optek_link_enable = TRUE;
  1280 + }
1369 1281 }
1370   -
1371   - if (app_main_data.share_link_role == SL_ROLE_SLAVE)
  1282 + else if (app_main_data.share_link_role == SL_ROLE_SLAVE)
1372 1283 {
1373   - #ifdef OPTEK_LINK_SLAVE_ROLE
  1284 + u8 succ;
  1285 + struct optek_link_setting_tag optek_link_setting_s;
  1286 + memset (&optek_link_setting_s,0,sizeof(optek_link_setting_s));
1374 1287
1375   - DBG_Printf("salver\n\r");
  1288 + DBG_Printf("optek link slave enable\n\r");
1376 1289
1377 1290 if(bt_flash_is_optek_role_btaddr_present())
1378 1291 {
... ... @@ -1406,41 +1319,13 @@ void optek_link_role_init(void)
1406 1319 succ = kBtHCI_optek_link_enable(1, OPTEK_LINK_H1);
1407 1320
1408 1321 DBG_Assert (succ == 1);
  1322 +
  1323 + optek_link_enable = TRUE;
1409 1324 }
1410 1325 else
1411 1326 {
1412 1327 optek_link_role_stop();
1413 1328 }
1414   -
1415   -
1416   - #endif
1417   -
1418   - #if 0//def OPTEK_LINK_SCAN_ROLE
1419   -
1420   - optek_link_setting_s.role = OPTEK_LINK_SCAN;
1421   -
1422   - optek_link_setting_s.mode = 0; //for slave and scan role
1423   -
1424   - optek_link_setting_s.btaddr = NULL; //for master role
1425   - optek_link_setting_s.link_group = optek_link_group;
1426   - optek_link_setting_s.window = 48;
1427   - optek_link_setting_s.interval = 64;
1428   - optek_link_setting_s.tx_power = OPTEK_LINK_POWER;
1429   - optek_link_setting_s.paring_power = OPTEK_LINK_PARING_POWER;
1430   - optek_link_setting_s.max_rx_len = 0;
1431   -
1432   - optek_link_setting_s.max_multi_rx_len = NULL;
1433   -
1434   - succ = optek_link_set (&optek_link_setting_s, OPTEK_LINK_H1);
1435   - DBG_Assert (succ == 1);
1436   -
1437   - if (succ)
1438   - succ = kBtHCI_optek_link_enable(1, OPTEK_LINK_H1);
1439   -
1440   - DBG_Assert (succ == 1);
1441   -
1442   - #endif
1443   -
1444 1329 }
1445 1330
1446 1331 }
... ... @@ -1508,6 +1393,28 @@ void app_change_mode_req(u8 mode, u8 max_master_tx_len, u8 max_master_rx_len)
1508 1393 req_rxlen = max_master_rx_len;
1509 1394 }
1510 1395
  1396 +
  1397 +void app_sw_mode(void)
  1398 +{
  1399 + static U8 mode;
  1400 +
  1401 + app_cmd_DecoderExit();
  1402 +
  1403 + if (mode)
  1404 + {
  1405 + app_change_mode_req(BC_SF48K_PT5MS,100,6);
  1406 + }
  1407 + else
  1408 + {
  1409 + app_change_mode_req(GAME_HEADPHONE_PT_5MS_LP,100,50);
  1410 + }
  1411 + mode = !mode;
  1412 +
  1413 + app_media_mute_disable();
  1414 + uDecSend (DECODE_INIT, NULL);
  1415 + spk_out_sync_w_tx_status = SPK_AND_TX_SYNCING;
  1416 +}
  1417 +
1511 1418 void optek_link_cal_drift (void)
1512 1419 {
1513 1420 u32 base_cnt_rxsync_1st;
... ...
... ... @@ -25,7 +25,7 @@ void csbm_tx_init(U16 sample_rate,U8 bt_src);
25 25 void csbm_put_tx_unencoded_data(short *ptr,U16 len);
26 26 void csbm_put_tx_encoded_data(short *ptr,U16 len);
27 27 void app_optek_link_role_sw(void);
28   -void app_nav_csb_pairing(void);
  28 +void app_nav_optek_link_pairing(void);
29 29 void optek_link_master_enable(U32 sample_rate);
30 30 void optek_link_role_stop(void);
31 31 void optek_link_master_mode_sel2spr(U32 sample_rate);
... ...
... ... @@ -19,7 +19,7 @@ static const KEY_AD_ENTRY oem_main_kbd_entry0[] = {
19 19 #if 1
20 20 {(0x000 - 0x000), (0x000 + V_TOLERANCE ), APP_KEY_SOURCE}, //Source
21 21 {(0x110 - V_TOLERANCE ), (0x110 + V_TOLERANCE ), APP_KEY_PLAY}, //Play/Pause
22   - {(0x230 - V_TOLERANCE ), (0x230 + V_TOLERANCE ), APP_KEY_SOURCE}, //STOP
  22 + {(0x230 - V_TOLERANCE ), (0x230 + V_TOLERANCE ), APP_KEY_STOP}, //STOP
23 23 {(0x340 - V_TOLERANCE ), (0x340 + V_TOLERANCE ), APP_KEY_SKIPF}, //skipF
24 24 {(0x470 - V_TOLERANCE ), (0x470 + V_TOLERANCE ), APP_KEY_SKIPB}, //skipB
25 25 {(0x5A0 - V_TOLERANCE ), (0x5A0 + V_TOLERANCE ), APP_KEY_PLUS}, //Vol +
... ...
... ... @@ -339,9 +339,9 @@ void app_window_prompt_2_window_init (void)
339 339 const APP_NAV_KEY APP_NAV_AUX_KEY [] =
340 340 {
341 341 #if (defined OPTEK_LINK_ENABLE)
342   - {APP_KEY_PLAY,NULL,app_nav_csb_pairing,2000,app_optek_link_role_sw},
  342 + {APP_KEY_PLAY,NULL,app_nav_optek_link_pairing,2000,app_optek_link_role_sw},
343 343 #else
344   - {APP_KEY_PLAY,app_nav_csb_pairing,NULL,5000,enter_bt_test_mode},
  344 + {APP_KEY_PLAY,app_nav_optek_link_pairing,NULL,5000,enter_bt_test_mode},
345 345 #endif
346 346
347 347 {APP_KEY_STOP,NULL,NULL,2000,app_nav_upgrade_project},
... ... @@ -810,7 +810,7 @@ const APP_NAV_KEY APP_NAV_BT_HCI_KEY [] =
810 810 {
811 811 // {APP_KEY_PLAY,app_nav_bt_hci_play,NULL,5000,enter_bt_test_mode},
812 812 #if (defined OPTEK_LINK_ENABLE)
813   - {APP_KEY_PLAY,NULL,app_nav_csb_pairing,2000,app_optek_link_role_sw},
  813 + {APP_KEY_PLAY,NULL,app_nav_optek_link_pairing,2000,app_optek_link_role_sw},
814 814 #else
815 815 {APP_KEY_PLAY,app_nav_bt_hci_play,NULL,5000,enter_bt_test_mode},
816 816 #endif
... ...
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