flash_boot.c 26.3 KB

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// Copyright (C) Optek. 2008
//
//! \file flash_boot.c
//! \brief
//! \version 0.1
//! \date Feb, 2007
//!
//!
//

#include "c_def.h"
#include "debug.h"
#include "oem.h"

#include "regmap.h"

#include "mem_reloc.h"

#include "hw_gpio.h"
#include "hw_uart.h"

#include "app_main.h"
#include "app_gpio.h"
#include "flash_boot.h"
//#include "app_flash_program.h"


#ifdef SPI_FLASH_ENABLE
#ifdef SPI_FLASH_WINBOND
#include "SpiFlash_W25QXX.h"
#endif
#endif


//#define LIBKERNEL_TEXT_LOAD
//#define CODEC_TEXT_LOAD

#if 0
#define BDM_RODATA_LOAD
#define ALL_RODATA_LOAD

#define FLASH_PROG_TEXT_LOAD

#define BTDM_TEXT_LOAD
#define ALL_TEXT_LOAD
#endif


//#undef BOOT_FROM_FLASH

//#pragma section boot_copy_code ".copyflash"
//#pragma use_section boot_copy_code InitSdram, CopyFlash

void System_Stack_Space_Init(void) __attribute__ ((section (".flash_boot_text")));
void Sdram_Init(void) __attribute__ ((section (".flash_boot_text")));

void SpiFlash_Enable(void) __attribute__ ((section (".flash_boot_text")));
void SpiFlash_4Bit_Enable(void) __attribute__ ((section (".flash_boot_text")));

void Flash_Boot_Copy(void) __attribute__ ((section (".flash_boot_text")));
void Flash_Boot_Switch(void) __attribute__ ((section (".flash_boot_text")));

//void DataCache_Clean(void) __attribute__ ((section (".flash_boot_text")));

void main_power_on(void) __attribute__ ((section (".flash_boot_text")));

void DataCache_Clean(void) __INTERNAL_RAM_TEXT;


#if 1
/* Normal code externs */

extern U32 __internal_ram_1_rom_start[];
extern U32 __internal_ram_1_ram_start[];
extern U32 __internal_ram_1_ram_end[];

extern U32 __internal_ram_2_rom_start[];
extern U32 __internal_ram_2_ram_start[];
extern U32 __internal_ram_2_ram_end[];

extern U32 __libkernel_rom_start[];
extern U32 __libkernel_ram_start[];
extern U32 __libkernel_ram_end[];

extern U32 __flash_prog_rom_start[];
extern U32 __flash_prog_ram_start[];
extern U32 __flash_prog_ram_end[];

extern U32 __all_text_rom_start[];
extern U32 __all_text_ram_start[];
extern U32 __all_text_ram_end[];

extern U32 __lc3_common_text_rom_start[];
extern U32 __lc3_common_text_ram_start[];
extern U32 __lc3_common_text_ram_end[];

extern U32 __btdm_text_rom_start[];
extern U32 __btdm_text_ram_start[];
extern U32 __btdm_text_ram_end[];

extern U32 __btdm_rodata_ram_start[];
extern U32 __btdm_rodata_ram_end[];
extern U32 __btdm_rodata_rom_start[];

extern U32 __all_rodata_rom_start[];
extern U32 __all_rodata_ram_start[];
extern U32 __all_rodata_ram_end[];


extern U32 __data_rom_start[];
extern U32 __data_ram_start[];
extern U32 __data_ram_end[];

#ifdef OPTEK_DSRC_ENABLE
extern U32 __dsrc_data_rom_start[];
extern U32 __dsrc_data_ram_start[];
extern U32 __dsrc_data_ram_end[];
#endif


extern U32 __TEXT_ROM_START35[];
extern U32 __TEXT_START35[];
extern U32 __TEXT_START35_END[];

#endif


extern U32 SYSTEM_STACK_START[];
extern U32 SYSTEM_STACK_END[];

U8 app_defalt_poweron_souce (void);

#define SYSTEM_STACK_SPACE_TEST

void System_Stack_Space_Init(void)
{
#if 0//def SYSTEM_STACK_SPACE_TEST
	U32 count;
	U32 len;

	len = SYSTEM_STACK_END - SYSTEM_STACK_START;
	for (count=0; count < len; count++)
	{
		SYSTEM_STACK_START[count] = 0xEEFFEEFF;
	}
#endif
}

/*******************************************************************************
 *
 *   FUNCTION NAME - Sdram_Init
 *
 *   ARGUMENTS     - None
 *
 *   RETURN VALUE  - None
 *
 *******************************************************************************
 *
 *   DESCRIPTION
 *   This function initializes the SDRAM.
 *
 ******************************************************************************/

#ifdef OPTEK_SOC2_VERSION
#define SDRAM_PIN_GPIO1_MASK     0xFFFFF800
#define SDRAM_PIN_GPIO2_MASK     0x000FFFFF
#else
#define SDRAM_PIN_GPIO1_MASK     0xFFFFF800
#define SDRAM_PIN_GPIO2_MASK     0xFFFFFFFF
#endif

#define SDRAM_CKE_PIN        GPIO43_MASK

#define SDRAM_CKE_LOW       GPIO1_FUNCTION_ENABLE2(SDRAM_CKE_PIN); \
							GPIO1_OUTPUT_ENABLE(SDRAM_CKE_PIN); \
							GPIO1_OUTPUT_CLR(SDRAM_CKE_PIN)

#define SDRAM_CKE_HIGH      GPIO1_FUNCTION_ENABLE2(SDRAM_CKE_PIN); \
							GPIO1_OUTPUT_ENABLE(SDRAM_CKE_PIN); \
							GPIO1_OUTPUT_SET(SDRAM_CKE_PIN)

#define SDRAM_CKE_INPUT     GPIO1_FUNCTION_ENABLE2(SDRAM_CKE_PIN); \
							GPIO1_OUTPUT_DISABLE(SDRAM_CKE_PIN)

void Sdram_Init(void)
{
#if 0//def BOOT_FROM_FLASH
	U32 temp;

#ifdef OPTEK_SOC2_VERSION
	REG_GPIO1_FUNC |= SDRAM_PIN_GPIO1_MASK;

	REG_GPIO2_FUNC |= SDRAM_PIN_GPIO2_MASK;

#if defined(SDRAM_16M)
//	REG_MISC_SDRAM_CFG1 = 0x246C01;	//16M sdram
	REG_MISC_SDRAM_CFG1 = 0x24A501;	//16M sdram 0010 0100 1010 0101 0001
#elif defined(SDRAM_64M)
//	REG_MISC_SDRAM_CFG1 = 0x246C09;	//64M sdram
	REG_MISC_SDRAM_CFG1 = 0x24A509;	//64M sdram 0010 0100 1010 0101 0001
#elif defined(SDRAM_128M)
//	REG_MISC_SDRAM_CFG1 = 0x246C11;	//128M sdram
	REG_MISC_SDRAM_CFG1 = 0x24A511;	//128M sdram 0010 0100 1010 0101 0001
#elif defined(SDRAM_256M)
//	REG_MISC_SDRAM_CFG1 = 0x246C19;	//256M sdram
	REG_MISC_SDRAM_CFG1 = 0x24A519;	//128M sdram 0010 0100 1010 0101 0001
#else
#error Must Define Sdram Size.
#endif

	temp = REG_MISC_SDRAM_CFG2;
	temp &= 0xffff0000;
//	temp |= 0x1400;		//wait 1 clk, refresh 800
	temp |= 0x1200;		//wait 1 clk, refresh 96M sysclk

//	temp |= 0x6400;		//wait 6 clk, refresh 400
	REG_MISC_SDRAM_CFG2 = temp;

	asm("nop");

#else
//	temp = REG_GPIO1_FUNC;
//	if (temp != ~SDRAM_PIN_GPIO1_MASK)
	{
		REG_GPIO1_FUNC &= ~SDRAM_PIN_GPIO1_MASK;
	}

//	temp = REG_GPIO2_FUNC;
//	if (temp != ~SDRAM_PIN_GPIO2_MASK)
	{
		REG_GPIO2_FUNC &= ~SDRAM_PIN_GPIO2_MASK;
	}

//	temp = REG_MISC_SDRAM_CFG1;
//	asm("nop");

#if defined(SDRAM_16M)
//	REG_MISC_SDRAM_CFG1 = 0x246C01;	//16M sdram
	REG_MISC_SDRAM_CFG1 = 0x24A501;	//16M sdram 0010 0100 1010 0101 0001
#elif defined(SDRAM_64M)
//	REG_MISC_SDRAM_CFG1 = 0x246C09;	//64M sdram
	REG_MISC_SDRAM_CFG1 = 0x24A509;	//64M sdram 0010 0100 1010 0101 0001
#elif defined(SDRAM_128M)
//	REG_MISC_SDRAM_CFG1 = 0x246C11;	//128M sdram
	REG_MISC_SDRAM_CFG1 = 0x24A511;	//128M sdram 0010 0100 1010 0101 0001
#elif defined(SDRAM_256M)
//	REG_MISC_SDRAM_CFG1 = 0x246C19;	//256M sdram
	REG_MISC_SDRAM_CFG1 = 0x24A519;	//128M sdram 0010 0100 1010 0101 0001
#else
#error Must Define Sdram Size.
#endif

	temp = REG_MISC_SDRAM_CFG2;
//	asm("nop");
	temp &= 0xffff0000;
//	temp |= 0x1400;		//wait 1 clk, refresh 800
	temp |= 0x1200;		//wait 1 clk, refresh 96M sysclk

//	temp |= 0x6400;		//wait 6 clk, refresh 400
	REG_MISC_SDRAM_CFG2 = temp;
#endif

#else

#if 0
	//Sdram Disable
	REG_MISC_SDRAM_CFG1 = 0;
	asm("nop");

	SDRAM_CKE_LOW;
#else

#if 0
	//Sdram Disable
	//REG_MISC_SDRAM_CFG1 = 0;
	asm("nop");
	asm("nop");
	asm("nop");
	asm("nop");
	asm("nop");

	SDRAM_CKE_LOW;
#else
	//REG_MISC_SDRAM_CFG1 &= ~0x01;
#endif

#endif

#endif
}

void SpiFlash_Enable(void)
{
#ifdef SPI_FLASH_ENABLE

#ifdef SPI_FLASH_WINBOND
	U32 tmp;

	tmp = REG_MISC_SDRAM_CFG2;

	tmp |= (1 << 16);

	REG_MISC_SDRAM_CFG2 = tmp;
#endif //SPI_FLASH_WINBOND

#endif //SPI_FLASH_ENABLE
}

//Enable 4 bit Flash
void SpiFlash_4Bit_Enable (void)
{
#ifdef SPI_FLASH_ENABLE

#ifdef SPI_FLASH_WINBOND
	U8 temp;

	temp = ADDR_SPI_STATUS2;

	if ( (temp & 0x02) == 0x00 )
	{
		//spi flash is 1 bit mode, set it to 4 bit
		ADDR_SPI_WR_ENABLE = 0x00;

		SFLASH_QUAD_ENABLE;

		while (ADDR_SPI_STATUS & SPI_FLASH_BUSY_MASK);

		temp = ADDR_SPI_STATUS2;
	}
#endif //SPI_FLASH_WINBOND

#endif //SPI_FLASH_ENABLE
}

extern U32 SDRAM_START_ADDR[];
extern U32 SFLASH_START_ADDR[];

void DataCache_Clean(void)
{
#if 0

#if 0//def SDRAM_ENABLE
	U16 i;
	volatile U32 *pAddr = (U32 *) SDRAM_START_ADDR;
	volatile U32 tmp;

	for(i=0; i<(1024*4); i++)
	{
		tmp = *pAddr++;
	}
#else
	U16 i;
	volatile U32 *pAddr = (U32 *) SFLASH_START_ADDR;
	volatile U32 tmp;

	for(i=0; i<(1024*4); i++)
	{
		tmp = *pAddr++;
	}
#endif

#endif
}

/*******************************************************************************
 *
 *   FUNCTION NAME - CopyFlash
 *
 *   ARGUMENTS     - None
 *
 *   RETURN VALUE  - None
 *
 *******************************************************************************
 *
 *   DESCRIPTION
 *   This function copies sections from Flash memory to SDRAM and SRAM, as
 *   per sections defined in the memory control file.
 *
 ******************************************************************************/

extern U8 SDRAM_ICON_RODATA_START[];
extern U8 SDRAM_ICON_RODATA_END[];
extern U8 ROM_ICON_RODATA_START[];
extern U8 ROM_ICON_RODATA_END[];

extern U8 SDRAM_FONT_RODATA_START[];
extern U8 SDRAM_FONT_RODATA_END[];
extern U8 ROM_FONT_RODATA_START[];
extern U8 ROM_FONT_RODATA_END[];

void Flash_Boot_Copy(void)
{
#if 1//def BOOT_FROM_FLASH
	U32 count;
	U32 len;
	//volatile U32 *p1;
	//volatile U32 *p2;


	//.interal_ram_0_text
	/*len = __TEXT_START29_END - __TEXT_START24;
	for (count=0; count < len; count++)
	{
		__TEXT_START29[count] = __TEXT_ROM_START29[count];
	}*/

	//.internal_ram_1_text
	if (!(__internal_ram_1_ram_start == __internal_ram_1_rom_start))
	{
		len = __internal_ram_1_ram_end - __internal_ram_1_ram_start;
		//p1 = __internal_ram_1_ram_start;
		//p2 = __internal_ram_1_rom_start;
		for (count=0; count < len; count++)
		{
			__internal_ram_1_ram_start[count] = __internal_ram_1_rom_start[count];
		}
	}

	if (!(__internal_ram_2_ram_start == __internal_ram_2_rom_start))
	{
		len = __internal_ram_2_ram_end - __internal_ram_2_ram_start;
		//p1 = __internal_ram_1_ram_start;
		//p2 = __internal_ram_1_rom_start;
		for (count=0; count < len; count++)
		{
			__internal_ram_2_ram_start[count] = __internal_ram_2_rom_start[count];
		}
	}

#if (defined LC3_DECODE_ENABLE || defined LC3_ENCODE_ENABLE)
	len = __lc3_common_text_ram_end - __lc3_common_text_ram_start;
	CFasm_memcpy(__lc3_common_text_ram_start, __lc3_common_text_rom_start, len*4);
#endif

#ifdef FLASH_PROG_TEXT_LOAD
	//.flash_prog_text
	len = __flash_prog_ram_end - __flash_prog_ram_start;
	CFasm_memcpy(__flash_prog_ram_start, __flash_prog_rom_start, len*4);
#endif

#if 1
	//.libkernel_text
	len = __libkernel_ram_end - __libkernel_ram_start;
	CFasm_memcpy(__libkernel_ram_start, __libkernel_rom_start, len*4);
#endif

#if 1
	//.libkernel_text
	len = __libkernel_ram_end - __libkernel_ram_start;
	CFasm_memcpy(__libkernel_ram_start, __libkernel_rom_start, len*4);
#endif


#ifdef CODEC_TEXT_LOAD
	//.codec_text
	len = __TEXT_START25_END - __TEXT_START25;
	CFasm_memcpy(__TEXT_START25, __TEXT_ROM_START25, len*4);
#endif


#ifdef BTDM_TEXT_LOAD
	//.btdm_text
	len = __btdm_text_ram_end - __btdm_text_ram_start;
	CFasm_memcpy(__btdm_text_ram_start, __btdm_text_rom_start, len*4);
#endif


#ifdef ALL_TEXT_LOAD
	//.all_text
	len = __all_text_ram_end - __all_text_ram_start;
	CFasm_memcpy(__all_text_ram_start, __all_text_rom_start, len*4);
#endif


#if 0
	//.libkernel_rodata
	len = __TEXT_START20_END - __TEXT_START20;
	CFasm_memcpy(__TEXT_START20, __TEXT_ROM_START20, len*4);
#endif

#if 0
	//.libmp3_dec_rodata
	len = __TEXT_START21_END - __TEXT_START21;
	CFasm_memcpy(__TEXT_START21, __TEXT_ROM_START21, len*4);


	//.libwma_dec_rodata
	len = __TEXT_START22_END - __TEXT_START22;
	CFasm_memcpy(__TEXT_START22, __TEXT_ROM_START22, len*4);
#endif

#if 0
	//.libmp3_enc_rodata
	len = __TEXT_START28_END - __TEXT_START28;
	CFasm_memcpy(__TEXT_START28, __TEXT_ROM_START28, len*4);
#endif

#ifdef UPGRADE_RODATA_LOAD
	//.upgrade_rodata
	len = __TEXT_START26_END - __TEXT_START26;
	CFasm_memcpy(__TEXT_START26, __TEXT_ROM_START26, len*4);
#endif

#ifdef BDM_RODATA_LOAD
	//.all_rodata
	len = __btdm_rodata_ram_end - __btdm_rodata_ram_start;
	CFasm_memcpy(__btdm_rodata_ram_start, __btdm_rodata_rom_start, len*4);
#endif


#ifdef ALL_RODATA_LOAD
	//.all_rodata
	len = __all_rodata_ram_end - __all_rodata_ram_start;
	CFasm_memcpy(__all_rodata_ram_start, __all_rodata_rom_start, len*4);
#endif


	//.data
	len = __data_ram_end - __data_ram_start;
	CFasm_memcpy(__data_ram_start, __data_rom_start, len*4);

#if 0//def OPTEK_DSRC_ENABLE
	//.dsrc_data_tbl
	len = __dsrc_data_ram_end - __dsrc_data_ram_start;
	CFasm_memcpy(__data_ram_start, __dsrc_data_rom_start, len*4);
#endif


#if 0
	//.libkernel_bss
	len = __TEXT_START35_END - __TEXT_START35;
	for (count=0; count < len; count++)
	{
		__TEXT_START35[count] = 0;
	}
#endif


#ifdef FONT_IN_SFLASH
	//icon_rodata
	//len = ROM_ICON_RODATA_END - ROM_ICON_RODATA_START;
	//CFasm_memcpy(SDRAM_ICON_RODATA_START, ROM_ICON_RODATA_START, len);

	//len = ROM_FONT_RODATA_END - ROM_FONT_RODATA_START;
	//CFasm_memcpy(SDRAM_FONT_RODATA_START, ROM_FONT_RODATA_START, len);
#endif

	asm("nop");

#else

#if 1
	U32 count;
	U32 len;
	volatile U32 *p1;
	volatile U32 *p2;


	//.interal_ram_0_text
	/*len = __TEXT_START29_END - __TEXT_START24;
	for (count=0; count < len; count++)
	{
		__TEXT_START29[count] = __TEXT_ROM_START29[count];
	}*/


	//.internal_ram_1_text
	if (!(__internal_ram_1_ram_start == __internal_ram_1_rom_start))
	{
		len = __internal_ram_1_ram_end - __internal_ram_1_ram_start;
		//p1 = __internal_ram_1_ram_start;
		//p2 = __internal_ram_1_rom_start;
		for (count=0; count < len; count++)
		{
			__internal_ram_1_ram_start[count] = __internal_ram_1_rom_start[count];
		}
	}


	//.flash_prog_text
	if (!(__flash_prog_ram_start == __flash_prog_rom_start))
	{
		len = __flash_prog_ram_end - __flash_prog_ram_start;
		CFasm_memcpy(__flash_prog_ram_start, __flash_prog_rom_start, len*4);
	}


	//.libkernel_text
	if (!(__libkernel_ram_start == __libkernel_rom_start))
	{
		len = __libkernel_ram_end - __libkernel_ram_start;
		/*for (count=0; count < len; count++)o
		{
			__libkernel_ram_start[count] = __libkernel_rom_start[count];
		}*/
		CFasm_memcpy(__libkernel_ram_start, __libkernel_rom_start, len*4);
	}


	//.data
	len = __data_ram_end - __data_ram_start;
	CFasm_memcpy(__data_ram_start, __data_rom_start, len*4);

#if 0
	//.libkernel_bss
	len = __TEXT_START35_END - __TEXT_START35;
	for (count=0; count < len; count++)
	{
		__TEXT_START35[count] = 0;
	}
#endif

#ifdef FONT_IN_SFLASH
	//icon_rodata
	//len = ROM_ICON_RODATA_END - ROM_ICON_RODATA_START;
	//CFasm_memcpy(SDRAM_ICON_RODATA_START, ROM_ICON_RODATA_START, len);

	//len = ROM_FONT_RODATA_END - ROM_FONT_RODATA_START;
	//CFasm_memcpy(SDRAM_FONT_RODATA_START, ROM_FONT_RODATA_START, len);
#endif //FONT_IN_SFLASH

	asm("nop");
#endif

#endif //BOOT_FROM_FLASH
}


//#pragma section boot_switch_code ".boot_switch"
//#pragma use_section boot_switch_code boot_switch

extern U32 ROM_MP3_START_ADDR[];
#define HW_RST_MASK		0x80
#define SW_RST_MASK		0x20

void Flash_Boot_Switch(void)
{
#if 0
	U8 i;
	U8 wBuf[7];
	U8 rBuf[7];
	U8 page_addr;
	//U16 *pFlashAddr = (U16 *)ROM_MP3_START_ADDR;
	U16 tmp;

#ifdef FLASH_BOOT1_CONFIG_USED
	U8 *pFlashBootConfig = (U8 *)flash_boot1_config;
#else
	U8 *pFlashBootConfig = (U8 *)flash_boot_config;
#endif


#if 1//def POWER_RELAY_CONTROL
	//main_power_on();
#else
	POWER_ON;
	//STANDBY_POWER_ON;
#endif

#ifndef BOOT_FROM_FLASH

#if 1
	sram_boot_config[0] = 'B';
	sram_boot_config[1] = 'T';
	sram_boot_config[2] = ' ';
	sram_boot_config[3] = 'A';
	sram_boot_config[4] = 'P';
	sram_boot_config[5] = 'P';
	sram_boot_config[6] = 'R';
	sram_boot_config[7] = 'E';
	sram_boot_config[8] = 'S';

/*
	sram_boot_config[0] = 'A';
	sram_boot_config[1] = 'U';
	sram_boot_config[2] = 'X';
	sram_boot_config[3] = 'A';
	sram_boot_config[4] = 'P';
	sram_boot_config[5] = 'P';
	sram_boot_config[6] = 'R';
	sram_boot_config[7] = 'E';
	sram_boot_config[8] = 'S';
*/

#else

	sram_boot_config[0] = 'B';
	sram_boot_config[1] = 'T';
	sram_boot_config[2] = ' ';
	sram_boot_config[3] = 'A';
	sram_boot_config[4] = 'P';
	sram_boot_config[5] = 'P';
	sram_boot_config[6] = '1';
	sram_boot_config[7] = 'S';
	sram_boot_config[8] = 'T';

	sram_boot_config[0] = 'A';
	sram_boot_config[1] = 'U';
	sram_boot_config[2] = 'X';
	sram_boot_config[3] = 'A';
	sram_boot_config[4] = 'P';
	sram_boot_config[5] = 'P';
	sram_boot_config[6] = 'R';
	sram_boot_config[7] = 'E';
	sram_boot_config[8] = 'S';
#endif


#if 0//fro test
	//sram_boot_config[POWER_ON_FROM_ECO_OFFSET] = APP_IPOD_STANDBY_FLAG;
	//sram_boot_config[POWER_ON_FROM_ECO_OFFSET] = APP_CLOCK_VIEW_FLAG;
	sram_boot_config[POWER_ON_FROM_ECO_OFFSET] = APP_NORMAL_FLAG;
	//sram_boot_config[POWER_ON_FROM_ECO_OFFSET] = APP_CLOCK_VIEW_FLAG;
#endif

#endif

#ifdef BOOT_FROM_FLASH
	/*if (MBAR_RSR & HRST_MASK)
	{
		//internal sram boot tag
		sram_boot_config[0] = 0;
		sram_boot_config[1] = 0;
		sram_boot_config[2] = 0;
		sram_boot_config[3] = 0;
		sram_boot_config[4] = 0;
		sram_boot_config[5] = 0;
		//sram_boot_config[WATCHDOG_OFFSET] = TRUE;
	}*/
#endif


#ifdef UPGRADE_PROJECT_ENABLE

	//firt check boot tag in sram
	if (sram_boot_config[0] == 'U' && sram_boot_config[1] == 'P' &&
		sram_boot_config[2] == 'G')
	{
#ifndef UPGRADE_PROJECT_FIRST_START
		if (sram_boot_config[3] == 'U' && sram_boot_config[4] == 'S' &&
			sram_boot_config[5] == 'B')
		{
			//app_main_data.media = MEDIA_USB_DEVICE;

			if (sram_boot_config[6] == 'E' && sram_boot_config[7] == 'F' &&
				sram_boot_config[8] == 'A')
			{
				//app_main_data.flashEraseMode = FLASH_ERASE_ALL;
			}
			else
			{
				//app_main_data.flashEraseMode = FLASH_ERASE_PARTIAL;
			}

			boot_upgrade();
			return;
		}
		else if (sram_boot_config[3] == ' ' && sram_boot_config[4] == 'S' &&
				sram_boot_config[5] == 'D')
		{
			//app_main_data.media = MEDIA_SDMMC;

			if (sram_boot_config[6] == 'E' && sram_boot_config[7] == 'F' &&
				sram_boot_config[8] == 'A')
			{
				//app_main_data.flashEraseMode = FLASH_ERASE_ALL;
			}
			else
			{
				//app_main_data.flashEraseMode = FLASH_ERASE_PARTIAL;
			}

			boot_upgrade();
			return;
		}
		else if (sram_boot_config[3] == 'S' && sram_boot_config[4] == 'u' &&
				sram_boot_config[5] == 'c')
		{
			app_main_data.media = MEDIA_UPGRADE;
			return;
		}
#else
		if (sram_boot_config[3] == 'S' && sram_boot_config[4] == 'u' &&
				sram_boot_config[5] == 'c')
		{
			app_main_data.media = MEDIA_UPGRADE;
			return;
		}
#endif //UPGRADE_PROJECT_FIRST_START
		else if (sram_boot_config[3] == 'E' && sram_boot_config[4] == 'r' &&
				sram_boot_config[5] == 'r')
		{
			app_main_data.media = MEDIA_UPGRADE;
			return;
		}
		else
		{
			//app_main_data.media = MEDIA_SDMMC;
			asm("nop");

			//boot_upgrade();
			//return;
		}
	}
#endif //UPGRADE_PROJECT_ENABLE


#if 1
	//jump MP3CD project
	if (sram_boot_config[0] == 'C' && sram_boot_config[1] == 'D' &&
		sram_boot_config[2] == ' ' && sram_boot_config[3] == 'A' &&
		sram_boot_config[4] == 'P' && sram_boot_config[5] == 'P')
	{
		//app_main_data.media = MEDIA_CD;
		return;
	}
	else if (sram_boot_config[0] == 'U' && sram_boot_config[1] == 'S' &&
		sram_boot_config[2] == 'B' && sram_boot_config[3] == 'A' &&
		sram_boot_config[4] == 'P' && sram_boot_config[5] == 'P')
	{
		app_main_data.media = MEDIA_USB_DEVICE;
		return;
	}
#ifdef SD_ENABLE
	else if (sram_boot_config[0] == 'S' && sram_boot_config[1] == 'D' &&
		sram_boot_config[2] == ' ' && sram_boot_config[3] == 'A' &&
		sram_boot_config[4] == 'P' && sram_boot_config[5] == 'P')
	{
		app_main_data.media = MEDIA_SDMMC;
		return;
	}
#endif
#if 0//def BLUETOOTH_MODULE
	else if (sram_boot_config[0] == 'B' && sram_boot_config[1] == 'T' &&
		sram_boot_config[2] == ' ' && sram_boot_config[3] == 'A' &&
		sram_boot_config[4] == 'P' && sram_boot_config[5] == 'P')
	{
		app_main_data.media = MEDIA_BLUETOOTH;
		return;
	}
#endif
#ifdef BT_HCI_ENABLE
	else if (sram_boot_config[0] == 'H' && sram_boot_config[1] == 'C' &&
	         sram_boot_config[2] == 'I' && sram_boot_config[3] == 'A' &&
	         sram_boot_config[4] == 'P' && sram_boot_config[5] == 'P')
	{
		app_main_data.media = MEDIA_BT_HCI;
		return;
	}
#endif
#if 0
	else if (sram_boot_config[0] == 'I' && sram_boot_config[1] == 'P' &&
		sram_boot_config[2] == 'H' && sram_boot_config[3] == 'A' &&
		sram_boot_config[4] == 'P' && sram_boot_config[5] == 'P')
	{
		app_main_data.media = MEDIA_IPHONE;
		return;
	}
#endif
#if (defined TUNER_MODULE || defined DAB_MODULE)
	else if (sram_boot_config[0] == 'F' && sram_boot_config[1] == 'M' &&
		sram_boot_config[2] == ' ' && sram_boot_config[3] == 'A' &&
		sram_boot_config[4] == 'P' && sram_boot_config[5] == 'P')
	{
#if defined TUNER_MODULE
		app_main_data.media = MEDIA_TUNER;
		app_main_data.tuner_band = SELECTED_BAND_FM;
#elif defined DAB_MODULE
		app_main_data.media = MEDIA_DAB;
		app_main_data.tuner_band = SELECTED_BAND_FM;
#endif
		return;
	}
#endif
#ifdef TUNER_MODULE
	else if (sram_boot_config[0] == 'A' && sram_boot_config[1] == 'M' &&
		sram_boot_config[2] == ' ' && sram_boot_config[3] == 'A' &&
		sram_boot_config[4] == 'P' && sram_boot_config[5] == 'P')
	{
		app_main_data.media = MEDIA_TUNER;
		app_main_data.tuner_band = SELECTED_BAND_MW;
		return;
	}
#endif
#ifdef DAB_MODULE
	else if (sram_boot_config[0] == 'D' && sram_boot_config[1] == 'A' &&
		sram_boot_config[2] == 'B' && sram_boot_config[3] == 'A' &&
		sram_boot_config[4] == 'P' && sram_boot_config[5] == 'P')
	{
		app_main_data.media = MEDIA_DAB;
		app_main_data.tuner_band = sram_boot_config[TN_BAND_OFFSET];
		return;
	}
#endif
	else if (sram_boot_config[0] == 'A' && sram_boot_config[1] == 'U' &&
		sram_boot_config[2] == 'X' && sram_boot_config[3] == 'A' &&
		sram_boot_config[4] == 'P' && sram_boot_config[5] == 'P')
	{
		app_main_data.media = MEDIA_AUX;
		return;
	}
/*	else if (sram_boot_config[0] == 'I' && sram_boot_config[1] == 'P' &&
		sram_boot_config[2] == 'H' && sram_boot_config[3] == 'S' &&
		sram_boot_config[4] == 'D' && sram_boot_config[5] == 'B')
	{
		app_main_data.standby_status = TRUE;
		app_main_data.media = MEDIA_IPHONE;
		return;
	}
	else if (sram_boot_config[0] == 'A' && sram_boot_config[1] == 'L' &&
		sram_boot_config[2] == 'M' && sram_boot_config[3] == 'S' &&
		sram_boot_config[4] == 'B')
	{
		app_main_data.standby_status = TRUE;
		app_main_data.media = sram_boot_config[5];
		return;
	}
	else if (sram_boot_config[0] == 'C' && sram_boot_config[1] == 'L' &&
		sram_boot_config[2] == 'K' && sram_boot_config[3] == 'S' &&
		sram_boot_config[4] == 'B')
	{
		app_main_data.standby_status = TRUE;
		app_main_data.media = sram_boot_config[5];
		return;
	}*/
#endif


	//second check boot tag in flash
	if (pFlashBootConfig[0] == 'C' && pFlashBootConfig[1] == 'D' &&
		pFlashBootConfig[2] == ' ' && pFlashBootConfig[3] == 'A' &&
		pFlashBootConfig[4] == 'P' && pFlashBootConfig[5] == 'P')
	{
		sram_boot_config[6] = '1';
		sram_boot_config[7] = 'S';
		sram_boot_config[8] = 'T';

#ifndef BOOT_FROM_FLASH
#ifdef CD_ENABLE
		app_main_data.media = MEDIA_CD;
#else
		app_main_data.media = MEDIA_USB_DEVICE;
#endif
#endif
	}
	else if (pFlashBootConfig[0] == 'U' && pFlashBootConfig[1] == 'S' &&
		pFlashBootConfig[2] == 'B' && pFlashBootConfig[3] == 'A' &&
		pFlashBootConfig[4] == 'P' && pFlashBootConfig[5] == 'P')
	{
		sram_boot_config[6] = '1';
		sram_boot_config[7] = 'S';
		sram_boot_config[8] = 'T';

		app_main_data.media = MEDIA_USB_DEVICE;
	}
#ifdef SD_ENABLE
	else if (pFlashBootConfig[0] == 'S' && pFlashBootConfig[1] == 'D' &&
		pFlashBootConfig[2] == ' ' && pFlashBootConfig[3] == 'A' &&
		pFlashBootConfig[4] == 'P' && pFlashBootConfig[5] == 'P')
	{
		sram_boot_config[6] = '1';
		sram_boot_config[7] = 'S';
		sram_boot_config[8] = 'T';

		app_main_data.media = MEDIA_SDMMC;
	}
#endif
#ifdef BLUETOOTH_MODULE
	else if (pFlashBootConfig[0] == 'B' && pFlashBootConfig[1] == 'T' &&
		pFlashBootConfig[2] == ' ' && pFlashBootConfig[3] == 'A' &&
		pFlashBootConfig[4] == 'P' && pFlashBootConfig[5] == 'P')
	{
		sram_boot_config[6] = '1';
		sram_boot_config[7] = 'S';
		sram_boot_config[8] = 'T';

		app_main_data.media = MEDIA_BLUETOOTH;
	}
#endif
#ifdef BT_HCI_ENABLE
	else if (pFlashBootConfig[0] == 'H' && pFlashBootConfig[1] == 'C' &&
		pFlashBootConfig[2] == 'I' && pFlashBootConfig[3] == 'A' &&
		pFlashBootConfig[4] == 'P' && pFlashBootConfig[5] == 'P')
	{
		sram_boot_config[6] = '1';
		sram_boot_config[7] = 'S';
		sram_boot_config[8] = 'T';

		app_main_data.media = MEDIA_BT_HCI;
	}
#endif
#if 0
	else if (pFlashBootConfig[0] == 'I' && pFlashBootConfig[1] == 'P' &&
		pFlashBootConfig[2] == 'H' && pFlashBootConfig[3] == 'A' &&
		pFlashBootConfig[4] == 'P' && pFlashBootConfig[5] == 'P')
	{
		sram_boot_config[6] = '1';
		sram_boot_config[7] = 'S';
		sram_boot_config[8] = 'T';

		app_main_data.media = MEDIA_IPHONE;
	}
#endif
	else if (pFlashBootConfig[0] == 'F' && pFlashBootConfig[1] == 'M' &&
		pFlashBootConfig[2] == ' ' && pFlashBootConfig[3] == 'A' &&
		pFlashBootConfig[4] == 'P' && pFlashBootConfig[5] == 'P')
	{
		sram_boot_config[6] = '1';
		sram_boot_config[7] = 'S';
		sram_boot_config[8] = 'T';

		app_main_data.media = MEDIA_TUNER;
	}
	else if (pFlashBootConfig[0] == 'A' && pFlashBootConfig[1] == 'M' &&
		pFlashBootConfig[2] == ' ' && pFlashBootConfig[3] == 'A' &&
		pFlashBootConfig[4] == 'P' && pFlashBootConfig[5] == 'P')
	{
		sram_boot_config[6] = '1';
		sram_boot_config[7] = 'S';
		sram_boot_config[8] = 'T';

		app_main_data.media = MEDIA_TUNER;
	}
	else
	{
#if 1
		app_main_data.media = app_defalt_poweron_souce ();

		sram_boot_config[6] = '1';
		sram_boot_config[7] = 'S';
		sram_boot_config[8] = 'T';
#else
		sram_boot_config[0] = 'U';
		sram_boot_config[1] = 'P';
		sram_boot_config[2] = 'G';
		sram_boot_config[3] = 'U';
		sram_boot_config[4] = 'S';
		sram_boot_config[5] = 'B';
		sram_boot_config[6] = 'E';
		sram_boot_config[7] = 'F';
		sram_boot_config[8] = 'P';

		//boot_upgrade();
#endif
	}
#endif
}


#if 1//def POWER_RELAY_CONTROL

//52.00us at 24 Mhz
#define LOOP_24MHZ_52US_CNT1		(4960/4)

//52.00us at 96 Mhz
#define LOOP_96MHZ_52US_CNT1		4960

void main_power_on(void)
{
#if 0
	U32 len;
	U32 count;

	//POWER_ON;
	//STANDBY_POWER_ON;
#if defined POWER_PIN_USED_GROUP_0
	gpio0_ClrOutput_for_no_os(POWER_PIN);
	gpio0_SetOutputEnable_for_no_os(POWER_PIN);
	gpio0_SetFunction_for_no_os(POWER_PIN, TRUE);
#elif defined POWER_PIN_USED_GROUP_1
	gpio1_ClrOutput_for_no_os(POWER_PIN);
	gpio1_SetOutputEnable_for_no_os(POWER_PIN);
	gpio1_SetFunction_for_no_os(POWER_PIN, TRUE);
#endif


#if 1
	//.internal_ram_1_text
	len = __internal_ram_1_ram_end - __internal_ram_1_ram_start;
	//p1 = __internal_ram_1_ram_start;
	//p2 = __internal_ram_1_rom_start;
	for (count=0; count < len; count++)
	{
		__internal_ram_1_ram_start[count] = __internal_ram_1_rom_start[count];
	}

	//delay 50ms
	//delay_loop( ((LOOP_24MHZ_52US_CNT1 * 20) * 50) );
	//delay 25ms
	//delay_loop( ((LOOP_24MHZ_52US_CNT1 * 20) * 25) );
	//delay 10ms
	//delay_loop( ((LOOP_24MHZ_52US_CNT1 * 20) * 10) );
#ifdef SHARP_KP82
	//delay 350ms * 1
	delay_loop( ((LOOP_24MHZ_52US_CNT1 * 20) * 350) );
#else
	//delay 50ms
	delay_loop( ((LOOP_24MHZ_52US_CNT1 * 20) * 50) );

	//delay 300ms * 1
	//delay_loop( ((LOOP_24MHZ_52US_CNT1 * 20) * 300) );
#endif

	//delay 400ms
	//delay_loop( ((LOOP_24MHZ_52US_CNT1 * 20) * 400) );

	//delay 3s
	//delay_loop( ((LOOP_24MHZ_52US_CNT1 * 20) * 3000) );
	//delay 2s
	//delay_loop( ((LOOP_24MHZ_52US_CNT1 * 20) * 2000) );
	//delay 1s
	//delay_loop( ((LOOP_24MHZ_52US_CNT1 * 20) * 1000) );
#endif

#endif
}
#endif