hw_uart.h
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#ifndef _HW_UART_H
#define _HW_UART_H
#define UART0_TX GPIO0_01_INDEX //[0][0]
#define UART0_RX GPIO0_02_INDEX //[0][1]
#define UART1_TX 0//GPIO0_10_INDEX //[0][10]
#define UART1_RX 0//GPIO0_11_INDEX //[0][11]
#define UART2_TX 0//GPIO0_09_INDEX //[0][9]
#define UART2_RX 0//GPIO0_26_INDEX //??
typedef struct {
U32 control;
U32 divisor;
U32 status;
U32 intEnable;
#ifdef OPTEK_SOC2_VERSION
U32 idel;
#else
U32 intStat;
#endif
U32 txBuf;
U32 rxBuf;
U32 version;
} UART_REGISTERS;
// control
#define CTL_TX_ENA (1 << 0)
#define CTL_RX_ENA (1 << 1)
#define CTL_RESET (1 << 2)
#define CTL_PARITY_MASK (3 << 3)
#define CTL_PARITY_NON (0)
#define CTL_PARITY_EVEN (1 << 3)
#define CTL_PARITY_ODD (2 << 3)
#define CTL_TX_FIFO_RESET (1 << 5)
#define CTL_RX_FIFO_RESET (1 << 6)
// status
#define STAT_TX_BUF_EMPTY (1 <<0)
#define STAT_TX_BUF_HALF_EMPTY (1 <<1)
#define STAT_TX_BUF_FULL (1 <<2)
#define STAT_RX_BUF_EMPTY (1 <<3)
#define STAT_RX_BUF_NOT_EMPTY (1 <<4)
#define STAT_RX_BUF_FULL (1 <<5)
#define STAT_RX_BUF_HALF_FULL (1 <<6)
#define STAT_RX_OVERRUN (1 <<7)
#define STAT_PARITY_ERR (1 <<8)
#define STAT_FRAME_ERR (1 <<9)
// intEnable/intStat
#define INTCON_UART0 (1 << 0)
#define INTCON_UART1 (1 << 0)
#define UART_INT_ENABLE( x ) ( REG_INTCON_INT_ENA |= x )
#define UART_INT_DISABLE( x ) ( REG_INTCON_INT_ENA &= ~x )
#define INT_TX_BUF_EMPTY (1 << 0)
#define INT_TX_BUF_HALF_EMPTY (1 << 1)
#define INT_TX_BUF_FULL (1 << 2)
#define INT_RX_BUF_EMPTY (1 << 3)
#define INT_RX_BUF_NOT_EMPTY (1 << 4)
#define INT_RX_BUF_FULL (1 << 5)
#define INT_RX_BUF_HALF_FULL (1 << 6)
#define INT_RX_OVERRUN (1 << 7)
#define INT_ERR (1 << 8)
#ifdef OPTEK_SOC2_VERSION
#define UART_FIFO_SIZE 64 //byte
#else
#define UART_FIFO_SIZE 16 //byte
#endif
#define UART_FIFO_HALF_SIZE (UART_FIFO_SIZE/2)
//#define DEFAULT_BAUD 9600
//#define DEFAULT_BAUD 19200
//#define DEFAULT_BAUD 38400
//#define DEFAULT_BAUD 57600
#define DEFAULT_BAUD 115200
//#define DEFAULT_BAUD 460800
//#define DEFAULT_BAUD 921600
#define UART_BT_HCI_INIT_BAUD 115200
//#define UART_BT_HCI_BAUD 921600
#define UART_BT_HCI_BAUD 921600*2
//#define UART_BT_HCI_BAUD 0x0030d400
#define UART_BT_HCI_TEST_BAUD 921600*2
//#define UART1_DEFAULT_BAUD 38400
#define UART1_DEFAULT_BAUD 115200
#define UART2_DEFAULT_BAUD 115200
typedef enum
{
BAUD_RATE_9600 = 9600,
BAUD_RATE_19200 = 19200,
BAUD_RATE_38400 = 38400,
BAUD_RATE_115200 = 115200,
} enum_BAUD_RATE;
typedef enum {
en_UART0 = 0,
en_UART1,
en_UART2,
en_NUM_MAX
} enum_UART_NUM;
typedef enum {
en_MODE_FIFO,
en_MODE_NON_FIFO
} enum_UART_MODE;
typedef struct {
U8 txmode;
U8 rxmode;
U32 baudRate;
volatile UART_REGISTERS *registers;
} UART_DATA;
extern UART_DATA uartData[en_NUM_MAX];
//#define UART0_TX_DMA_BUF_SIZE (256+64)
#define UART0_TX_DMA_BUF_SIZE (1280)
#define UART0_RX_DMA_BUF_SIZE (256*4)
#ifdef UART0_TX_DMA_8bit
extern U8 uart0_tx_dma_buf [];
#else
extern U32 uart0_tx_dma_buf [];
#endif
int uart_init( int num );
int uart_open( int num );
int uart_close( int num );
int uart_setBaudRate( int num, U32 baudRate, U32 sysclk );
int uart_changeParity( int num, U32 parity);
int uart_changeBaudRate( int num, U32 baudRate, U32 sysclk );
//int uart_startTx( int num, FIFO *fifo );
int uart_stopTx( int num );
int uart_startRx( int num );
int uart_stopRx( int num );
void uart0_tx_send(char *buf, int size);
void uart1_tx_send(char *buf, int size);
void uart0_tx_send1(char *buf);
void uart1_tx_send1(char *buf);
void uart_0_rx_enble (void);
void uart_tx_gpio_send (U8 val);
void uart_test( U8 num );
#endif //_HW_UART_H