#include "os_config.h"

#include "c_def.h"
#include "debug.h"
#include "oem.h"

#include "regmap.h"

//#include "mem_reloc.h"

#include "hw_gpio.h"
#include "hw_uart.h"
#include "hw_misc.h"
//#include "hw_dma.h"

#include "app_gpio.h"
#include "interrupt.h"
#include "printf_fifo.h"
#include <string.h>

#include "flash_boot.h"
#include "hw_pll.h"


#ifdef UART_TX_FIFO_ENABLE
#define IMPROVE_EFFICIENCY_ENABLE
#endif


//#undef UART0_USED_FOR_APP_UI
//#define UART1_USED_FOR_APP_UI
//#define UART2_USED_FOR_APP_UI

//#define UART_BAUD_19200_FIX
//#define UART_TX_USED_GPIO
//#define UART_TX_1ST_BYTE_USED_GPIO

//#define UART_PORT_CHANGED_TO_GPIO


#if 0
//#define BUS_CLKS        (SYSTEM_CLKS/2)
#else
//#define BUS_CLKS        (SystemClock/2)
#endif


//UART_DATA uartData[en_UART0];
#ifdef UART0_TX_DMA_8bit
U8 uart0_tx_dma_buf [UART0_TX_DMA_BUF_SIZE];
#else
U32 uart0_tx_dma_buf [UART0_TX_DMA_BUF_SIZE];
#endif



#define	UART_NOP	{	\
	asm( "nop" );	\
	asm( "nop" );	\
	asm( "nop" );	\
}

int uart_init( int num )
{
	//UART_DATA *puart = uartData;

	if (num == en_UART0)
	{
		//set GPIO32 for Uart Tx.
		//gpio1_SetOutput(UART0_TX);
//		gpio0_ClrOutput(UART0_TX);
//		gpio0_SetOutputEnable(UART0_TX);
//		gpio0_SetFunction(UART0_TX, FALSE);
		app_gpio_MUXfunction_select(UART0_TX, MUX_SEL_FUNCTION1);

#ifdef UART0_RX_ENABLE

		//set GPIO33 for Uart Rx.
		//gpio0_ClrOutput(UART0_RX);
		//gpio0_SetOutputEnable(UART0_RX);
		//gpio0_SetFunction(UART0_RX, FALSE);
		app_gpio_MUXfunction_select(UART0_RX, MUX_SEL_FUNCTION1);
#endif
	}
	else if (num == en_UART1)
	{
		//set GPIO9 for Uart Tx.
		//gpio0_ClrOutput(UART1_TX);
		//gpio0_SetOutputEnable(UART1_TX);
		//gpio0_SetFunction(UART1_TX, FALSE);
		app_gpio_MUXfunction_select(UART1_TX, MUX_SEL_FUNCTION1);

#ifdef UART1_RX_ENABLE
		//set GPIO5 for Uart Rx.
		//gpio0_ClrOutput(UART1_RX);
		//gpio0_SetOutputEnable(UART1_RX);
		//gpio0_SetFunction(UART1_RX, FALSE);
		app_gpio_MUXfunction_select(UART1_RX, MUX_SEL_FUNCTION1);
#endif
	}
	else if (num == en_UART2)
	{
		//gpio0_SetFunction(UART2_TX, FALSE);
		app_gpio_MUXfunction_select(UART2_TX, MUX_SEL_FUNCTION1);
#ifdef UART2_RX_ENABLE
		//gpio0_SetFunction(UART2_RX, FALSE);
		app_gpio_MUXfunction_select(UART2_RX, MUX_SEL_FUNCTION1);
#endif
	}
	else
	{
		DBG_Assert(FALSE);
	}


#if 0
	puart->txmode	=	en_MODE_FIFO;
//	puart->txmode	=	en_MODE_NON_FIFO;
	puart->rxmode	=	en_MODE_NON_FIFO;
	puart->baudRate	=	DEFAULT_BAUD;
	puart->registers	=	(UART_REGISTERS *)UART0_BASE_ADDR;
	
	++puart;
	
	puart->txmode	=	en_MODE_FIFO;
	puart->rxmode	=	en_MODE_NON_FIFO;
	puart->baudRate	=	DEFAULT_BAUD;
	puart->registers	=	(UART_REGISTERS *)UART1_BASE_ADDR;
#endif

	return TRUE;
}

void uart_0_rx_enble (void)
{
	volatile UART_REGISTERS *pregs;

	pregs = (UART_REGISTERS *)UART0_BASE_ADDR;
	pregs->control	|=	CTL_RX_ENA;
}

int uart_open( int num )
{
	//UART_DATA *puart = &uartData[num];
	//volatile UART_REGISTERS *pregs = puart->registers;
	volatile UART_REGISTERS *pregs;
	int	ret;

	DBG_assert( num < en_NUM_MAX );
	
	if (num == en_UART0)
	{
#ifdef UART_PORT_CHANGED_TO_GPIO
		//gpio1_SetFunction(UART0_TX, FALSE);
		app_gpio_MUXfunction_select(UART0_TX, MUX_SEL_FUNCTION1);

#ifdef UART0_RX_ENABLE
		//gpio1_SetFunction(UART0_RX, FALSE);
		app_gpio_MUXfunction_select(UART0_RX, MUX_SEL_FUNCTION1);
#endif
#endif

		pregs = (UART_REGISTERS *)UART0_BASE_ADDR;
	}
	else if(num == en_UART1)
	{
#ifdef UART_PORT_CHANGED_TO_GPIO
		//gpio0_SetFunction(UART1_TX, FALSE);
		app_gpio_MUXfunction_select(UART1_TX, MUX_SEL_FUNCTION1);

#ifdef UART1_RX_ENABLE
		//gpio0_SetFunction(UART1_RX, FALSE);
		app_gpio_MUXfunction_select(UART1_RX, MUX_SEL_FUNCTION1);
#endif
#endif

		pregs = (UART_REGISTERS *)UART1_BASE_ADDR;
	}
	else
	{
		pregs = (UART_REGISTERS *)UART2_BASE_ADDR;
	}

	pregs->control	=	CTL_RESET;
	timer_delayus( 2 );
	pregs->control	=	0;
	timer_delayus( 2 );


#if 0
	//ret = uart_setBaudRate( num, puart->baudRate, BUS_CLKS );
	ret = uart_setBaudRate( num, DEFAULT_BAUD, BUS_CLKS );
	DBG_assert( ret );
#endif

	pregs->control	|=	CTL_RX_FIFO_RESET;
	UART_NOP;
	pregs->control	&=	~CTL_RX_FIFO_RESET;

	if (num == en_UART0)
	{
		//ret = uart_setBaudRate( num, puart->baudRate, BUS_CLKS );
		ret = uart_setBaudRate( num, DEFAULT_BAUD, BUS_CLKS );
		DBG_assert( ret );

#if 0//def BT_HCI_ENABLE
		//at biginning, just enable tx
		pregs->control	=	CTL_TX_ENA | 0 | CTL_PARITY_NON;
#else
#ifdef UART0_RX_ENABLE
		pregs->control	=	CTL_TX_ENA | CTL_RX_ENA | CTL_PARITY_NON;
#else
		pregs->control	=	CTL_TX_ENA | 0 | CTL_PARITY_NON;
#endif
#endif
	}
	else if(num == en_UART1)
	{
		//ret = uart_setBaudRate( num, puart->baudRate, BUS_CLKS );
		ret = uart_setBaudRate( num, UART1_DEFAULT_BAUD, BUS_CLKS );
		DBG_assert( ret );

#ifdef UART1_RX_ENABLE
		pregs->control	=	CTL_TX_ENA | CTL_RX_ENA | CTL_PARITY_NON;
#else
		pregs->control	=	CTL_TX_ENA | 0 | CTL_PARITY_NON;
#endif
	}
	else if(num == en_UART2)
	{
		//ret = uart_setBaudRate( num, puart->baudRate, BUS_CLKS );
		ret = uart_setBaudRate( num, UART2_DEFAULT_BAUD, BUS_CLKS );
		DBG_assert( ret );

#ifdef UART2_RX_ENABLE
		pregs->control	=	CTL_TX_ENA | CTL_RX_ENA | CTL_PARITY_NON;
#else
		pregs->control	=	CTL_TX_ENA | 0 | CTL_PARITY_NON;
#endif
	}

	if (num == en_UART0)
	{
		//uart_test(en_UART0);

		UART_INT_ENABLE( UART_INT_MASK );

#ifdef UART0_RX_ENABLE
#ifdef UART0_RX_DMA
		
#else
		uart_startRx( num );
#endif
#endif
	}
	else if (num == en_UART1)
	{
		//uart_test(en_UART1);

		UART_INT_ENABLE( UART1_INT_MASK );

#ifdef UART1_RX_ENABLE
		uart_startRx( num );
#endif
	}
	else
	{
		//uart_test(en_UART2);

#if (defined UART2_INT_ENABLE)
		UART_INT_ENABLE( UART2_INT_MASK );
#endif

#ifdef UART2_RX_ENABLE
		uart_startRx( num );
#endif
	}

	XT_INTS_ON(LEVEL1_INT1_MASK);

	return TRUE;
}

int uart_close( int num )
{
	//UART_DATA *puart = &uartData[num];
	//volatile UART_REGISTERS *pregs = puart->registers;
	volatile UART_REGISTERS *pregs;

	DBG_assert( num < en_NUM_MAX );

	if (num == en_UART0)
	{
		pregs = (UART_REGISTERS *)UART0_BASE_ADDR;
	}
	else if(num == en_UART1)
	{
		pregs = (UART_REGISTERS *)UART1_BASE_ADDR;
	}
	else
	{
		pregs = (UART_REGISTERS *)UART2_BASE_ADDR;
	}

	pregs->control	=	0;

	if (num == en_UART0)
	{
#ifdef UART_PORT_CHANGED_TO_GPIO
		delayms(2);
		//gpio1_SetFunction(UART0_TX, TRUE);
		app_gpio_MUXfunction_select(UART0_TX,MUX_SEL_GPIO_INPUT);
#ifdef UART0_RX_ENABLE
		//gpio1_SetFunction(UART0_RX, TRUE);
		app_gpio_MUXfunction_select(UART0_RX,MUX_SEL_GPIO_INPUT);
#endif
#endif
	}
	else if(num == en_UART1)
	{
#ifdef UART_PORT_CHANGED_TO_GPIO
		delayms(2);
		//gpio0_SetFunction(UART1_TX, TRUE);
		app_gpio_MUXfunction_select(UART1_TX,MUX_SEL_GPIO_INPUT);

#ifdef UART1_RX_ENABLE
		//gpio0_SetFunction(UART1_RX, TRUE);
		app_gpio_MUXfunction_select(UART1_RX,MUX_SEL_GPIO_INPUT);
#endif
#endif
	}

	return TRUE;
}

int uart_setBaudRate( int num, U32 baudRate, U32 sysclk )
{
	//volatile U32 tmp;
	//UART_DATA *puart = &uartData[num];
	//volatile UART_REGISTERS *pregs = puart->registers;
	volatile UART_REGISTERS *pregs;
	
	DBG_assert( num < en_NUM_MAX );

	if (num == en_UART0)
	{
		pregs = (UART_REGISTERS *)UART0_BASE_ADDR;
	}
	else if(num == en_UART1)
	{
		pregs = (UART_REGISTERS *)UART1_BASE_ADDR;
	}
	else
	{
		pregs = (UART_REGISTERS *)UART2_BASE_ADDR;
	}

#ifdef UART_BAUD_19200_FIX
	if (baudRate == BAUD_RATE_19200)
	{
#if 1
		//155
		pregs->divisor	=	sysclk/baudRate - 1;
#else
		//pregs->divisor = 155; 	//49us -> 52us
		pregs->divisor = 155 + 1;
		//pregs->divisor = 155 + 2;
		//pregs->divisor = 155 + 3; //50us -> 53us
		//pregs->divisor = 155 + 5; //50us -> 53us
		//pregs->divisor = 155 + 6; //51us -> 54us
		//pregs->divisor = 155 + 7; //51us -> 54us
#endif
	}
	else
	{
		pregs->divisor	=	sysclk/baudRate - 1;
	}
#else
	pregs->divisor	=	sysclk/baudRate - 1;
#endif

	return TRUE;
}

int uart_changeParity( int num, U32 parity)
{
	//UART_DATA *puart = &uartData[num];
	//volatile UART_REGISTERS *pregs = puart->registers;
	volatile UART_REGISTERS *pregs;
	
	DBG_assert( num < en_NUM_MAX );

	if (num == en_UART0)
	{
		pregs = (UART_REGISTERS *)UART0_BASE_ADDR;
	}
	else if(num == en_UART1)
	{
		pregs = (UART_REGISTERS *)UART1_BASE_ADDR;
	}
	else
	{
		pregs = (UART_REGISTERS *)UART2_BASE_ADDR;
	}

	pregs->control	&=	~(CTL_TX_ENA | CTL_RX_ENA);

	pregs->control	&=	~CTL_PARITY_MASK;
	pregs->control	|=	parity;

	pregs->control	|=	(CTL_TX_ENA | CTL_RX_ENA);

	return TRUE;
}

int uart_changeBaudRate( int num, U32 baudRate, U32 sysclk )
{
	//UART_DATA *puart = &uartData[num];
	//volatile UART_REGISTERS *pregs = puart->registers;
	volatile UART_REGISTERS *pregs;

	DBG_assert( num < en_NUM_MAX );

	if (num == en_UART0)
	{
		pregs = (UART_REGISTERS *)UART0_BASE_ADDR;
	}
	else if (num == en_UART1)
	{
		pregs = (UART_REGISTERS *)UART1_BASE_ADDR;
	}
	else
	{
		pregs = (UART_REGISTERS *)UART2_BASE_ADDR;
	}

	pregs->control	&=	~(CTL_TX_ENA | CTL_RX_ENA);
	
	pregs->divisor	=	sysclk/baudRate - 1;

	pregs->control	|=	(CTL_TX_ENA | CTL_RX_ENA);

	return TRUE;
}

int uart_startTx( int num, PRINTF_FIFO *fifo )
{
	//UART_DATA *puart = &uartData[num];
	//volatile UART_REGISTERS *pregs = puart->registers;
	volatile UART_REGISTERS *pregs;
	U32	tmp;
	int ret;

	DBG_assert( num < en_NUM_MAX );

	if (num == en_UART0)
	{
		pregs = (UART_REGISTERS *)UART0_BASE_ADDR;
	}
	else if(num == en_UART1)
	{
		pregs = (UART_REGISTERS *)UART1_BASE_ADDR;
	}
	else
	{
		pregs = (UART_REGISTERS *)UART2_BASE_ADDR;
	}

#ifdef UART_TX_FIFO_ENABLE
	//if( puart->txmode == en_MODE_FIFO )
	{
		if( !(pregs->intEnable & STAT_TX_BUF_HALF_EMPTY) )
		{
#if 1

#ifndef IMPROVE_EFFICIENCY_ENABLE
			while( !(pregs->status & STAT_TX_BUF_FULL) && fifo_getDataSize( fifo ) )
#else
			while( !(pregs->status & STAT_TX_BUF_FULL) && FiFo_GetDataSize( fifo ) )
#endif
			{
#ifndef IMPROVE_EFFICIENCY_ENABLE
				ret = fifo_get( fifo, (U8*)&tmp, 1 );
#else
				unsigned char *pTmp = (char *)&tmp;
                ret = FiFo_Get( fifo, pTmp, 1 );
#endif
				DBG_assert( ret == 1 );

				pregs->txBuf	=	tmp;
			}
#endif

			//pregs->intEnable	&=	~INT_TX_BUF_FULL;
			pregs->intEnable	|=	INT_TX_BUF_HALF_EMPTY;
		}
	}
	/*else
	{
		// nonfifo

		if( !(pregs->intEnable & INT_TX_BUF_EMPTY) )
		{
			ret = fifo_get( fifo, (U8*)&tmp, 1 );
			DBG_assert( ret == 1 );
			pregs->txBuf	=	tmp;

			pregs->intEnable	|=	INT_TX_BUF_EMPTY;
		}
	}*/
#else
	// nonfifo
	if( !(pregs->intEnable & INT_TX_BUF_EMPTY) )
	//if( !(pregs->intEnable & INT_TX_BUF_HALF_EMPTY) )
	{
#ifndef IMPROVE_EFFICIENCY_ENABLE
		ret = fifo_get( fifo, (U8*)&tmp, 1 );
#else
		U8 *pBuf = (U8*)&tmp;
		ret = FiFo_Get( fifo, pBuf, 1 );
#endif

		//DBG_Assert( ret == 1 );
		if (ret)
		{
			pregs->txBuf	=	tmp;
		}

		//don't need uart interrupt
		//pregs->intEnable	|=	INT_TX_BUF_FULL;
	}
#endif

	return TRUE;
}


int uart_stopTx( int num )
{
	//UART_DATA *puart = &uartData[num];
	//volatile UART_REGISTERS *pregs = puart->registers;
	volatile UART_REGISTERS *pregs;

	DBG_assert( num < en_NUM_MAX );

	if (num == en_UART0)
	{
		pregs = (UART_REGISTERS *)UART0_BASE_ADDR;
	}
	else if (num == en_UART1)
	{
		pregs = (UART_REGISTERS *)UART1_BASE_ADDR;
	}
	else
	{
		pregs = (UART_REGISTERS *)UART2_BASE_ADDR;
	}

	pregs->intEnable	&=	~(INT_TX_BUF_HALF_EMPTY | INT_TX_BUF_HALF_EMPTY | INT_TX_BUF_FULL);

	pregs->control	|=	CTL_TX_FIFO_RESET;
	UART_NOP;
	pregs->control	&=	~CTL_TX_FIFO_RESET;

	return TRUE;
}

int uart_startRx( int num )
{
	//UART_DATA *puart = &uartData[num];
	//volatile UART_REGISTERS *pregs = puart->registers;
	volatile UART_REGISTERS *pregs;

	DBG_assert( num < en_NUM_MAX );

	if (num == en_UART0)
	{
		pregs = (UART_REGISTERS *)UART0_BASE_ADDR;
	}
	else if(num == en_UART1)
	{
		pregs = (UART_REGISTERS *)UART1_BASE_ADDR;
	}
	else
	{
		pregs = (UART_REGISTERS *)UART2_BASE_ADDR;
	}

#ifdef UART_RX_FIFO_ENABLE
	//if( puart->rxmode == en_MODE_FIFO )
	{
		pregs->intEnable	|=	INT_RX_BUF_HALF_FULL;
	}
	/*else
	{
		pregs->intEnable	|=	INT_RX_BUF_NOT_EMPTY;
	}*/
#else
	pregs->intEnable	|=	INT_RX_BUF_NOT_EMPTY;
#endif

	return TRUE;
}

int uart_stopRx( int num )
{
	//UART_DATA *puart = &uartData[num];
	//volatile UART_REGISTERS *pregs = puart->registers;
	volatile UART_REGISTERS *pregs;

	if (num == en_UART0)
	{
		pregs = (UART_REGISTERS *)UART0_BASE_ADDR;
	}
	else if(num == en_UART1)
	{
		pregs = (UART_REGISTERS *)UART1_BASE_ADDR;
	}
	else
	{
		pregs = (UART_REGISTERS *)UART2_BASE_ADDR;
	}

	DBG_assert( num < en_NUM_MAX );

	pregs->intEnable	&=	~(INT_RX_BUF_NOT_EMPTY | INT_RX_BUF_HALF_FULL | INT_RX_BUF_FULL);

	pregs->control	|=	CTL_RX_FIFO_RESET;
	UART_NOP;
	pregs->control	&=	~CTL_RX_FIFO_RESET;

	return TRUE;
}

void uart0_isr( void )
{
	//uart_isr( en_UART0 );
}

void uart1_isr( void )
{
	//uart_isr( en_UART1 );
}

void uart_test( U8 num )
{
	char testString[] =	"UART0 tx test\n\r";
	//UART_DATA *puart = &uartData[0];
	//volatile UART_REGISTERS *pregs = puart->registers;
	//volatile UART_REGISTERS *pregs = (UART_REGISTERS *)UART0_BASE_ADDR;
	volatile UART_REGISTERS *pregs;

	if (num == en_UART0)
	{
		pregs	=	(UART_REGISTERS *)UART0_BASE_ADDR;
		testString[4] = '0';
	}
	else if (num == en_UART1)
	{
		pregs	=	(UART_REGISTERS *)UART1_BASE_ADDR;
		testString[4] = '1';
	}
	else
	{
		pregs	=	(UART_REGISTERS *)UART2_BASE_ADDR;
		testString[4] = '2';
	}

	int len = strlen( testString );
	int i = 0;

#if 1
	while( 1 )
	{
#if 1
		delayms((U32)1);
		//delayus(1);
		//while( !(pregs->status & STAT_TX_BUF_EMPTY) );
		while( ( pregs->status & STAT_TX_BUF_FULL) );
		delayms((U32)1);
		//delayus(1);
		{
			pregs->txBuf	=	(U32) testString[i ++];			
			if( i >= len ) i = 0;
			//if( i >= len ) break;
		}
#else
		uart0_tx_send(testString, len);
#endif
	}

#else
	while( 1 )
	{
		while( !(pregs->status & STAT_TX_BUF_EMPTY) ) ;
		pregs->txBuf	=	(U32) 'U';
		pregs->txBuf	=	(U32) 'A';
		pregs->txBuf	=	(U32) 'R';
		pregs->txBuf	=	(U32) 'T';
		pregs->txBuf	=	(U32) ' ';

		pregs->txBuf	=	(U32) 't';
		pregs->txBuf	=	(U32) 'x';
		pregs->txBuf	=	(U32) ' ';
		
		pregs->txBuf	=	(U32) 't';
		pregs->txBuf	=	(U32) 'e';
		pregs->txBuf	=	(U32) 's';
		pregs->txBuf	=	(U32) 't';
		pregs->txBuf	=	(U32) '\n';
		pregs->txBuf	=	(U32) '\r';
	}
#endif
}


#if 0

void uart0_tx_send(char *buf, int size)
{
#ifdef UART0_TX_DMA
	int i;
	U32 ret;
	U32 *pDmaDest;
	U32 eventMask;


	if (size > UART0_TX_DMA_BUF_SIZE) {
		//Because Tx buffer isnot big enough, use Rx buf for Tx buf.
		DBG_Assert (FALSE);
	}

	//waiting for uart0 tx ready
	tx_event_flags_get(&event_grop, UART0_TX_EVENT, TX_OR_CLEAR, &eventMask, TX_WAIT_FOREVER);


	for (i=0; i<size; i++) 
	{
		uart0_tx_dma_buf[i] = (U32) buf[i];	
	}

	//dma
	pDmaDest = (U32 *)(&REG_UART0_TX_DATA);
	DMA_Channel5_Init(pDmaDest, uart0_tx_dma_buf, size, SOURCE_DMA_UART_0_TX);

#else
	int i = 0;
	U32 ret;
	volatile UART_REGISTERS *pregs = (UART_REGISTERS *)UART0_BASE_ADDR;
	
#ifdef RTOS_ENABLE
	ret = tx_mutex_get( &mutex_uart0_tx, TX_WAIT_FOREVER );
#endif	
	for (i=0; i<size; i++)
	{
		//while( !(pregs->status & STAT_TX_BUF_EMPTY) );
		while( (pregs->status & STAT_TX_BUF_FULL) );

		pregs->txBuf = *buf++;
	}
	
#ifdef RTOS_ENABLE
	ret = tx_mutex_put( &mutex_uart0_tx );
#endif

#endif
}

void uart1_tx_send(char *buf, int size)
{
#if (defined UART1_USED_FOR_APP_UI && defined UART1_ENABLE)
	int i = 0;
	U32 ret;
	volatile UART_REGISTERS *pregs	=	(UART_REGISTERS *)UART1_BASE_ADDR;

	ret = tx_mutex_get( &mutex_uart1_tx, TX_WAIT_FOREVER );

	for (i=0; i<size; i++)
	{
		//while( !(pregs->status & STAT_TX_BUF_EMPTY) );
		while( (pregs->status & STAT_TX_BUF_FULL) );

		pregs->txBuf = *buf++;
	}

	ret = tx_mutex_put( &mutex_uart1_tx );
#endif //UART1_USED_FOR_APP_UI
}

void uart2_tx_send(char *buf, int size)
{
#if (defined UART2_USED_FOR_APP_UI && defined UART2_ENABLE)
	int i = 0;
	U32 ret;
	volatile UART_REGISTERS *pregs	=	(UART_REGISTERS *)UART2_BASE_ADDR;

	ret = tx_mutex_get( &mutex_uart2_tx, TX_WAIT_FOREVER );

	for (i=0; i<size; i++)
	{
		//while( !(pregs->status & STAT_TX_BUF_EMPTY) );
		while( (pregs->status & STAT_TX_BUF_FULL) );

		pregs->txBuf = *buf++;
	}

	ret = tx_mutex_put( &mutex_uart2_tx );
#endif //UART2_USED_FOR_APP_UI
}

void uart0_tx_send1(char *buf)
{
	int size;

	size = strlen(buf);
	uart0_tx_send(buf, size);
}

void uart1_tx_send1(char *buf)
{
#if defined(BOOT_FROM_FLASH) && defined(UART1_ENABLE)
	int size;

	size = strlen(buf);
	uart1_tx_send(buf, size);
#endif
}
#endif
#if 0

#define UART_TX_PIN_LOW			GPIO1_OUTPUT_CLR(UART0_TX)

#define UART_TX_PIN_HIGH		GPIO1_OUTPUT_SET(UART0_TX)

//52.40us
//#define LOOP_52US_CNT1		5000
//52.00us
//#define LOOP_52US_CNT1		4960
//52.08us
#define LOOP_52US_CNT1			4970

//51.60us
//#define LOOP_52US_CNT2		4900
//52.00us
//#define LOOP_52US_CNT2		4950
//52.08us
#define LOOP_52US_CNT2			4960


//#define ASM_NOP_DELAY		asm("nop"); \
//							asm("nop");


//void uart_tx_gpio_send(U8 val) __INTERNAL_RAM_TEXT;


//use tx pin as gpio function
void uart_tx_gpio_send (U8 val)
{
#if defined UART_TX_1ST_BYTE_USED_GPIO
	U8 i;
	//U8 bit_mask = 0x80;
	U8 bit_mask = 0x01;
	TX_INTERRUPT_SAVE_AREA;

	TX_DISABLE;

	// start bit
	UART_TX_PIN_LOW;
	delay_loop(LOOP_52US_CNT1);

	if (val & 01)
	{
		UART_TX_PIN_HIGH;
	}
	else
	{
		UART_TX_PIN_LOW;
	}
	delay_loop(LOOP_52US_CNT2);

	if (val & 0x02)
	{
		UART_TX_PIN_HIGH;
	}
	else
	{
		UART_TX_PIN_LOW;
	}
	delay_loop(LOOP_52US_CNT2);

	if (val & 0x04)
	{
		UART_TX_PIN_HIGH;
	}
	else
	{
		UART_TX_PIN_LOW;
	}
	delay_loop(LOOP_52US_CNT2);

	if (val & 0x08)
	{
		UART_TX_PIN_HIGH;
	}
	else
	{
		UART_TX_PIN_LOW;
	}
	delay_loop(LOOP_52US_CNT2);

	if (val & 0x10)
	{
		UART_TX_PIN_HIGH;
	}
	else
	{
		UART_TX_PIN_LOW;
	}
	delay_loop(LOOP_52US_CNT2);

	if (val & 0x20)
	{
		UART_TX_PIN_HIGH;
	}
	else
	{
		UART_TX_PIN_LOW;
	}
	delay_loop(LOOP_52US_CNT2);

	if (val & 0x40)
	{
		UART_TX_PIN_HIGH;
	}
	else
	{
		UART_TX_PIN_LOW;
	}
	delay_loop(LOOP_52US_CNT2);

	if (val & 0x80)
	{
		UART_TX_PIN_HIGH;
	}
	else
	{
		UART_TX_PIN_LOW;
	}
	delay_loop(LOOP_52US_CNT1);

	//sop bit
	UART_TX_PIN_HIGH;
	delay_loop(LOOP_52US_CNT1);

	TX_RESTORE;

#elif defined UART_TX_USED_GPIO

TX_DISABLE;
	// start bit
	UART_TX_PIN_LOW;
	delay_loop(LOOP_52US_CNT1);

	for (i=0; i<8; i++)
	{
		if (val & bit_mask)
		{
			UART_TX_PIN_HIGH;
		}
		else
		{
			UART_TX_PIN_LOW;
		}

		bit_mask <<= 1;
		delay_loop(LOOP_52US_CNT2);
	}

	//sop bit
	UART_TX_PIN_HIGH;
	delay_loop(LOOP_52US_CNT1);

	TX_RESTORE;

#else
//	#error "defined Uart1 Used Gpio"
#endif
}

#endif //1