#include "os_config.h"

#include "c_def.h"
#include "debug.h"
#include "oem.h"

#include "regmap.h"

#include "hw_misc.h"
#include "hw_uart.h"
#include "app_gpio_OEM.h"
#include "os_type.h"
#include "hw_pll.h"
#include "interrupt.h"

//void misClockFreq_Set(I16 type) __INTERNAL_RAM_TEXT;
//void misClockFreq_Set_Bybass(void) __INTERNAL_RAM_TEXT;
//void misClockFreq_Set_RtcClk(void ) __INTERNAL_RAM_TEXT;
//void misClockFreq_Set_Crystal_Div (I16 div) __INTERNAL_RAM_TEXT;

U32 SystemClock = SYSTEM_CLKS;

volatile I8 pre_freq = -1;


#if 1

void delaynop( int loop )
{
	while( loop -- )
	{
		asm("nop");
	}
}

void reg_misc_pll_config( U8 regPLL_m, U8 regPLL_n, U8 regPLL_od, U8 regPLL_div, U8  pd)
{
	//REG_MISC_PLL = (regPLL_div << 15) | (regPLL_od << 13) | (regPLL_n << 9) | (regPLL_m << 1) | (pd);
	//delayus(10);
}

void misc_clkgate_init( void )
{
	U32 i;
	volatile U32 val;
	U8 flag;
	volatile U32 tmp,tmp1,tmp2,tmp3,temp;
	U32 *otgEnhCtrl_ctrl;
    U32 reg32;
	MISC_CLKGATE_CONTROLs *clkgate_config;
	clkgate_config = (MISC_CLKGATE_CONTROLs *)&tmp;
	
#ifndef LOW_POWER_MODE
	tmp = 0xFFFFFFFF;
	REG_MISC_CLKGATE = tmp;
#else	
	tmp = 0;
	clkgate_config = (MISC_CLKGATE_CONTROLs *) &tmp;
	
	clkgate_config->AHB_BTDM_IF_gate = 1;
	clkgate_config->u_uart0_gate = 1;
	clkgate_config->AHB_Audio_Controller_gate = 1;
	clkgate_config->AHB_BTDM_IF_pclk_gate = 1;
	//clkgate_config->u_uart2_gate = 1;
	clkgate_config->usbOtgSd_gate = 1;
	clkgate_config->codec_apb_gate = 1;
	REG_MISC_CLKGATE = tmp;	

#if 1
	//otgEnhCtrl
	otgEnhCtrl_ctrl	=	(U32*)OTG_CTL_REG_ADDR;

	//int otg_open( void )				//Enable OTG.
	reg32 = ENH_CTRL_PHY_CLK_ENA|ENH_CTRL_PHY_REG_ENA|ENH_CTRL_PHY_PLL_ENA|ENH_CTRL_DIS_HSPEED | ENH_CTRL_PHY_NO_SUSPEND;
	*otgEnhCtrl_ctrl	=	reg32;
	timer_delayms(20);
	reg32 &= ~(ENH_CTRL_PHY_PLL_ENA|ENH_CTRL_PHY_NO_SUSPEND);
	*otgEnhCtrl_ctrl	=	reg32;

	timer_delayms(1);

	clkgate_config->usbOtgSd_gate = 0;

	REG_MISC_CLKGATE = tmp;	
#endif
#endif


#if 0
	//otgEnhCtrl
	otgEnhCtrl_ctrl	=	(U32*)OTG_CTL_REG_ADDR;
	reg32 = ENH_CTRL_PHY_CLK_ENA|ENH_CTRL_PHY_REG_ENA|ENH_CTRL_PHY_PLL_ENA|ENH_CTRL_DIS_HSPEED | ENH_CTRL_PHY_NO_SUSPEND;
	*otgEnhCtrl_ctrl	=	reg32;
	timer_delayms(20);
	reg32 &= ~(ENH_CTRL_PHY_PLL_ENA|ENH_CTRL_PHY_NO_SUSPEND);
	*otgEnhCtrl_ctrl	=	reg32;

	timer_delayms(1);

	clkgate_config->usbOtgSd_gate = 0;
	REG_MISC_CLKGATE = tmp;	
#endif

	MISC_RTC_CONTROLs *rtc_config;
	tmp = REG_MISC_RTC;
	rtc_config = (MISC_RTC_CONTROLs *) &tmp;	
	rtc_config->rtc_en = 0;
	//rtc_config->btdm_en = 0;

#if 1
	rtc_config->cpu_mem_emaw = 0; //memory fast
	rtc_config->cpu_mem_ema = 0; //memory fast
#endif

	REG_MISC_RTC = tmp;

}

void pll_set( void )
{
}


void misClockFreq_init (void)
{
}


void misClockFreq_Set (I16 type)
{
}


#ifdef SYS_CLK_VOLATILE
void misClockFreq_Set_Bybass (void)
{
	U32 temp;

	pre_freq = FREQ_24MHZ;

	//switch to crystal	
	//REG_MISC_CFG	=	( 7 << 13 ) | ( 7 << 7 ) | 0x6a;
	temp = (REG_MISC_CFG & 0xFF00);
	temp |= 0x6a;
	REG_MISC_CFG = temp;

	//delay_loop(10);

	SystemClock =  CLK_BASE_FREQ  * 2;

	_xt_tick_divisor_init();

#ifdef PWM_OUT_ENABLE
	hw_pwm_clk_set(PWM_CLK_DIV4);
#endif

#ifdef UART0_ENABLE
	//uart_setBaudRate(en_UART0, DEFAULT_BAUD, SystemClock/2);
#endif

#ifdef UART1_ENABLE
	uart_setBaudRate(en_UART1, DEFAULT_BAUD, SystemClock/2);
#endif

#ifdef UART2_ENABLE
	uart_setBaudRate(en_UART2, DEFAULT_BAUD, SystemClock/2);
#endif

#ifdef REMOTE_ENABLE
#if (defined SYS_CLK_VOLATILE && (!(defined REMOTE_IR_ENABLE)))
	Remote_Timer_Init();
#endif
#endif

#ifdef BLUETOOTH_MODULE
#if (defined BT_SIMPLE_CONTROL && defined BT_STATUS_POLLING_USED_GPIO)
#ifdef SYS_CLK_VOLATILE
	bt_timer_init();
#endif
#endif
#endif

	//Spi_Clk_Freq_Set(SPI_CLK_DEFAULT/2);
}

void misClockFreq_Set_RtcClk (void)
{
#if 0
	U32 temp;

	pre_freq = FREQ_32kHZ;

	//switch to rtc 32k
	//REG_MISC_CFG	=	( 7 << 13 ) | ( 7 << 7 ) | 0x55;
	temp = (REG_MISC_CFG & 0xFF00);
	temp |= 0x55;
	REG_MISC_CFG = temp;

	delay_loop(10);

	//32 kHz
	//SystemClock =  32  * 1000;

	//_xt_tick_divisor_init();
#endif
}

/*divider clock from 24MHz*/
void misClockFreq_Set_Crystal_Div (I16 div)
{
#if 0

#if 1
	U32 temp;
	TX_INTERRUPT_SAVE_AREA;

	TX_DISABLE;

	div &= 0x3F;				//only 6 bits

	//pre_freq = FREQ_24MHZ;

	temp = REG_MISC_CFG;
	temp &= ~(0x3F << 7);			//reg[12:7] cryetal div
	//temp |= (0x01 << 7);			//24M/2=12M clk

	switch (div)
	{
		case FREQ_DIV_12MHZ:
			SystemClock =  CLK_BASE_FREQ;			//12M
			temp |= (0x0 << 7);				//24M/2=12M clk
			break;

		case FREQ_DIV_6MHZ:
			SystemClock =  CLK_BASE_FREQ/2;			//6M
			temp |= (0x01 << 7);			//24M/4=6M clk
			break;

		case FREQ_DIV_4MHZ:
			SystemClock =  CLK_BASE_FREQ/3;			//4M
			temp |= (0x02 << 7);			//24M/6=4M clk
			break;

		case FREQ_DIV_2MHZ:
			SystemClock =  CLK_BASE_FREQ/6;			//2M
			temp |= (0x03 << 7);			//24M/12=2M clk
			break;

		case FREQ_DIV_1MHZ:
			SystemClock =  CLK_BASE_FREQ/12;		//1M
			temp |= (0x04 << 7);			//24M/6=4M clk
			break;

		default:
			SystemClock =  CLK_BASE_FREQ;			//12M
			temp |= (0x0 << 7);				//24M/2=12M clk
			break;
	}

#ifdef UART0_ENABLE
	//uart_setBaudRate(en_UART0, DEFAULT_BAUD, SystemClock/2);
#endif

#ifdef UART1_ENABLE
	uart_setBaudRate(en_UART1, DEFAULT_BAUD, SystemClock/2);
#endif

#ifdef UART2_ENABLE
	uart_setBaudRate(en_UART2, DEFAULT_BAUD, SystemClock/2);
#endif

#if (defined SYS_CLK_VOLATILE && (!(defined REMOTE_IR_ENABLE)))
	Remote_Timer_Init();
#endif


	//temp |= (0x02 << 7);			//24M/6=4M clk
	//temp |= (0x01 << 7);			//24M/4=6M clk
	//temp |= (0x0 << 7);			//24M/2=12M clk

	//temp &= ~(0x03 << 4);			//32k, crystal div sel
	//temp |= (0x01 << 4);			//sel crystal div

#if 0
	temp &= (~0x7F);
	temp |= 0x65;
#endif

	//select crystal div
	temp &= (~0x7C);
	temp |= 0x64;
	REG_MISC_CFG = temp;

	delayms (10);

	//switch
	temp &= (~0x03);
	temp |= 0x65;
	REG_MISC_CFG = temp;
#endif


#if 0
	//switch to crystal	
//	REG_MISC_CFG	=	( 7 << 13 ) | ( 7 << 7 ) | 0x6a;
	temp = (REG_MISC_CFG & 0xFF00);
	temp |= 0x6a;
	REG_MISC_CFG = temp;

	//delay_loop(10);
#endif


	_xt_tick_divisor_init();

#ifdef UART0_ENABLE
	//uart_setBaudRate(en_UART0, DEFAULT_BAUD, SystemClock/2);
#endif

#ifdef UART1_ENABLE
	//uart_setBaudRate(en_UART1, DEFAULT_BAUD, SystemClock/2);
#endif

#ifdef UART2_ENABLE
	//uart_setBaudRate(en_UART2, DEFAULT_BAUD, SystemClock/2);
#endif

#ifdef REMOTE_ENABLE
#if (defined SYS_CLK_VOLATILE && (!(defined REMOTE_IR_ENABLE)))
	//Remote_Timer_Init();
#endif
#endif

#ifdef PWM_OUT_ENABLE
	//Spi_Clk_Freq_Set(SPI_CLK_DEFAULT/8);
#endif

	TX_RESTORE;
#endif
}

#endif //SYS_CLK_VOLATILE
	

void miscPll_power_down(void)
{
	//REG_MISC_PLL |= PLL_POWER_MASK;
}

void miscPll_power_up(void)
{
	//REG_MISC_PLL &= ~PLL_POWER_MASK;
}

void miscCrystal_disable(void)
{
	//REG_MISC_CFG &= ~CRYSTAL_CLK_MASK;
}

void miscCrystal_enable(void)
{
	//REG_MISC_CFG |= CRYSTAL_CLK_MASK;
}

void miscAdc_clk_disable(void)
{
	//REG_MISC_ADC_CTL &= ~ADC_CLK_MASK;
}

void miscAdc_clk_enable(void)
{
	//REG_MISC_ADC_CTL |= ADC_CLK_MASK;
}

void misSdram_clk_disable(void)
{
	//REG_MISC_SDRAM_CFG1 &= ~SDRAM_CLK_MASK;
}

void misSdram_clk_enable(void)
{
	//REG_MISC_SDRAM_CFG1 |= SDRAM_CLK_MASK;
}

void misDebug_function_enable(U8 con)
{
#if 0	
	if (con)
	{
		REG_MISC_SDRAM_CFG2	&= ~REG_MISC_SDRAM_CFG2_BIT_DBG;
	}
	else
	{
		REG_MISC_SDRAM_CFG2	|= REG_MISC_SDRAM_CFG2_BIT_DBG;
	}
#endif
}

void misSdram_func_clr(void)
{
#if 0
	U32 tmp;

	REG_MISC_SDRAM_CFG1 = 0;
	delay_loop(10);

	REG_MISC_SDRAM_CFG2 = 0x11080;
#endif
}

U32 miscClock_gate_get(void)
{
	U32 temp;

	temp = REG_MISC_CLKGATE;
	return temp;	
}

void miscClock_gate_set(U32 clk_gate)
{
	REG_MISC_CLKGATE |= clk_gate;
}

void miscClock_gate_clr(U32 clk_gate)
{
	REG_MISC_CLKGATE &= ~clk_gate;
}

#ifdef POWER_KEY_ENABLE
void app_power_key_init(void)
{
	app_gpio_MUXfunction_select(POWER_KEY_PIN,MUX_SEL_GPIO_INPUT);
	app_gpio_interrupt_set(POWER_KEY_PIN,1,TRIGGER_EDGE,GPIO_INT_RISING_EDGE);

	XT_INTS_ON(LEVEL1_INT0_MASK);
}

void app_rtc_write_reg(U32 reg_addr, U32 *data)
{

	volatile U32 tmp;
	MISC_RTC_CONTROLs *rtc_config;

	tmp = REG_MISC_RTC;
	rtc_config = (MISC_RTC_CONTROLs *) &tmp;
	
	rtc_config->rtc_addr = reg_addr;
	rtc_config->rtc_spi_rwn = 0;
	
	REG_MISC_RTCWD = *data;
	REG_MISC_RTC = tmp;
	
	rtc_config->rtc_spi_go = 1;
	REG_MISC_RTC = tmp;	

	while(1) {
		tmp = REG_MISC_RTC;
		rtc_config = (MISC_RTC_CONTROLs *) &tmp;
	
		if (rtc_config->rtc_rw_fini) {			

			rtc_config->rtc_spi_go = 0;			
			rtc_config->rtc_addr = 0;
			REG_MISC_RTC = tmp;
			break;
		}
	}
}

void app_rtc_read_reg(U32 reg_addr, U32 *data)
{
	volatile U32 tmp;
	MISC_RTC_CONTROLs *rtc_config;

	tmp = REG_MISC_RTC;
	rtc_config = (MISC_RTC_CONTROLs *) &tmp;
	

	rtc_config->rtc_addr = reg_addr;
	rtc_config->rtc_spi_rwn = 1;
	REG_MISC_RTC = tmp;
	
	rtc_config->rtc_spi_go = 1;
	REG_MISC_RTC = tmp;	

	while(1) {
		tmp = REG_MISC_RTC;
		rtc_config = (MISC_RTC_CONTROLs *) &tmp;	
	
		if (rtc_config->rtc_rw_fini) {

			*data = REG_MISC_RTCRD;
			
			rtc_config->rtc_spi_go = 0;			
			rtc_config->rtc_addr = 0;
			REG_MISC_RTC = tmp;
			break;
		}
	}
}

void hw_rtc_init(void)
{
	volatile U32 val;
	volatile U32 tmp,tmp1;
	volatile U32 reg_val;
	RTC_CTRL_ST *reg_val_cfg;
	RTC_CTRL2_ST *reg2_val_cfg;
	RTC_TIMER_ST *timer_cfg;
	RTC_DAY_SEC_ST *alam_cfg;
	RTC_SEC_32K_ST *alam2_cfg;

	//read
	app_rtc_read_reg(RTC_CTRL_ADDR, &val);
	
	//write
	reg_val_cfg = (RTC_CTRL_ST *) &val;
	reg_val_cfg->minPoweronWidth = 0xA;
	reg_val_cfg->rtc_Sel = 0;			//RC 32K
	reg_val_cfg->rtc_pd = 0;
	reg_val_cfg->alarm0En =0;
	reg_val_cfg->alarm1En =0;
	reg_val_cfg->alarm2En =0;
	reg_val_cfg->rtc_crystal_en =0;
	//reg_val_cfg->reg_power =1;
	reg_val_cfg->reg_power =1;			//power oN
	reg_val_cfg->reg_power_key_en =1;
	reg_val_cfg->reg_ir_en =1;
	reg_val_cfg->reg_hdmicec_en =1;

	app_rtc_write_reg(RTC_CTRL_ADDR, &val);
	
	//write
	reg2_val_cfg = (RTC_CTRL2_ST *) &val;
	reg2_val_cfg->trim = 4;
	reg2_val_cfg->lp_clk_en = 0;					
	app_rtc_write_reg(RTC_CTRL2_ADDR, &val);


	MISC_CFG_CONTROLs *CFG_config;
	tmp = REG_MISC_CFG;
	CFG_config = (MISC_CFG_CONTROLs *) &tmp;
	CFG_config->lp_clk_from_24M_en = 1;
	REG_MISC_CFG = tmp;	
	delayus(5);
	
	//write timer
	reg_val = 0;
	timer_cfg = (RTC_TIMER_ST *) &reg_val;
	timer_cfg->sec = 3;
	timer_cfg->days = 4;

	app_rtc_write_reg(RTC_TIMER_WT_ADDR, &reg_val);


	//write alarm0
	reg_val = 0;
	alam_cfg = (RTC_DAY_SEC_ST *) &reg_val;
	alam_cfg->sec = 4;
	alam_cfg->days = 0;

	app_rtc_write_reg(RTC_ALARM0_ADDR, &reg_val);

	//read timer
	app_rtc_read_reg(RTC_TIMER_RD_ADDR, &tmp1);
	app_rtc_read_reg(RTC_TIMER32k_RD_ADDR, &tmp1);


	//write alarm1
	reg_val = 0;
	alam_cfg = (RTC_DAY_SEC_ST *) &reg_val;
	alam_cfg->sec = 5;
	alam_cfg->days = 0;
	app_rtc_write_reg(RTC_ALARM1_ADDR, &reg_val);


	//write alarm2
	reg_val = 0;
	alam2_cfg = (RTC_SEC_32K_ST *) &reg_val;
	alam2_cfg->sec = 7;
	alam2_cfg->count_32K = 6;

	app_rtc_write_reg(RTC_ALARM2_ADDR, &reg_val);

	reg_val = 0xFa5a5a5a;
	app_rtc_write_reg(RTC_EEROM_2_ADDR, &reg_val);

	app_rtc_read_reg(RTC_EEROM_2_ADDR, &tmp1);

	if (tmp1 != 0xFa5a5a5a)
	{
		while(1);
	}

	//read alarm0 1 2

	app_rtc_read_reg(RTC_ALARM0_ADDR, &tmp1);

	alam_cfg = (RTC_DAY_SEC_ST *) &tmp1;
	//if (alam_cfg->sec == 4 && alam_cfg->days == 0) 
	if (alam_cfg->sec == 4) 
	{

	}
	else{
		while(1);
	}

	app_rtc_read_reg(RTC_ALARM1_ADDR, &tmp1);

	alam_cfg = (RTC_DAY_SEC_ST *) &tmp1;
	//if (alam_cfg->sec == 5 && alam_cfg->days == 0) 
	if (alam_cfg->sec == 5) 
	{

	}
	else{
		while(1);
	}

	app_rtc_read_reg(RTC_ALARM2_ADDR, &tmp1);

	alam2_cfg = (RTC_SEC_32K_ST *) &tmp1;
	if (alam2_cfg->sec == 7 && alam2_cfg->count_32K == 6) {

	}
	else{
		while(1);
	}

	//open alarm int 0 1 2
	reg_val_cfg = (RTC_CTRL_ST *) &val;	
	reg_val_cfg->alarm0En = 1;
	app_rtc_write_reg(RTC_CTRL_ADDR, &val);

	reg_val_cfg->alarm1En = 1;
	app_rtc_write_reg(RTC_CTRL_ADDR, &val);

	reg_val_cfg->alarm2En = 1;
	app_rtc_write_reg(RTC_CTRL_ADDR, &val);
	

	while (1)
	{
		app_rtc_read_reg(RTC_CTRL_ADDR, &val);
		reg_val_cfg = (RTC_CTRL_ST *) &val;	
		if (reg_val_cfg->alarm0Int)
		{
			reg_val_cfg->alarm0Int = 1;
			reg_val_cfg->alarm1Int = 0;
			reg_val_cfg->alarm2Int = 0;
			app_rtc_write_reg(RTC_CTRL_ADDR, &val);		
			break;
		}
	}

	while (1)
	{
		app_rtc_read_reg(RTC_CTRL_ADDR, &val);
		reg_val_cfg = (RTC_CTRL_ST *) &val;	
		if (reg_val_cfg->alarm1Int)
		{
			reg_val_cfg->alarm0Int = 0;
			reg_val_cfg->alarm1Int = 1;
			reg_val_cfg->alarm2Int = 0;
			app_rtc_write_reg(RTC_CTRL_ADDR, &val);		
			break;
		}
	}

}

void hw_power_off(void)
{
	volatile U32 val;
	RTC_CTRL_ST *reg_val_cfg;
	//read
	app_rtc_read_reg(RTC_CTRL_ADDR, &val);

	//write
	reg_val_cfg = (RTC_CTRL_ST *) &val;	
	reg_val_cfg->reg_power = 0;

	reg_val_cfg->alarm0En = 0;
	reg_val_cfg->alarm1En = 0;
	reg_val_cfg->alarm2En = 0;

	reg_val_cfg->alarm0Int = 0;
	reg_val_cfg->alarm1Int = 0;
	reg_val_cfg->alarm2Int = 0;
	
	app_rtc_write_reg(RTC_CTRL_ADDR, &val);

}
#endif

#endif