optek_d2as_table.h
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#ifndef __OPTEK_D2AS_TABLE_H__
#define __OPTEK_D2AS_TABLE_H__
//#define P160_M8_COEFFS_USED
//#define P160_M12_COEFFS_USED
//#define P160_M24_COEFFS_USED
//#define P160_M48_COEFFS_USED
//#define P192_M8_COEFFS_USED
//#define P192_M12_COEFFS_USED
//#define P192_M24_COEFFS_USED
//#define P192_M48_COEFFS_USED
//#define P1920_M48_COEFFS_USED
//#define P1920_M32_COEFFS_USED
// the macro below is used for SRC from x --> 48kHz
#define SPDIF_INPUT_SAMPLERATE_32K
//#define SPDIF_INPUT_SAMPLERATE_44P1K
//#define SPDIF_INPUT_SAMPLERATE_64K
//#define SPDIF_INPUT_SAMPLERATE_88P2K
#if 0
#define SPDIF_D2AS_N (192) //512/4+512/4/2
#else
//#define SPDIF_D2AS_N (216) //576/4+576/4/2
//#define SPDIF_D2AS_N (300) //
//#define SPDIF_D2AS_N (288) //
#define SPDIF_D2AS_N (288+12) //
//#define SPDIF_D2AS_N (432) //576/4+576/4/2
#endif
#define SPDIF_D2AS_M_32 32
//#define SPDIF_D2AS_M_24 24
#define SPDIF_D2AS_M_12 12
//efine SPDIF_D2AS_M_8 8
#if 0
#define SPDIF_44100_BASE_STEP (147)
#define SPDIF_44100_BASE_INTER_D (160)
#else
#define SPDIF_44P1K_TO_48K_BASE_STEP (147)
#define SPDIF_44P1K_TO_48K_BASE_INTER_D (160)
#endif
#if 0
#define SPDIF_88200_BASE_STEP (147)
#define SPDIF_88200_BASE_INTER_D (160/2)
#else
#define SPDIF_44P1K_TO_88P2K_BASE_STEP 147
#define SPDIF_44P1K_TO_88P2K_BASE_INTER_D (160/2)
#endif
#if 1
#define SPDIF_32000_BASE_STEP 128
#define SPDIF_32000_BASE_INTER_D 192
#else
#define SPDIF_32000_BASE_STEP 576//128
#define SPDIF_32000_BASE_INTER_D 864//192
#endif
#define SPDIF_64000_BASE_STEP 128
#define SPDIF_64000_BASE_INTER_D (192/2)
#define SPDIF_48000_BASE_STEP 192
#define SPDIF_48000_BASE_INTER_D 192
#define SPDIF_D2AS_HP_MASK 3
#define SPDIF_D2AS_MASK 15
#define SPDIF_D2AS_CHAN 2
#define SPDIF_D2AS_BUF_SZ ((288+128)*4+64) /*max 32000->192 * 3/2 -> 288 + remain*/
//#define SPDIF_D2AS_BUF_SZ ((288+512)*4+64) /*max 32000->192 * 3/2 -> 288 + remain*/
//#define SPDIF_D2AS_BUF_SZ ((288+576)*4+64) /*max 32000->192 * 3/2 -> 288 + remain*/
//#define SPDIF_D2AS_BUF_SZ ((288+1152)*4+64) /*max 32000->192 * 3/2 -> 288 + remain*/
#define SBC_BLOCK_SAMPLES 128
// the macro below is used for SRC from x --> 44.1kHz
#define SPDIF_48K_T0_44P1K_BASE_STEP 160
#define SPDIF_48K_T0_44P1K_BASE_INTER_D 147
#define SPDIF_48K_T0_88P2K_BASE_STEP 147
#define SPDIF_48K_T0_88P2K_BASE_INTER_D (160/2)
extern const int P160_M8_coeffs[159][8];
extern const int P160_M12_coeffs[159][12];
extern const int P160_M12_coeffs[159][12];
extern const int P160_M24_coeffs[159][24];
extern const int P160_M48_coeffs[159][48];
extern const int P192_M8_coeffs[191][8];
extern const int P192_M12_coeffs[191][12];
extern const int P192_M12_coeffs[191][12];
extern const int P192_M24_coeffs[191][24];
extern const int P192_M48_coeffs[191][48];
extern const int P1920_M32_coeffs[1920-1][32];
extern int *pP1920_M32_coeffs;
extern const int spdif_lpf_88200_to_44100[];
extern const int spdif_lpf_96000_to_48000[];
extern const int spdif_lpf_176400_to_44100[];
extern const int spdif_lpf_192000_to_48000[];
extern const int spdif_lpf_bypass[];
#endif //__OPTEK_D2AS_TABLE_H__