os_config.h
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/*
* Copyright (C) Optek
* All Rights Reserved
*
* Model specific rtos configuration file.
*/
#ifndef _OS_CONFIG_H
#define _OS_CONFIG_H
#include "os_type.h"
//#define UART_TX_EVENT_FIFO_EMPTY_ENABLE
//#define TX_INT_DISABLE XCHAL_EXCM_LEVEL /* Disable interrupts value */
//#define TX_INT_ENABLE 0x0 /* Enable interrupt value */
#include "tx_port.h"
#include "FreeRTOS.h"
#include "task.h"
#include "semphr.h"
#include "timers.h"
//RTOS
//#define TIMER0_1MS
#define TIMER0_5MS
//#define TIMER0_10MS
//#define TIMER0_20MS
//#define TIMER0_25MS
#if defined TIMER0_1MS
#define TIMER0_MIN_TIME 1 //ms
#elif defined TIMER0_5MS
#define TIMER0_MIN_TIME 5 //ms
#endif
#if 0
#undef XT_TIMER_INDEX
#undef XT_TIMER_INTPRI
#define XT_TIMER_INDEX 0
#define XT_TIMER_INTPRI 1
//#define XT_TIMER_INTPRI 2
//#define XT_TIMER_INTPRI 3
//#define XT_TIMER_INTPRI 4
//#define XT_TIMER_INTPRI 5
//#define XT_TIMER_INTPRI 6
#endif
/*
#define OS_TIMER_INT_1000HZ 1000
#define OS_TIMER_INT_200HZ 200
#define OS_TIMER_INT_100HZ 100
*/
#if defined(TIMER0_1MS)
#define TIMER0_INT_FREQ 1000
#define TIMER0_MSEC_PER_TICK 1
#elif defined(TIMER0_5MS)
#define TIMER0_INT_FREQ 200
#define TIMER0_MSEC_PER_TICK 5
#elif defined(TIMER0_10MS)
#define TIMER0_INT_FREQ 100
#define TIMER0_MSEC_PER_TICK 10
#elif defined(TIMER0_20MS)
#define TIMER0_INT_FREQ 50
#define TIMER0_MSEC_PER_TICK 20
#elif defined(TIMER0_25MS)
#define TIMER0_INT_FREQ 40
#define TIMER0_MSEC_PER_TICK 25
#else
#error "Timer INT Freq must be defined for RTOS."
#endif
#define OS_MSEC_PER_TICK TIMER0_MSEC_PER_TICK
#define OS_TIMER_INT_FREQ TIMER0_INT_FREQ
//#define TIMER1_50US_INT
//#define TIMER1_100US_INT
#define TIMER1_1MS_INT
//#define TIMER1_5MS_INT
//#define TIMER1_10MS_INT
//for Timer1
#if defined TIMER1_50US_INT
#define TIMER1_INT_FREQ 20000
#elif defined TIMER1_100US_INT
#define TIMER1_INT_FREQ 10000
#elif defined TIMER1_1MS_INT
#define TIMER1_INT_FREQ 1000
#elif defined TIMER1_5MS_INT
#define TIMER1_INT_FREQ 200
#elif defined TIMER1_10MS_INT
#define TIMER1_INT_FREQ 100
#endif
//Events: <= 32
#define AUDIO_DECODE_EVENT (1<<0)
//#define QSPI_COMPLETED_EVENT (1<<1)
#define EVENT_TX_DMA7_COMPLETE (1<<1)
#define UART_TX_EVENT_FIFO_EMPTY (1<<2)
//#define INPUT_EVENT (1<<3)
#define EVENT_RX_DMA8_COMPLETE (1<<3)
//#define NAV_SLEEP_EVENT (1<<4)
#define AUDIO_DECODE_EVENT2 (1<<4)
#define USB_URB_EVENT (1<<5)
#define USB_IRP_EVENT (1<<6)
#define USB_ISR_EVNET (1<<7)
#define USB_HTD_EVNET (1<<8)
#define UART_RX_EVENT_CHAR (1<<9)
#define UART_RX_EVENT_LINE_DATA (1<<10)
#define HDD_READ_FILE_EVENT (1<<11)
#define UART1_TX_EVENT_FIFO_EMPTY (1<<12)
#define UARTB_TX_EVENT_HALF_EMPTY (1<<13)
#define IAP2_BT_RX_PKT (1<<14)
#define SD_DMA_TX_EVENT (1<<15)
#define UART0_TX_EVENT (1<<16)
#define UART0_RX_EVENT (1<<17)
#define BT_CMD_EVENT (1<<18)
#define BT_CONTROLLER_EVENT (1<<19)
#define BT_CONTROLLER_RX_EVENT (1<<20)
#define BT_HOST_INTERNAL_MSG (1<<21)
#define STREAM_EVENT (1<<22)
#define HP_DECODE_EVENT (1<<23)
#define DAPP_EVENT (1<<24)
#define MP3_ENC_EVENT (1<<25)
//#define USB_READ_FILE_EVENT (1<<25)
/*===========================================================================*
*
* Resource Definitions
*
* Define resource names here. Resource names are handles which are used
* merely to look up corresponding resource IDs. Resource names are constant
* to a system and cannot be changed by a ReconfigSys() directive. Thus, all
* configuration tables defined in the system must share resource names.
*
*===========================================================================*/
//Tasks
/*
#define T_DEC 1
#define T_AD 2
#define T_CDSC 3
#define T_UI 4
#define T_KFUN 5
#define T_HDD 6
#define T_USB 7
#define T_IDLE 8*/
//Queues:
/*
#define Q_DEC 1
#define Q_CDSC 2
#define Q_UI 3
#define Q_KFUNC 4
#define Q_HDD 5
#define Q_USBMSG 6
*/
//unit(U32)
#define WIDTH_OF_STREAM_RCV_QUEUE 4
#define WIDTH_OF_CDSC_QUEUE 4
#define WIDTH_OF_DEC_QUEUE 4
#define WIDTH_OF_UI_QUEUE 4
#define WIDTH_OF_KFUNC_QUEUE 4
//#define WIDTH_OF_KFUNC_QUEUE 2
#define WIDTH_OF_AD_QUEUE 4
#define WIDTH_OF_HDD_QUEUE 4
#define WIDTH_OF_USBMSG_QUEUE 8
#define WIDTH_OF_SD_QUEUE 4
#define WIDTH_OF_IPOD_QUEUE 4
#define WIDTH_OF_BtHCI_QUEUE 4
#if 1
#if 0
#define DEPTH_OF_STREAM_RCV_QUEUE 16
#define DEPTH_OF_CDSC_QUEUE 32
#define DEPTH_OF_DEC_QUEUE 32
#define DEPTH_OF_UI_QUEUE 32
#define DEPTH_OF_KFUNC_QUEUE 32
#define DEPTH_OF_BFM_QUEUE 32
#define DEPTH_OF_AD_QUEUE 32
#define DEPTH_OF_HDD_QUEUE 32
#define DEPTH_OF_USBMSG_QUEUE 32
#define DEPTH_OF_SD_QUEUE 8
#define DEPTH_OF_IPOD_QUEUE 16
#define DEPTH_OF_BtHCI_QUEUE 16
#else
#define DEPTH_OF_STREAM_RCV_QUEUE 16
#define DEPTH_OF_CDSC_QUEUE 16//20
#define DEPTH_OF_DEC_QUEUE 8//20
#define DEPTH_OF_UI_QUEUE 16//20
#define DEPTH_OF_KFUNC_QUEUE 16//20
#define DEPTH_OF_BFM_QUEUE 16//20
#define DEPTH_OF_AD_QUEUE 16//20
#define DEPTH_OF_HDD_QUEUE 16//20
#define DEPTH_OF_USBMSG_QUEUE 16//20
#define DEPTH_OF_SD_QUEUE 8
#define DEPTH_OF_IPOD_QUEUE 16
#define DEPTH_OF_BtHCI_QUEUE 16
#endif
#else
#define DEPTH_OF_STREAM_RCV_QUEUE 8
#define DEPTH_OF_CDSC_QUEUE 8
#define DEPTH_OF_DEC_QUEUE 8
#define DEPTH_OF_UI_QUEUE 8
#define DEPTH_OF_KFUNC_QUEUE 8
#define DEPTH_OF_BFM_QUEUE 8
#define DEPTH_OF_AD_QUEUE 8
#define DEPTH_OF_HDD_QUEUE 8
#define DEPTH_OF_USBMSG_QUEUE 8
#define DEPTH_OF_SD_QUEUE 8
#define DEPTH_OF_BtHCI_QUEUE 16
#endif
//Timers:
#define TIMER_1MS 1
#define TIMER_5MS 5
#define TIMER_10MS 10
#define TIMER_15MS 10
#define TIMER_20MS 20
#define TIMER_25MS 25
#define TIMER_50MS 50
#define TIMER_100MS 100
/*
#define CD_TIMER_TIME 25 //25ms
#define CD_FIT_TIMER 25 //25ms
#define CD_INPUT_TIMER 10 //10ms
#define CD_PROCESS_TIMER 50 //50ms
#define CD_BASE_TIMER 5 //5ms
#define CD_BATT_TIME 100 //100ms
*/
//RTOS 5ms
#define CD_FIT_TIMER ((TIMER0_INT_FREQ*25)/1000) //25ms
#define CD_INPUT_TIMER ((TIMER0_INT_FREQ*10)/1000) //10ms
#define CD_PROCESS_TIMER ((TIMER0_INT_FREQ*50)/1000) //50ms
#define CD_BASE_TIMER ((TIMER0_INT_FREQ*5)/1000) //5ms
#define CD_BATT_TIMER ((TIMER0_INT_FREQ*100)/1000) //100ms
#define CD_TIMER_TIME ((TIMER0_MSEC_PER_TICK*CD_FIT_TIMER)) //25ms
#define TIMER_5MS_TICK ((TIMER0_INT_FREQ*5)/1000) // 5ms
#define TIMER_10MS_TICK ((TIMER0_INT_FREQ*10)/1000) //10ms
#define TIMER_15MS_TICK ((TIMER0_INT_FREQ*15)/1000) //15ms
#define TIMER_25MS_TICK ((TIMER0_INT_FREQ*25)/1000) //25ms
/*
//RTOS 10ms
#define CD_FIT_TIMER ((TIMER0_INT_FREQ*20)/1000) //20ms
#define CD_INPUT_TIMER ((TIMER0_INT_FREQ*10)/1000) //10ms
#define CD_PROCESS_TIMER ((TIMER0_INT_FREQ*50)/1000) //50ms
#define CD_BASE_TIMER ((TIMER0_INT_FREQ*10)/1000) //10ms
#define CD_BATT_TIMER ((TIMER0_INT_FREQ*100)/1000) //100ms
#define CD_TIMER_TIMER ((TIMER0_MSEC_PER_TICK*CD_FIT_TIMER)) //20ms
*/
#define TX_INTERRUPT_SAVE_AREA //register int interrupt_save;
//#define TX_INT_DISABLE XCHAL_EXCM_LEVEL /* Disable interrupts value */
//#define TX_INT_ENABLE 0x0 /* Enable interrupt value */
#if defined TX_DISABLE
#undef TX_DISABLE
#endif
#if defined TX_RESTORE
#undef TX_RESTORE
#endif
#define UART_TX_FIFO_ENABLE
//#define UART_RX_FIFO_ENABLE
#define UART0_TX_DMA_8bit
#if 0
#define UART0_ENABLE
#define UART0_INT_ENABLE
#define UART0_TX_FIFO_ENABLE
#define UART0_TX_ENABLE
//#define UART0_RX_ENABLE
//#define UART0_TX_DMA
//#define UART0_RX_DMA
#define UART0_USED_FOR_UI_DEBUG
//#define UART0_USED_FOR_APP_UI
#endif
#if 0
#define UART1_ENABLE
#define UART1_INT_ENABLE
//#define UART1_TX_FIFO_ENABLE
//#define UART0_TX_ENABLE
#define UART1_RX_ENABLE
//#define UART1_RX_FIFO_ENABLE
//#define UART1_USED_FOR_UI_DEBUG
//#define UART1_USED_FOR_APP_UI
#endif
#if 0
#define UART2_ENABLE
#define UART2_INT_ENABLE
#define UART2_TX_FIFO_ENABLE
#define UART2_TX_ENABLE
//#define UART2_RX_ENABLE
//#define UART2_RX_FIFO_ENABLE
#define UART2_USED_FOR_UI_DEBUG
//#define UART2_USED_FOR_APP_UI
#endif
#define USB_WAIT_IRP_EVENT_MAX_TIME (3000 / OS_MSEC_PER_TICK + 1) //3s
#define USB_WAIT_HTD_EVENT_MAX_TIME (1000) //FIXME
int os_mutex_lock(unsigned long *mutexID);
int os_mutex_unlock(unsigned long *mutexID);
int os_event_set(unsigned long event_mask);
int os_event_iset(unsigned long event_mask);
int os_event_clr(unsigned long event_mask);
int os_event_get(unsigned long event_mask);
int os_event_iget(unsigned long event_mask);
int os_event_get_for_wait_xms(unsigned long event_mask, unsigned long wait_xms);
int os_queue_send(void *queueID, unsigned long *msg_buf);
int os_queue_isend(void *queueID, unsigned long *msg_buf);
int os_queue_send_wait_forever(void *queueID, unsigned long *msg_buf);
int os_queue_receive(void *queueID, unsigned long *msg_buf);
int os_queue_receive_for_wait_xms(void *queueID, unsigned long *data, unsigned long wait_xms);
//Mutexes:
extern void * mutex_qspi;
extern void * mutex_i2c0;
extern void * mutex_uart0_tx;
extern void * mutex_uart0_rx;
extern void * mutex_uart1_tx;
extern void * mutex_uart1_rx;
extern void * mutex_uart2_tx;
extern void * mutex_uart2_rx;
extern void * mutex_stream;
extern void * mutex_cd_ervo_if; //for CD Servo Interface
extern void * mutex_usb;
extern void * mutex_fs;
extern void * mutex_mtp;
extern void * gSDmutex;
extern void * gIpodMutex;
extern void * mutex_spi;
extern void *mutex_hef4094;
extern void *event_grop;
//extern void *gSDdmaEvent;
extern void * qStream_Rcv;
extern void * qCDSC;
extern void * qDEC;
extern void * qUI;
extern void * qKFUNC;
extern void * qHDD;
extern void * gUsbQueue;
extern void * gSDqueue;
extern void * gIpodQueue;
extern void * qBtHCI;
extern void *timer_CD_INPUT;
extern void *timer_CD_FIT; //for 25ms timer
extern void *timer_5ms; //for 5ms timer
extern void *timer_10ms; //for 10ms timer
extern void *timer_CD_PROCESS;
//interrupt enable or disable
//They cannot be called from interrupt level.
#if 0
#if 0
#define TX_DISABLE int interrupt_save = portENTER_CRITICAL_NESTED();
#define TX_RESTORE portEXIT_CRITICAL_NESTED(interrupt_save);
#else
#define TX_DISABLE portDISABLE_INTERRUPTS();
#define TX_RESTORE portENABLE_INTERRUPTS();
#endif
#else
#define TX_DISABLE register int interrupt_save; \
interrupt_save = _interrupt_control(XCHAL_EXCM_LEVEL);
#define TX_RESTORE _interrupt_control(interrupt_save)
#endif
//interrupt enable or disable
//They cannot be called from interrupt level.
#if 0
#define TX_DISABLE register int interrupt_save = portENTER_CRITICAL_NESTED()
#define TX_RESTORE portEXIT_CRITICAL_NESTED(interrupt_save)
//#define TX_DISABLE portDISABLE_INTERRUPTS()
//#define TX_RESTORE portENABLE_INTERRUPTS()
//They can be called from interrupt level.
#define TX_iDISABLE register int interrupt_save; \
interrupt_save = portSET_INTERRUPT_MASK_FROM_ISR()
#define TX_iRESTORE portCLEAR_INTERRUPT_MASK_FROM_ISR(interrupt_save)
#endif
#if 1
#define TX_DISABLE register int interrupt_save; \
interrupt_save = _interrupt_control(XCHAL_EXCM_LEVEL)
#define TX_RESTORE _interrupt_control(interrupt_save)
//They can be called from interrupt level.
#define TX_iDISABLE register int interrupt_save; \
interrupt_save = _interrupt_control(XCHAL_EXCM_LEVEL)
#define TX_iRESTORE _interrupt_control(interrupt_save)
#endif
#define TX_SLEEP_MS(xms) vTaskDelay( ((xms + (OS_MSEC_PER_TICK - 1))/OS_MSEC_PER_TICK) );
//Mutex:
#define CD_SERVO_IF_MUTEX_LOCK os_mutex_lock(mutex_cd_ervo_if)
#define CD_SERVO_IF_MUTEX_UNLOCK os_mutex_unlock(mutex_cd_ervo_if)
#define USB_MUTEX_LOCK os_mutex_lock(mutex_usb)
#define USB_MUTEX_UNLOCK os_mutex_unlock(mutex_usb)
#define SDIF_WAIT_TIMEOUT (6000) //3s
#define SD_MUTEX_LOCK os_mutex_lock(gSDmutex)
#define SD_MUTEX_UNLOCK os_mutex_unlock(gSDmutex)
#define SD_MUTEX_TIMEOUT_LOCK os_mutex_lock_for_timeout(gSDmutex, SDIF_WAIT_TIMEOUT)
#define FS_THREAD_LOCK os_mutex_lock(mutex_fs)
#define FS_THREAD_UNLOCK os_mutex_unlock(mutex_fs)
#define STREAM_MUTEX_LOCK os_mutex_lock(mutex_stream)
#define STREAM_MUTEX_UNLOCK os_mutex_unlock(mutex_stream)
#define I2C0_MUTEX_LOCK os_mutex_lock(mutex_i2c0)
#define I2C0_MUTEX_UNLOCK os_mutex_unlock(mutex_i2c0)
#define OS_MUTEX_I2C0_LOCK I2C0_MUTEX_LOCK
#define OS_MUTEX_I2C0_UNLOCK I2C0_MUTEX_UNLOCK
#define SPI_MUTEX_LOCK os_mutex_lock(mutex_spi)
#define SPI_MUTEX_UNLOCK os_mutex_unlock(mutex_spi)
#define UART0_TX_MUTEX_LOCK os_mutex_lock(mutex_uart0_tx)
#define UART0_TX_MUTEX_UNLOCK os_mutex_unlock(mutex_uart0_tx)
#define UART0_RX_MUTEX_LOCK os_mutex_lock(mutex_uart0_rx)
#define UART0_RX_MUTEX_UNLOCK os_mutex_unlock(mutex_uart0_rx)
#define UART1_TX_MUTEX_LOCK os_mutex_lock(mutex_uart1_tx)
#define UART1_TX_MUTEX_UNLOCK os_mutex_unlock(mutex_uart1_tx)
#define UART1_RX_MUTEX_LOCK os_mutex_lock(mutex_uart1_rx)
#define UART1_RX_MUTEX_UNLOCK os_mutex_unlock(mutex_uart1_rx)
#define UART2_TX_MUTEX_LOCK os_mutex_lock(mutex_uart2_tx)
#define UART2_TX_MUTEX_UNLOCK os_mutex_unlock(mutex_uart2_tx)
//jj+
#define UART2_TX_MUTEX_iLOCK os_mutex_ilock(mutex_uart2_tx)
#define UART2_TX_MUTEX_iUNLOCK os_mutex_iunlock(mutex_uart2_tx)
#define OS_MUTEX_QSPI_LOCK os_mutex_lock(mutex_qspi)
#define OS_MUTEX_QSPI_UNLOCK os_mutex_unlock(mutex_qspi)
#if 0
#define MUTEX_HEF4094_LOCK OS_MUTEX_QSPI_LOCK
#define MUTEX_HEF4094_UNLOCK OS_MUTEX_QSPI_UNLOCK
#else
#define MUTEX_HEF4094_LOCK os_mutex_lock(mutex_hef4094)
#define MUTEX_HEF4094_UNLOCK os_mutex_unlock(mutex_hef4094)
#endif
//Event:
#define UART_TX_EVENT_FIFO_EMPTY_SET os_event_set(UART_TX_EVENT_FIFO_EMPTY)
#if 1
#define UART_TX_EVENT_FIFO_EMPTY_iSET os_event_iset(UART_TX_EVENT_FIFO_EMPTY)
#else
#define UART_TX_EVENT_FIFO_EMPTY_iSET \
{\
unsigned long ret;\
ret = xEventGroupSetBitsFromISR( event_grop, UART_TX_EVENT_FIFO_EMPTY, NULL); \
if (ret != TRUE)\
{\
DBG_Assert(FALSE);\
}\
}
#endif
#if 1
#define UART_TX_EVENT_FIFO_EMPTY_GET os_event_get(UART_TX_EVENT_FIFO_EMPTY)
#else
#if 1
#define UART_TX_EVENT_FIFO_EMPTY_GET \
{\
unsigned long ret;\
ret = xEventGroupWaitBits(event_grop, UART_TX_EVENT_FIFO_EMPTY, pdFALSE, pdTRUE, PRINTF_MAX_WAIT_TIME);\
if ( (ret & UART_TX_EVENT_FIFO_EMPTY) != UART_TX_EVENT_FIFO_EMPTY) \
{\
DBG_Assert(FALSE);\
}\
ret = xEventGroupClearBits(event_grop, UART_TX_EVENT_FIFO_EMPTY);\
if ( (ret & UART_TX_EVENT_FIFO_EMPTY) != UART_TX_EVENT_FIFO_EMPTY)\
{\
DBG_Assert(FALSE);\
}\
}
#else
#define UART_TX_EVENT_FIFO_EMPTY_GET \
{\
unsigned long ret;\
ret = xEventGroupWaitBits(event_grop, UART_TX_EVENT_FIFO_EMPTY, pdTRUE, pdTRUE, portMAX_DELAY);\
if ( (ret & UART_TX_EVENT_FIFO_EMPTY) != UART_TX_EVENT_FIFO_EMPTY) \
{\
DBG_Assert(FALSE);\
}\
}
#endif
#endif
#define UART_TX_EVENT_FIFO_EMPTY_CLR os_event_clr(UART_TX_EVENT_FIFO_EMPTY)
#define UART_RX_EVENT_CHAR_SET os_event_set(UART_RX_EVENT_CHAR)
#define UART_RX_EVENT_CHAR_GET os_event_get(UART_RX_EVENT_CHAR)
#define UART_RX_EVENT_CHAR_CLR os_event_clr(UART_RX_EVENT_CHAR)
#define UART_RX_EVENT_LINE_DATA_SET os_event_set(UART_RX_EVENT_LINE_DATA)
#define UART_RX_EVENT_LINE_DATA_GET os_event_get(UART_RX_EVENT_LINE_DATA)
#define UART_RX_EVENT_LINE_DATA_CLR os_event_clr(UART_RX_EVENT_LINE_DATA)
#define UART_RX_EVENT_SET os_event_set(UART_RX_EVENT_CHAR|UART_RX_EVENT_LINE_DATA)
#define UART_RX_EVENT_iSET os_event_iset(UART_RX_EVENT_CHAR|UART_RX_EVENT_LINE_DATA)
#define UART_RX_EVENT_CLR os_event_clr(UART_RX_EVENT_CHAR|UART_RX_EVENT_LINE_DATA)
#define USB_IRP_EVENT_SET os_event_set(USB_IRP_EVENT)
#define USB_IRP_EVENT_iSET os_event_iset(USB_IRP_EVENT)
#define USB_IRP_EVENT_GET os_event_get(USB_IRP_EVENT)
#define USB_IRP_EVENT_CLR os_event_clr(USB_IRP_EVENT)
#define USB_IRP_EVENT_iCLR os_event_iclr(USB_IRP_EVENT)
#define USB_HTD_EVENT_SET os_event_set(USB_HTD_EVNET)
#define USB_HTD_EVENT_iSET os_event_iset(USB_HTD_EVNET)
#define USB_HTD_EVENT_GET os_event_get(USB_HTD_EVNET)
#define USB_HTD_EVENT_CLR os_event_clr(USB_HTD_EVNET)
#define HDD_READ_FILE_EVENT_SET os_event_set(HDD_READ_FILE_EVENT)
#define HDD_READ_FILE_EVENT_GET os_event_get(HDD_READ_FILE_EVENT)
#define HDD_READ_FILE_EVENT_CLR os_event_clr(HDD_READ_FILE_EVENT)
#define HDD_READ_FILE_EVENT_iSET os_event_iset(HDD_READ_FILE_EVENT)
#define AUDIO_DECODE_EVENT_SET os_event_set(AUDIO_DECODE_EVENT)
#if 0
#define AUDIO_DECODE_EVENT_iSET os_event_iset(AUDIO_DECODE_EVENT)
#else
#define AUDIO_DECODE_EVENT_iSET \
{\
unsigned long ret;\
ret = xEventGroupSetBitsFromISR( event_grop, AUDIO_DECODE_EVENT, NULL); \
if (ret != TRUE)\
{\
DBG_Assert(FALSE);\
}\
}
#endif
#define AUDIO_DECODE_EVENT_GET os_event_get(AUDIO_DECODE_EVENT)
#define AUDIO_DECODE_EVENT_CLR os_event_clr(AUDIO_DECODE_EVENT)
#define SD_DMA7_EVENT_SET os_event_set(EVENT_TX_DMA7_COMPLETE)
#if 0
#define SD_DMA7_EVENT_iSET os_event_iset(EVENT_TX_DMA7_COMPLETE)
#else
#define SD_DMA7_EVENT_iSET \
{\
unsigned long ret;\
ret = xEventGroupSetBitsFromISR(event_grop, EVENT_TX_DMA7_COMPLETE, NULL); \
if (ret != TRUE)\
{\
DBG_Assert(FALSE);\
}\
}
#endif
#define SD_DMA_EVENT_TIME_OUT (5000)//5S
#define SD_DMA7_EVENT_GET os_event_get(EVENT_TX_DMA7_COMPLETE)
#define SD_DMA7_EVENT_CLR os_event_clr(EVENT_TX_DMA7_COMPLETE)
#define SD_DMA7_EVENT_TIMEOUT_GET os_event_get_for_wait_xms(EVENT_TX_DMA7_COMPLETE, SD_DMA_EVENT_TIME_OUT)
#define SD_DMA8_EVENT_SET os_event_set(EVENT_RX_DMA8_COMPLETE)
#if 0
#define SD_DMA8_EVENT_iSET os_event_iset(EVENT_RX_DMA8_COMPLETE)
#else
#define SD_DMA8_EVENT_iSET \
{\
unsigned long ret;\
ret = xEventGroupSetBitsFromISR(event_grop, EVENT_RX_DMA8_COMPLETE, NULL); \
if (ret != TRUE)\
{\
DBG_Assert(FALSE);\
}\
}
#endif
#define SD_DMA8_EVENT_GET os_event_get(EVENT_RX_DMA8_COMPLETE)
#define SD_DMA8_EVENT_CLR os_event_clr(EVENT_RX_DMA8_COMPLETE)
#define SD_DMA7_DMA8_EVENT_CLR os_event_clr(EVENT_TX_DMA7_COMPLETE|EVENT_RX_DMA8_COMPLETE)
#define MP3_ENC_EVENT_SET os_event_set(MP3_ENC_EVENT)
#define MP3_ENC_EVENT_GET os_event_get(MP3_ENC_EVENT)
#define UART0_TX_EVENT_SET os_event_set(UART0_TX_EVENT)
#if 1
#define UART0_TX_EVENT_iSET os_event_iset(UART0_TX_EVENT)
#else
#define UART0_TX_EVENT_iSET \
{\
unsigned long ret;\
ret = xEventGroupSetBitsFromISR( event_grop, UART0_TX_EVENT, NULL); \
if (ret != TRUE)\
{\
DBG_Assert(FALSE);\
}\
}
#endif
#define UART0_TX_EVENT_GET os_event_get(UART0_TX_EVENT)
#define UART0_RX_EVENT_SET os_event_set(UART0_RX_EVENT)
#if 1
#define UART0_RX_EVENT_iSET os_event_iset(UART0_RX_EVENT)
#endif
#if 0
#define UART0_RX_EVENT_iSET \
{\
unsigned long ret;\
ret = xEventGroupSetBitsFromISR( event_grop, UART0_RX_EVENT, NULL);\
if (ret != TRUE)\
{\
DBG_Assert(FALSE);\
}\
}
#endif
#if 0
#define UART0_RX_EVENT_iSET xEventGroupSetBitsFromISR( event_grop, UART0_RX_EVENT, NULL);
#endif
#define UART0_RX_EVENT_GET os_event_get(UART0_RX_EVENT)
#define BT_CMD_EVENT_SET os_event_set(BT_CMD_EVENT)
#if 1
//#define BT_CMD_EVENT_GET os_event_get_for_wait_xms(BT_CMD_EVENT, 1000) //1000ms
#define BT_CMD_EVENT_GET os_event_get_for_wait_xms(BT_CMD_EVENT, 1000*4) //1000ms
#else
#define BT_CMD_EVENT_GET \
{\
unsigned long ret;\
unsigned long flag;\
ret = xEventGroupWaitBits(event_grop, UART_TX_EVENT_FIFO_EMPTY, pdTRUE, pdTRUE, 200);\
if ( (ret & UART_TX_EVENT_FIFO_EMPTY) != UART_TX_EVENT_FIFO_EMPTY) \
{\
DBG_Assert(FALSE);\
}\
}
#endif
#define EVENT_BIT_SET( eventID, bit_mask ) \
{\
unsigned long ret;\
ret = xEventGroupSetBits(eventID, bit_mask);\
if ( (ret & bit_mask) != bit_mask)\
{\
DBG_Assert(FALSE);\
}\
}
#define EVENT_BIT_iSET( eventID, bit_mask ) \
{\
unsigned long ret;\
ret = xEventGroupSetBitsFromISR( eventID, bit_mask, NULL); \
if (ret != TRUE)\
{\
DBG_Assert(FALSE);\
}\
}
#define EVENT_BIT_GET( eventID, bit_mask ) \
{\
unsigned long ret;\
ret = xEventGroupWaitBits(eventID, bit_mask, pdFALSE, pdTRUE, portMAX_DELAY);\
if ( (ret & bit_mask) != bit_mask) \
{\
DBG_Assert(FALSE);\
}\
ret = xEventGroupClearBits(eventID, bit_mask);\
if ( (ret & bit_mask) != bit_mask)\
{\
DBG_Assert(FALSE);\
}\
}
#if 0
#define EVENT_BIT_CLR( (eventID), (bit_mask) ) \
{\
unsigned long ret;\
ret = xEventGroupSetBits(eventID, ~(bit_mask));\
if ( (ret & (bit_mask)) != (bit_mask))\
{\
DBG_Assert(FALSE);\
}\
}
#else
#define EVENT_BIT_CLR( eventID, bit_mask ) \
{\
unsigned long ret;\
ret = xEventGroupClearBits(eventID, bit_mask);\
if ( (ret & (bit_mask)) != (bit_mask))\
{\
DBG_Assert(FALSE);\
}\
}
#endif
//Queue:
#define QUEUE_UI_SEND os_queue_send(qUI, data)
#define QUEUE_UI_iSEND os_queue_isend(qUI, data)
#define QUEUE_UI_RECEIVE os_queue_receive(qUI, data)
#define QUEUE_HDD_SEND os_queue_send(qHDD, data)
#define QUEUE_HDD_iSEND os_queue_isend(qHDD, data)
#if 1
#define QUEUE_HDD_RECEIVE os_queue_receive(qHDD, data)
#else
#define QUEUE_HDD_RECEIVE \
{\
U32 ret; \
ret = xQueueReceive( qHDD, (void *)qBuf, portMAX_DELAY ); \
if (ret != TRUE) \
{\
DBG_Assert(FALSE);\
}\
}
#endif
#define QUEUE_DEC_SEND os_queue_send(qDEC, data )
#if 1
#define QUEUE_DEC_iSEND os_queue_isend(qDEC, data )
#else
#define QUEUE_DEC_iSEND \
{\
U32 ret;\
ret = xQueueSend( qDEC, data, 0 );\
if (ret != TRUE)\
{\
DBG_Assert(FALSE);\
return FALSE;\
}\
return TRUE;\
}
#endif
#define QUEUE_DEC_SEND_WAIT_FOREVER os_queue_send_wait_forever(qDEC, data )
#define QUEUE_DEC_RECEIVE os_queue_receive(qDEC, data )
#define QUEUE_USB_SEND os_queue_send(gUsbQueue, data)
#define QUEUE_USB_iSEND os_queue_isend(gUsbQueue, data)
#define QUEUE_USB_RECEIVE os_queue_receive(gUsbQueue, data)
#define QUEUE_KEYFUNC_SEND os_queue_send(qKFUNC, data)
#define QUEUE_KEYFUNC_iSEND os_queue_isend(qKFUNC, data)
#define QUEUE_KEYFUNC_RECEIVE os_queue_receive(qKFUNC, data)
#define QUEUE_STREAM_RCV_SEND os_queue_send(qStream_Rcv, data )
#define QUEUE_STREAM_RCV_iSEND os_queue_isend(qStream_Rcv, data )
#define QUEUE_STREAM_RCV_RECEIVE os_queue_receive(qStream_Rcv, data )
#define QUEUE_CDSC_SEND os_queue_send(qCDSC, data )
#define QUEUE_CDSC_iSEND os_queue_isend(qCDSC, data )
#define QUEUE_CDSC_RECEIVE os_queue_receive(qCDSC, data )
#define QUEUE_SD_SEND os_queue_send(gSDqueue, data )
#if 1
#define QUEUE_SD_iSEND os_queue_isend(gSDqueue, data )
#else
#define QUEUE_SD_iSEND \
{\
U32 ret;\
ret = xQueueSendToBackFromISR(gSDqueue, data, NULL);\
if (ret != TRUE)\
{\
DBG_Assert(FALSE);\
return FALSE;\
}\
return TRUE;\
}
#endif
#define SD_QUEUE_TIME_OUT (5000) //5s
#define QUEUE_SD_RECEIVE os_queue_receive(gSDqueue, data )
#define QUEUE_SD_RECEIVE_TIMEOUT os_queue_receive_for_wait_xms(gSDqueue, data, SD_QUEUE_TIME_OUT)
#define QUEUE_SD_CLEAR os_queue_clear(gSDqueue)
#if 0
#define QUEUE_BT_HCI_SEND os_queue_send(qBtHCI, data)
#else
#define QUEUE_BT_HCI_SEND os_queue_send(qBtHCI, data); \
xEventGroupSetBits(event_grop, BT_HOST_INTERNAL_MSG);
#endif
#if 0
#define QUEUE_BT_HCI_RECEIVE os_queue_receive(qBtHCI, data)
#else
#define QUEUE_BT_HCI_RECEIVE os_queue_receive_for_wait_xms(qBtHCI, data, 0) //No Wait:0ms
#if 0
#define QUEUE_MSG_SEND(qID, qBuf) \
xQueueSend( qID, (void *)qBuf, 0 )
#else
#define QUEUE_MSG_SEND(qID, qBuf) \
{\
U32 ret;\
ret = xQueueSend( qID, (void *)qBuf, 0 );\
if (ret != TRUE)\
{\
DBG_Assert(FALSE);\
}\
}
#endif
#endif
#if 0
#define QUEUE_MSG_iSEND(qID, qBuf) \
xQueueSendToBackFromISR( gUsbQueue, (void *)msg_buf, NULL )
#else
#define QUEUE_MSG_iSEND(qID, qBuf) \
{\
U32 ret;\
ret = xQueueSendToBackFromISR( gUsbQueue, (void *)qBuf, NULL );\
if (ret != TRUE)\
{\
DBG_Assert(FALSE);\
}\
}
#endif
#if 0
#define QUEUE_MSG_RECEIVE(qID, qBuf) \
xQueueReceive( gUsbQueue, (void *)msg_buf, portMAX_DELAY )
#else
#define QUEUE_MSG_RECEIVE(qID, qBuf) \
{\
U32 ret; \
ret = xQueueReceive( gUsbQueue, (void *)qBuf, portMAX_DELAY ); \
if (ret != TRUE) \
{\
DBG_Assert(FALSE);\
}\
}
#endif
//xSemaphoreGive( gUartSemphrBinnary );
//xSemaphoreTake(gUartSemphrBinnary, portMAX_DELAY);
//xSemaphoreTake(gUartSemphrBinnary, 0);
//#define BTDM_CONTROLLER_ONLY
#endif //_OS_CONFIG_H