hw_pll.h
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/*
* hw_pll.h
*
* Created on: 2019-7-11
* Author: Windowns
*/
#ifndef _HW_PLL_H_
#define _HW_PLL_H_
#include "hw_da_pp.h"
extern unsigned long SystemClock;
//#define PWM_768_4096 //4096 sample/frame
//#define PWM_768_2048 //2048 sample/frame
//#define PWM_2304x
//#define DMIC_TEST
//#define CLKSSCG_ENABLE
#define CRYSTAL_FREQ (24*1000*1000)
#define CLK_BASE_FREQ (1000*1000)
enum CPU_CLOCK {
CPU_24MHz = (24*CLK_BASE_FREQ), /*CPU 24MHz, AHB 12MHz, 1/2 BTDM 12MHz*/
CPU_32MHz = (32*CLK_BASE_FREQ), /*CPU 32MHz, AHB 16MHz, 1/2 BTDM 16MHz*/
CPU_48MHz = (48*CLK_BASE_FREQ), /*CPU 48MHz, AHB 24MHz, 1/4 BTDM 12MHz*/
CPU_64MHz = (64*CLK_BASE_FREQ), /*CPU 64MHz, AHB 32MHz, 1/4 BTDM 16MHz*/
CPU_72MHz = (72*CLK_BASE_FREQ), /*CPU 72MHz, AHB 36MHz, 1/6 BTDM 12MHz*/
CPU_96MHz = (96*CLK_BASE_FREQ), /*CPU 96MHz, AHB 48MHz, 1/6 BTDM 16MHz*/
CPU_120MHz = (120*CLK_BASE_FREQ), /*CPU 120MHz, AHB 60MHz, 1/10 BTDM 12MHz*/
CPU_128MHz = (128*CLK_BASE_FREQ) /*CPU 128MHz, AHB 64MHz, 1/16 BTDM 16MHz*/
};
#ifdef LOW_POWER_MODE
#define SYS_CLK_FREQ_DEFAULT CPU_32MHz
#else
//#define SYS_CLK_FREQ_DEFAULT CPU_32MHz
#define SYS_CLK_FREQ_DEFAULT CPU_64MHz
//#define SYS_CLK_FREQ_DEFAULT CPU_72MHz
//#define SYS_CLK_FREQ_DEFAULT CPU_96MHz
//#define SYS_CLK_FREQ_DEFAULT CPU_120MHz
//#define SYS_CLK_FREQ_DEFAULT CPU_128MHz
#endif
#define SYSTEM_CLKS SYS_CLK_FREQ_DEFAULT
#if 1
#define BUS_CLKS (SYSTEM_CLKS/2)
#else
#define BUS_CLKS (SystemClock/2)
#endif
#if 1
#define XT_CLOCK_FREQ SYSTEM_CLKS
#else
#define XT_CLOCK_FREQ SystemClock
#endif
enum SF_BASE {
SF_BASE_48000,
SF_BASE_44100,
SF_BASE_32000,
SF_BASE_DET //for spdif sf detect, at current it is 49kHz sample frequency
};
enum PWM_MODE {
PWM_384,
PWM_768_4096x, //768 8b pwm
PWM_768_2048x, //768 7b pwm
PWM_2304
};
enum SPDIF_SF {
SPDIF_SF_1x = 2, //32,44.1,48
SPDIF_SF_2x = 1, //64/88.2/96
SPDIF_SF_4x = 0, //128/176.4/192
/***********************/
SPDIF_SF_hx = 3 //half, 16,22.05,24
};
#define SS_DIVVAL 5
#define SS_SPREAD 1
//#define SS_DIVVAL 12
//#define SS_SPREAD 16
void hw_soc_pll_set (u8 enable, u32 freq);
void hw_audio_pll_set (u8 enable, u8 CLKSSCG_en, u8 sf_base, u8 pwm_out_en, u8 pwm_mode, u8 spdif_dec_en, u8 spdif_dec_sf, u8 adda_en, u8 mclk_en);
void hw_audio_pll_clk_fre_set (u8 sf_base,u8 spdif_dec_sf);
void hw_pll_headphone_sample_rate_set(int sample_rate);
#endif //_HW_PLL_H_