#include "c_def.h"
#include "debug.h"
#include "oem.h"

#include "hw_iis.h"

#include "mem_reloc.h"

#include "hw_da_pp.h"
#include "audio_pll.h"

//#include "app_dec.h"

//#include "optek_d2as_table.h"
//#include "optek_dsp_ip.h"


U32 gAudioFNPLLFrac;
U8 audio_pll;
U8 fn_pll;

U16 pll_lock_cn,pll_lock_cn_p,pll_lock_cn_n;
U16 pll_lock_interval;

/* ((44100) * 256 * 8 * 6)/6000000 = 90.3168 */
/* 0.3168 * 1048576 (0x100000) = 332188.8768 */
#define FN_FRAC_44100_NORMAL		332189		//0x5119D
/*(((44100 x 0.01%) * 256 * 8 * 6)/6000000) * 1048576  = 9470.40288768*/
#define FN_FRAC_44100_100PP		9470

#define FN_FRAC_44100_M100PP	(FN_FRAC_44100_NORMAL - 1 * FN_FRAC_44100_100PP)		
#define FN_FRAC_44100_M200PP	(FN_FRAC_44100_NORMAL - 2 * FN_FRAC_44100_100PP)	
#define FN_FRAC_44100_M400PP	(FN_FRAC_44100_NORMAL - 4 * FN_FRAC_44100_100PP)	
#define FN_FRAC_44100_P100PP	(FN_FRAC_44100_NORMAL + 1 * FN_FRAC_44100_100PP)	
#define FN_FRAC_44100_P200PP	(FN_FRAC_44100_NORMAL + 2 * FN_FRAC_44100_100PP)	
#define FN_FRAC_44100_P400PP	(FN_FRAC_44100_NORMAL + 4 * FN_FRAC_44100_100PP)


/* ((44100) * 256 * 8 * 4)/6000000 = 60.2112 */
/* 0.2112 * 1048576 (0x100000) = 221459.2512 */
#define FN_FRAC_44100_4X_NORMAL		221459		//0x36113
/* (((44100 x 0.01%) * 256 * 8 * 4)/6000000) *  1048576 = 6313.60192512 */
#define FN_FRAC_44100_4X_100PP		6314		//0x36113

#define FN_FRAC_44100_4X_M100PP		(FN_FRAC_44100_4X_NORMAL - 1 * 	FN_FRAC_44100_4X_100PP)	
#define FN_FRAC_44100_4X_M200PP		(FN_FRAC_44100_4X_NORMAL - 2 * 	FN_FRAC_44100_4X_100PP)
#define FN_FRAC_44100_4X_M400PP		(FN_FRAC_44100_4X_NORMAL - 4 * 	FN_FRAC_44100_4X_100PP)
#define FN_FRAC_44100_4X_P100PP		(FN_FRAC_44100_4X_NORMAL + 1 * 	FN_FRAC_44100_4X_100PP)
#define FN_FRAC_44100_4X_P200PP		(FN_FRAC_44100_4X_NORMAL + 2 * 	FN_FRAC_44100_4X_100PP)
#define FN_FRAC_44100_4X_P400PP		(FN_FRAC_44100_4X_NORMAL + 4 * 	FN_FRAC_44100_4X_100PP)





/* ((48000) * 256 * 8 * 6)/6000000 = 98.304 */
/* 0.304 * 1048576 (0x100000) = 318767.104 */
#define FN_FRAC_48000_NORMAL		(318767)		//0x4dd2f
/* (((48000 x 0.01%) * 256 * 8 * 6)/6000000) * 1048576 = 10307.9215104 */
#define FN_FRAC_48000_100PP			10308

#define FN_FRAC_48000_M100PP		(FN_FRAC_48000_NORMAL - 1 * FN_FRAC_48000_100PP)
#define FN_FRAC_48000_M200PP		(FN_FRAC_48000_NORMAL - 2 * FN_FRAC_48000_100PP)
#define FN_FRAC_48000_M400PP		(FN_FRAC_48000_NORMAL - 4 * FN_FRAC_48000_100PP)
#define FN_FRAC_48000_P100PP		(FN_FRAC_48000_NORMAL + 1 * FN_FRAC_48000_100PP)
#define FN_FRAC_48000_P200PP		(FN_FRAC_48000_NORMAL + 2 * FN_FRAC_48000_100PP)
#define FN_FRAC_48000_P400PP		(FN_FRAC_48000_NORMAL + 4 * FN_FRAC_48000_100PP)


/* ((48000) * 256 * 8 * 4)/6000000 = 65.536 */
/* 0.536 * 1048576 (0x100000) = 562036.736*/
#define FN_FRAC_48000_4X_NORMAL		562037 //0x89374
/* (((48000 x 0.01%) * 256 * 8 * 4)/6000000) * 1048576 = 6871.9476736 */
#define FN_FRAC_48000_4X_100PP		6872

#define FN_FRAC_48000_4X_M100PP		(FN_FRAC_48000_4X_NORMAL - 1 * FN_FRAC_48000_4X_100PP)
#define FN_FRAC_48000_4X_M200PP		(FN_FRAC_48000_4X_NORMAL - 2 * FN_FRAC_48000_4X_100PP)
#define FN_FRAC_48000_4X_M400PP		(FN_FRAC_48000_4X_NORMAL - 4 * FN_FRAC_48000_4X_100PP)
#define FN_FRAC_48000_4X_P100PP		(FN_FRAC_48000_4X_NORMAL + 1 * FN_FRAC_48000_4X_100PP)
#define FN_FRAC_48000_4X_P200PP		(FN_FRAC_48000_4X_NORMAL + 2 * FN_FRAC_48000_4X_100PP)
#define FN_FRAC_48000_4X_P400PP		(FN_FRAC_48000_4X_NORMAL + 4 * FN_FRAC_48000_4X_100PP)


/* ((32000) * 256 * 8 * 8)/6000000 = 87.381333333 */
/* 0.381333333 * 1048576 (0x100000) = 399856.980983808e */
#define FN_FRAC_32000_NORMAL		399857

/* (((32000 x 0.01%) * 256 * 8 * 8)/6000000) * 1048576  = 9162.5968981333333333333333333333 */
#define FN_FRAC_32000_100PP		9163

#define FN_FRAC_32000_M100PP	(FN_FRAC_32000_NORMAL - 1 * FN_FRAC_32000_100PP)
#define FN_FRAC_32000_M200PP	(FN_FRAC_32000_NORMAL - 2 * FN_FRAC_32000_100PP)
#define FN_FRAC_32000_M400PP	(FN_FRAC_32000_NORMAL - 4 * FN_FRAC_32000_100PP)
#define FN_FRAC_32000_P100PP	(FN_FRAC_32000_NORMAL + 1 * FN_FRAC_32000_100PP)
#define FN_FRAC_32000_P200PP	(FN_FRAC_32000_NORMAL + 2 * FN_FRAC_32000_100PP)
#define FN_FRAC_32000_P400PP	(FN_FRAC_32000_NORMAL + 4 * FN_FRAC_32000_100PP)

const U32 fn_table [9][7] = {
	{FN_FRAC_44100_NORMAL, FN_FRAC_44100_P100PP,FN_FRAC_44100_P200PP,FN_FRAC_44100_P400PP,FN_FRAC_44100_M100PP, FN_FRAC_44100_M200PP,FN_FRAC_44100_M400PP},
	{FN_FRAC_44100_NORMAL, FN_FRAC_44100_P100PP,FN_FRAC_44100_P200PP,FN_FRAC_44100_P400PP,FN_FRAC_44100_M100PP, FN_FRAC_44100_M200PP,FN_FRAC_44100_M400PP},
	{FN_FRAC_44100_4X_NORMAL, FN_FRAC_44100_4X_P100PP,FN_FRAC_44100_4X_P200PP,FN_FRAC_44100_4X_P400PP,FN_FRAC_44100_4X_M100PP, FN_FRAC_44100_4X_M200PP,FN_FRAC_44100_4X_M400PP},

	{FN_FRAC_48000_NORMAL, FN_FRAC_48000_P100PP,FN_FRAC_48000_P200PP,FN_FRAC_48000_P400PP,FN_FRAC_48000_M100PP, FN_FRAC_48000_M200PP,FN_FRAC_48000_M400PP},
	{FN_FRAC_48000_NORMAL, FN_FRAC_48000_P100PP,FN_FRAC_48000_P200PP,FN_FRAC_48000_P400PP,FN_FRAC_48000_M100PP, FN_FRAC_48000_M200PP,FN_FRAC_48000_M400PP},
	{FN_FRAC_48000_4X_NORMAL, FN_FRAC_48000_4X_P100PP,FN_FRAC_48000_4X_P200PP,FN_FRAC_48000_4X_P400PP,FN_FRAC_48000_4X_M100PP, FN_FRAC_48000_4X_M200PP,FN_FRAC_48000_4X_M400PP},

	{FN_FRAC_32000_NORMAL, FN_FRAC_32000_P100PP,FN_FRAC_32000_P200PP,FN_FRAC_32000_P400PP,FN_FRAC_32000_M100PP, FN_FRAC_32000_M200PP,FN_FRAC_32000_M400PP},
	{FN_FRAC_32000_NORMAL, FN_FRAC_32000_P100PP,FN_FRAC_32000_P200PP,FN_FRAC_32000_P400PP,FN_FRAC_32000_M100PP, FN_FRAC_32000_M200PP,FN_FRAC_32000_M400PP},
	{FN_FRAC_32000_NORMAL, FN_FRAC_32000_P100PP,FN_FRAC_32000_P200PP,FN_FRAC_32000_P400PP,FN_FRAC_32000_M100PP, FN_FRAC_32000_M200PP,FN_FRAC_32000_M400PP},
};


//#define MCLK_384					/*if defined out mclk 384x, else output 256x*/
#define FNPLL_ADJUST_ENABLE			/*fn pll adjust according to stream buf size*/

//#define FNPLL_SUBW

U16 fnpll_adjust_time;
I16 fnpll_adjust_frac;

U16 pll_lock_cn;


#define FNPLL_ADJUST_INTERVAL    ((75*3)*5)

#define MAX_FNPLL_ERR    32
#define FNPLL_ERR_SHIFT  5    /*2^4=16*/
#define FNPLL_10PPM      1024 /*about*/
//#define FNPLL_10PPM      (1024/8) /*1.25ppm*/
//I8 fnpll_err[MAX_FNPLL_ERR];


U32 audio_fnpll_adjust(U32 step)
{

}

U16 pre_audio_freq;

void audio_pll_init (void)
{
#if 0	
	volatile U32 tmp;
	AUDIO_FNPLL_CONTROLs *fnpll_ctrl;
	AUDIO_PLL_CONTROLs *pll_ctrl;
	AUDIO_CLK_CONFIGs *clk_config;

	pll_lock_interval = 6000;

	fnpll_adjust_time = FNPLL_ADJUST_INTERVAL; 
	fnpll_adjust_frac = 0;

	tmp = AUDIO_PLL_CONFIG;
	pll_ctrl = (AUDIO_PLL_CONTROLs *) &tmp;				
	pll_ctrl->sleep = 1;						//output is disable
	AUDIO_PLL_CONFIG = tmp;

	tmp = 0;

	fnpll_ctrl = (AUDIO_FNPLL_CONTROLs *) &tmp;

	/*Traget frequency 44100 or 48000 * 4 * 12/6*/
	/*pll frac = 0.xxxx * 1048576 (0x100000)*/

	fnpll_ctrl->sleep = 0;
	fnpll_ctrl->od = 0;
	fnpll_ctrl->reset = 0;

	fnpll_ctrl->M = 90;								//44100
	fnpll_ctrl->N = 4;

	//fnpll_ctrl->M = 98;							//48000
	//fnpll_ctrl->N = 4;

	fnpll_ctrl->select = 0;
	//fnpll_ctrl->fs = 1;
	fnpll_ctrl->fs = 0;								//franc is added after multiple pll lock 

	AUDIO_FNPLL_CONFIG = tmp;

	//audio_pll_mode = FNPLL_FOR_44P1K;

	AUDIO_FNPLL_FRAC = FN_FRAC_44100_NORMAL;		//44100
	//AUDIO_FNPLL_FRAC = FN_FRAC_48000_NORMAL;		//48000


	//config audio pll
	tmp = 0;
	
	pll_ctrl = (AUDIO_PLL_CONTROLs *) &tmp;
	
	pll_ctrl->sleep = 0;
	pll_ctrl->od = 1;
	pll_ctrl->M = 32;
	pll_ctrl->N = 2;
	
	AUDIO_PLL_CONFIG = tmp;
	DBG_Printf("Audio Pll Con0: 0x%x\n\r", tmp);

	tmp = 0;

	clk_config = (AUDIO_CLK_CONFIGs *) &tmp;

	clk_config->fnpll_xin_s = 0; //CLOCK_24M
	clk_config->pll_xin_s = 3; //audio_fn_pll_clk out
	//clk_config->pll_xin_s = 4; //spdif bit

#if ( ((defined AUDIO_OUT_FROM_I2S1) || (defined AUDIO_OUT_FROM_I2S2)) && (defined AUDIO_ORIGINAL_DATA_OUTPUT) )

	//clk_config->audio_pll_n1 = 1;
	clk_config->audio_pll_n1 = 7;					//11.2896*1
#else

	//clk_config->audio_pll_n1 = 1;

#if defined PWM_8_BITS
	clk_config->audio_pll_n1 = 1;					//11.2896*4
#elif defined PWM_7_BITS

#ifdef PWM_PD
	//for Mono channel output
	clk_config->audio_pll_n1 = 2;					//11.2896*4, 1/6
#else
	//clk_config->audio_pll_n1 = 2;					//11.2896*4
#ifdef AUDIO_CLK_SET_1
	clk_config->audio_pll_n1 = 5;					//11.2896*2
#else
	clk_config->audio_pll_n1 = 3;					//11.2896*2
#endif

	//clk_config->audio_pll_n1 = 7;					//11.2896*1
	//clk_config->audio_pll_n1 = 11;				//11.2896*1
#endif //PWM_PD

#elif defined PWM_6_BITS
	clk_config->audio_pll_n1 = 7;					//11.2896*1
#endif //PWM_6_BITS

#endif //AUDIO_OUT_FROM_I2S1


	//clk_config->audio_pll_n2 = 3;					//11.2896*2
	//clk_config->audio_pll_n2 = 7;					//(1/16)11.2896*1
	//clk_config->audio_pll_n2 = 0xB;				//(1/24)11.2896


	clk_config->audio_fnpll_n1 = 5;  //for MCLK1 and MCLK2, the frequency is 1/(x+1) times

#ifdef AUDIO_ORIGINAL_DATA_OUTPUT
	//LRCK: 44.1kHz
	clk_config->audio_pll_n1 = 7;    //for MCLK1,LRCK,BCK, the frequency is 1/(x+1) times
#else
	//LRCK: 88.2kHz
	clk_config->audio_pll_n1 = 3;    //for MCLK1,LRCK,BCK, the frequency is 1/(x+1) times
#endif

	//MCLK2 is 11.2896 Mhz
	//clk_config->audio_pll_n2 = 7;    //only for MCLK2, the frequency is 1/(x+1) times

	//MCLK2 is 11.2896*2 Mhz
	clk_config->audio_pll_n2 = 3;    //only for MCLK2, the frequency is 1/(x+1) times


#if 0
	clk_config->mclk1_s = 1; //checking fn pll clk
#else
	clk_config->mclk1_s = 0; //checking da pp clk
#endif

	clk_config->mclk2_s = 0;

	clk_config->mclk1_in_out = 1; //MCLK_OUTPUT;
	clk_config->mclk2_in_out = 1; //MCLK_OUTPUT;

	clk_config->mclk_s = 0;
	
	AUDIO_CLK_CONFIG = tmp;
	DBG_Printf("Audio Clk Config0: 0x%x\n\r", tmp);

	//pre_audio_freq = SR_44100_SPDIF_1x;
	pre_audio_freq = -1;

	delayms (25);					//waiting pll clk stable
#endif	
}

void audio_pll_open (void)
{
}

void audio_pll_clsoe(void)
{
}

void audio_pll_fini(void)
{
#if 0	
/*
	volatile U32 tmp;
	AUDIO_FNPLL_CONTROLs *fnpll_ctrl;
	AUDIO_PLL_CONTROLs *pll_ctrl;
	
	
	//config audio pll to sleep
	tmp = AUDIO_PLL_CONFIG;
	
	pll_ctrl = (AUDIO_PLL_CONTROLs *) &tmp;
	
	pll_ctrl->sleep = 1;
	
	AUDIO_PLL_CONFIG = tmp;
			
	tmp = AUDIO_FNPLL_CONFIG;
	
	fnpll_ctrl = (AUDIO_FNPLL_CONTROLs *) &tmp;
	
	fnpll_ctrl->sleep = 1;
	
	AUDIO_FNPLL_CONFIG = tmp;
*/

	//reset value
	AUDIO_PLL_CONFIG = 0x01;
	AUDIO_FNPLL_CONFIG = 0x01;
	AUDIO_CLK_CONFIG = 0x0;
	AUDIO_FNPLL_FRAC = 0x0;
#endif	
}

//void audio_pll_adjust_d16 (U16 size)	;
//void audio_pll_adjust_d24 (U16 size)	;

void audio_pll_adjust_d16 (U16 size)
{
#if 0//def FNPLL_ADJUST_ENABLE
	if (fnpll_adjust_time > 0) {
		fnpll_adjust_time--;
		return;
	} 

	if (size > EX_AUDIO_STREAM_THRESHOLD + 2*EX_AUDIO_STREAM_THRESHOLD_STEP) {
		if (fn_pll != FN_P200PP) {
			//AUDIO_FNPLL_FRAC = FN_FRAC_44100_P200PP;						//+
			AUDIO_FNPLL_FRAC = fn_table[audio_pll][fn_pll];
			fn_pll = FN_P200PP;
			fnpll_adjust_time = FNPLL_ADJUST_INTERVAL; 
			DBG_Printf ("FN P200PP\n\r");
		}
	}
	else if (size > EX_AUDIO_STREAM_THRESHOLD + EX_AUDIO_STREAM_THRESHOLD_STEP) {
		if (fn_pll == FN_M200PP || fn_pll == FN_M100PP) {
			//form minus, just adjust to normal
			//AUDIO_FNPLL_FRAC = FN_FRAC_44100_NORMAL;						//+
			fn_pll = FN_P100PP;
			AUDIO_FNPLL_FRAC = fn_table[audio_pll][FN_Normal];
			fnpll_adjust_time = FNPLL_ADJUST_INTERVAL; 
			DBG_Printf ("FN Normal\n\r");
		}
		else if (fn_pll != FN_P200PP && fn_pll != FN_P100PP) {
			//AUDIO_FNPLL_FRAC = FN_FRAC_44100_P100PP;						//+
			fn_pll = FN_P100PP;
			AUDIO_FNPLL_FRAC = fn_table[audio_pll][fn_pll];
			fnpll_adjust_time = FNPLL_ADJUST_INTERVAL; 
			DBG_Printf ("FN P100PP\n\r");
		}
	}
	else if (size < EX_AUDIO_STREAM_THRESHOLD - 2*EX_AUDIO_STREAM_THRESHOLD_STEP) {
		if (fn_pll != FN_M200PP) {
			//AUDIO_FNPLL_FRAC = FN_FRAC_44100_M200PP;						//+
			fn_pll = FN_M200PP;
			AUDIO_FNPLL_FRAC = fn_table[audio_pll][fn_pll];
			fnpll_adjust_time = FNPLL_ADJUST_INTERVAL; 
			DBG_Printf ("FN M200PP\n\r");
		}
	}
	else if (size < EX_AUDIO_STREAM_THRESHOLD - 1*EX_AUDIO_STREAM_THRESHOLD_STEP) {
		if (fn_pll == FN_P200PP || fn_pll == FN_P100PP) {
			//form plus, just adjust to normal
			//AUDIO_FNPLL_FRAC = FN_FRAC_44100_NORMAL;						//+
			fn_pll = FN_M100PP;
			AUDIO_FNPLL_FRAC = fn_table[audio_pll][FN_Normal];
			fnpll_adjust_time = FNPLL_ADJUST_INTERVAL; 
			DBG_Printf ("FN Normal\n\r");		
		}
		else if (fn_pll != FN_M200PP && fn_pll != FN_M100PP) {
			//AUDIO_FNPLL_FRAC = FN_FRAC_44100_M100PP;						//+
			fn_pll = FN_M100PP;
			AUDIO_FNPLL_FRAC = fn_table[audio_pll][fn_pll];
			fnpll_adjust_time = FNPLL_ADJUST_INTERVAL; 
			DBG_Printf ("FN M100PP\n\r");  
		}		
	}
#endif
}

void audio_pll_adjust_d24 (U16 size)
{

}

void audio_pll_set_default (void)
{
#if 0
	audio_pll_set_fnpll_clk_in ();

#ifdef BT_HCI_ENABLE
	if (bt_get_hp_status() == TRUE) 
	{
		audio_pll_set (SR_48000_SPDIF_1x);
	}
	else 
#endif
	{
		audio_pll_set (SR_44100_SPDIF_1x);
	}
#endif
}

void audio_pll_set (U16 freq)
{
#if 0
	volatile U32 tmp;
	AUDIO_FNPLL_CONTROLs *fnpll_ctrl;
	AUDIO_PLL_CONTROLs *pll_ctrl;
	AUDIO_CLK_CONFIGs *clk_config;

	if (freq == pre_audio_freq)
	{
		DBG_Printf("pll was set:%d\n\r",freq);
		return;
	}

	DBG_Printf("pll set:%d\n\r",freq);

	fnpll_adjust_time = FNPLL_ADJUST_INTERVAL; 
	fnpll_adjust_frac = 0;

	//DA_PP_CLASSD_EN = 0x0; //classd disable, audio clk is not gen except mclk
	DA_PP_MUTE_EN = TRUE;

	tmp = AUDIO_PLL_CONFIG;
	pll_ctrl = (AUDIO_PLL_CONTROLs *) &tmp;				
	pll_ctrl->sleep = 1;						//output is disable
	AUDIO_PLL_CONFIG = tmp;

	tmp = AUDIO_CLK_CONFIG;
	clk_config = (AUDIO_CLK_CONFIGs *) &tmp;	
	clk_config->pll_xin_s = 3;					//fn pll clk 
	AUDIO_CLK_CONFIG = tmp;


	switch (freq)
	{
	case SR_44100_SPDIF_1x:
		{
			/*11289600 x 8 x 6 / 6000000 = 90.3168, FRAC 0.3168 x 1048576 (0x100000) = 0x5119D*/

			tmp = AUDIO_FNPLL_CONFIG;
			
			fnpll_ctrl = (AUDIO_FNPLL_CONTROLs *) &tmp;
			
			fnpll_ctrl->M = 90;
			fnpll_ctrl->N = 4;
			
			AUDIO_FNPLL_CONFIG = tmp;
						
			AUDIO_FNPLL_FRAC = FN_FRAC_44100_NORMAL;						//44100


			tmp = AUDIO_CLK_CONFIG;
			clk_config = (AUDIO_CLK_CONFIGs *) &tmp;
			clk_config->audio_fnpll_n1 = 5;					//(1/12) spdif dec 1x
			//clk_config->audio_fnpll_n1 = 2;					//(1/6) spdif dec 2x
			AUDIO_CLK_CONFIG = tmp;	


			tmp = AUDIO_PLL_CONFIG;
			pll_ctrl = (AUDIO_PLL_CONTROLs *) &tmp;				
			pll_ctrl->M = 48;
			pll_ctrl->N = 2;
			pll_ctrl->sleep = 0;
			AUDIO_PLL_CONFIG = tmp;


			audio_pll = SR_44100_SPDIF_1x;
			fn_pll = FN_Normal;			

#ifdef BT_HEADPHONE
			//d2as
			DBG_Printf("size%d\n",optek_dsrc_alloc( 12, 512, OUT_SAMPLE_MASK, 2,PROCESSING_DATA_16b));

			hp_d2as_obj = optek_dsrc_open(hp_d2as_process_buffer, 12, 512, P160_M12_coeffs, 0,SPDIF_44100_BASE_STEP,SPDIF_44100_BASE_INTER_D,OUT_SAMPLE_MASK,2,PROCESSING_DATA_16b);				/*Nyquistx 160*/

			DBG_Assert (hp_d2as_obj != NULL);
#endif

		}
		break;
	case SR_44100_SPDIF_2x:
		{
			/*11289600 x 8 x 6 / 6000000 = 90.3168, FRAC 0.3168 x 1048576 (0x100000) = 0x5119D*/
			
			tmp = AUDIO_FNPLL_CONFIG;
			
			fnpll_ctrl = (AUDIO_FNPLL_CONTROLs *) &tmp;
			
			fnpll_ctrl->M = 90;
			fnpll_ctrl->N = 4;
			
			AUDIO_FNPLL_CONFIG = tmp;
			
			AUDIO_FNPLL_FRAC = FN_FRAC_44100_NORMAL;						//44100
			
			
			tmp = AUDIO_CLK_CONFIG;
			clk_config = (AUDIO_CLK_CONFIGs *) &tmp;
			//clk_config->audio_fnpll_n1 = 5;					//(1/12) spdif dec 1x
			clk_config->audio_fnpll_n1 = 2;					//(1/6) spdif dec 2x
			AUDIO_CLK_CONFIG = tmp;	
			
			
			tmp = AUDIO_PLL_CONFIG;
			pll_ctrl = (AUDIO_PLL_CONTROLs *) &tmp;				
			pll_ctrl->M = 48;
			pll_ctrl->N = 4;
			pll_ctrl->sleep = 0;
			AUDIO_PLL_CONFIG = tmp;
			

			audio_pll = SR_44100_SPDIF_2x;
			fn_pll = FN_Normal;
		}
		break;

	case SR_44100_SPDIF_4x:
		{
			/*11289600 x 8 x 4 / 6000000 = 60.2112, FRAC 0.2112 x 1048576 (0x100000) = 0x36113*/

			tmp = AUDIO_FNPLL_CONFIG;
			
			fnpll_ctrl = (AUDIO_FNPLL_CONTROLs *) &tmp;
			
			fnpll_ctrl->M = 60;
			fnpll_ctrl->N = 4;
			
			AUDIO_FNPLL_CONFIG = tmp;
			
			AUDIO_FNPLL_FRAC = FN_FRAC_44100_4X_NORMAL;						//44100
			
			
			tmp = AUDIO_CLK_CONFIG;
			clk_config = (AUDIO_CLK_CONFIGs *) &tmp;
			clk_config->audio_fnpll_n1 = 0;					//(1/2) spdif dec 1x
			AUDIO_CLK_CONFIG = tmp;	
			
			
			tmp = AUDIO_PLL_CONFIG;
			pll_ctrl = (AUDIO_PLL_CONTROLs *) &tmp;				
			pll_ctrl->M = 48;
			pll_ctrl->N = 8;
			pll_ctrl->sleep = 0;
			AUDIO_PLL_CONFIG = tmp;
						
			
			audio_pll = SR_44100_SPDIF_4x;
			fn_pll = FN_Normal;
		}
		break;

	case SR_48000_SPDIF_1x:
		{
			/*12288000 x 8 x 6 / 6000000 = 98.304, FRAC 0.304 x 1048576 (0x100000) = 0x4dd2f*/

			tmp = AUDIO_FNPLL_CONFIG;
			
			fnpll_ctrl = (AUDIO_FNPLL_CONTROLs *) &tmp;
			
			fnpll_ctrl->M = 98;
			fnpll_ctrl->N = 4;
			
			AUDIO_FNPLL_CONFIG = tmp;
			
			AUDIO_FNPLL_FRAC = FN_FRAC_48000_NORMAL;						//44100
			
			
			tmp = AUDIO_CLK_CONFIG;
			clk_config = (AUDIO_CLK_CONFIGs *) &tmp;
			clk_config->audio_fnpll_n1 = 5;					//(1/12) spdif dec 1x
			//clk_config->audio_fnpll_n1 = 2;					//(1/6) spdif dec 2x
			AUDIO_CLK_CONFIG = tmp;	
			
			
			tmp = AUDIO_PLL_CONFIG;
			pll_ctrl = (AUDIO_PLL_CONTROLs *) &tmp;				
			pll_ctrl->M = 48;
			pll_ctrl->N = 2;
			pll_ctrl->sleep = 0;
			AUDIO_PLL_CONFIG = tmp;
						
			audio_pll = SR_48000_SPDIF_1x;
			fn_pll = FN_Normal;
#ifdef BT_HEADPHONE
			//d2as
			DBG_Printf("size%d\n",optek_dsrc_alloc( 12, 512, OUT_SAMPLE_MASK, 2,PROCESSING_DATA_16b));

			hp_d2as_obj = optek_dsrc_open(hp_d2as_process_buffer, 12, 512, P192_M12_coeffs, 0,SPDIF_48000_BASE_STEP,SPDIF_48000_BASE_INTER_D,OUT_SAMPLE_MASK,2,PROCESSING_DATA_16b);				/*Nyquistx 160*/

			DBG_Assert (hp_d2as_obj != NULL);
#endif

		}
		break;

	case SR_48000_SPDIF_2x:
		{
			/*12288000 x 8 x 6 / 6000000 = 98.304, FRAC 0.304 x 1048576 (0x100000) = 0x4dd2f*/
			tmp = AUDIO_FNPLL_CONFIG;
			
			fnpll_ctrl = (AUDIO_FNPLL_CONTROLs *) &tmp;
			
			fnpll_ctrl->M = 98;
			fnpll_ctrl->N = 4;
			
			AUDIO_FNPLL_CONFIG = tmp;
			
			AUDIO_FNPLL_FRAC = FN_FRAC_48000_NORMAL;						//44100
			
			
			tmp = AUDIO_CLK_CONFIG;
			clk_config = (AUDIO_CLK_CONFIGs *) &tmp;
			//clk_config->audio_fnpll_n1 = 5;					//(1/12) spdif dec 1x
			clk_config->audio_fnpll_n1 = 2;					//(1/6) spdif dec 2x
			AUDIO_CLK_CONFIG = tmp;	
			
			
			tmp = AUDIO_PLL_CONFIG;
			pll_ctrl = (AUDIO_PLL_CONTROLs *) &tmp;				
			pll_ctrl->M = 48;
			pll_ctrl->N = 4;
			pll_ctrl->sleep = 0;
			AUDIO_PLL_CONFIG = tmp;
			
			audio_pll = SR_48000_SPDIF_2x;
			fn_pll = FN_Normal;
		}
		break;

	case SR_48000_SPDIF_4x:
		{
			/*12288000 x 8 x 4 / 6000000 = 65.536, FRAC 0.536 x 1048576 (0x100000) = 0x89374*/
			tmp = AUDIO_FNPLL_CONFIG;
			
			fnpll_ctrl = (AUDIO_FNPLL_CONTROLs *) &tmp;
			
			fnpll_ctrl->M = 65;
			fnpll_ctrl->N = 4;
			
			AUDIO_FNPLL_CONFIG = tmp;
			
			AUDIO_FNPLL_FRAC = FN_FRAC_48000_4X_NORMAL;						//44100
			
			
			tmp = AUDIO_CLK_CONFIG;
			clk_config = (AUDIO_CLK_CONFIGs *) &tmp;
			clk_config->audio_fnpll_n1 = 0;					//(1/2) spdif dec 1x
			AUDIO_CLK_CONFIG = tmp;	
			
			
			tmp = AUDIO_PLL_CONFIG;
			pll_ctrl = (AUDIO_PLL_CONTROLs *) &tmp;				
			pll_ctrl->M = 48;
			pll_ctrl->N = 8;
			pll_ctrl->sleep = 0;
			AUDIO_PLL_CONFIG = tmp;
			
	
			audio_pll = SR_48000_SPDIF_4x;
			fn_pll = FN_Normal;
		}
		break;

	case SR_32000_SPDIF_1x:
		{
			/*8192000 x 8 x 8 / 6000000 = 87.381333, FRAC 0.381333 x 1048576 (0x100000) = 399857 (0x619f1)*/

			tmp = AUDIO_FNPLL_CONFIG;
			
			fnpll_ctrl = (AUDIO_FNPLL_CONTROLs *) &tmp;
			
			fnpll_ctrl->M = 87;
			fnpll_ctrl->N = 4;
			
			AUDIO_FNPLL_CONFIG = tmp;
			
			AUDIO_FNPLL_FRAC = FN_FRAC_32000_NORMAL;        //44100
			
			
			tmp = AUDIO_CLK_CONFIG;
			clk_config = (AUDIO_CLK_CONFIGs *) &tmp;
			clk_config->audio_fnpll_n1 = 7;					//(1/16) spdif dec 1x
			AUDIO_CLK_CONFIG = tmp;	
			
			
			tmp = AUDIO_PLL_CONFIG;
			pll_ctrl = (AUDIO_PLL_CONTROLs *) &tmp;				
			pll_ctrl->M = 48;
			pll_ctrl->N = 2;
			pll_ctrl->sleep = 0;
			AUDIO_PLL_CONFIG = tmp;
			

			audio_pll = SR_32000_SPDIF_1x;
			fn_pll = FN_Normal;

#ifdef BT_HEADPHONE
			//d2as
			DBG_Printf("size%d\n",optek_dsrc_alloc( 12, 512, OUT_SAMPLE_MASK, 2,PROCESSING_DATA_16b));

			hp_d2as_obj = optek_dsrc_open(hp_d2as_process_buffer, 12, 512, P192_M12_coeffs, 0,SPDIF_32000_BASE_STEP,SPDIF_32000_BASE_INTER_D,OUT_SAMPLE_MASK,2,PROCESSING_DATA_16b);				/*Nyquistx 160*/

			DBG_Assert (hp_d2as_obj != NULL);
#endif
		}
		break;

	case SR_32000_SPDIF_2x:
		{
			/*8192000 x 8 x 8 / 6000000 = 87.381333, FRAC 0.381333 x 1048576 (0x100000) = 399857 (0x619f1)*/
			
			tmp = AUDIO_FNPLL_CONFIG;
			
			fnpll_ctrl = (AUDIO_FNPLL_CONTROLs *) &tmp;
			
			fnpll_ctrl->M = 87;
			fnpll_ctrl->N = 4;
			
			AUDIO_FNPLL_CONFIG = tmp;
			
			AUDIO_FNPLL_FRAC = FN_FRAC_32000_NORMAL;						//44100
			
			
			tmp = AUDIO_CLK_CONFIG;
			clk_config = (AUDIO_CLK_CONFIGs *) &tmp;
			clk_config->audio_fnpll_n1 = 3;					//(1/8) spdif dec 1x
			AUDIO_CLK_CONFIG = tmp;	
			
			
			tmp = AUDIO_PLL_CONFIG;
			pll_ctrl = (AUDIO_PLL_CONTROLs *) &tmp;				
			pll_ctrl->M = 48;
			pll_ctrl->N = 4;
			pll_ctrl->sleep = 0;
			AUDIO_PLL_CONFIG = tmp;
			

			audio_pll = SR_32000_SPDIF_2x;
			fn_pll = FN_Normal;
		}
		break;

	case SR_32000_SPDIF_4x:
		DBG_Printf ("SR_32000_SPDIF_4x\n\r");
		//256FS = 256*128kHz = 16.384*2mHz = 32.768mHz
		{
			/*8192000 x 8 x 8 / 6000000 = 87.381333, FRAC 0.381333 x 1048576 (0x100000) = 399857 (0x619f1)*/
			
			tmp = AUDIO_FNPLL_CONFIG;
			
			fnpll_ctrl = (AUDIO_FNPLL_CONTROLs *) &tmp;
			
			fnpll_ctrl->M = 87;
			fnpll_ctrl->N = 4;
			
			AUDIO_FNPLL_CONFIG = tmp;
			
			AUDIO_FNPLL_FRAC = FN_FRAC_32000_NORMAL;
			
			
			tmp = AUDIO_CLK_CONFIG;
			clk_config = (AUDIO_CLK_CONFIGs *) &tmp;
			clk_config->audio_fnpll_n1 = 1;					//(1/4) spdif dec 1x
			AUDIO_CLK_CONFIG = tmp;	
			
			
			tmp = AUDIO_PLL_CONFIG;
			pll_ctrl = (AUDIO_PLL_CONTROLs *) &tmp;				
			pll_ctrl->M = 48;
			pll_ctrl->N = 8;
			pll_ctrl->sleep = 0;
			AUDIO_PLL_CONFIG = tmp;
			
			
			audio_pll = SR_32000_SPDIF_4x;
			fn_pll = FN_Normal;
		}
		break;

	case SR_24000_SPDIF_1x:
		DBG_Printf ("SR_24000_SPDIF_1x\n\r");
		//6.144mHz:(12.288/2),256FS(256*24kHz)
		{
#if 1
			/*12288000 x 8 x 6 / 6000000 = 98.304, FRAC 0.304 x 1048576 (0x100000) = 0x4dd2f*/
			tmp = AUDIO_FNPLL_CONFIG;
			
			fnpll_ctrl = (AUDIO_FNPLL_CONTROLs *) &tmp;
			
			fnpll_ctrl->M = 98;
			fnpll_ctrl->N = 4;
			
			AUDIO_FNPLL_CONFIG = tmp;
			
			AUDIO_FNPLL_FRAC = FN_FRAC_48000_NORMAL;
#endif

#if 1
			tmp = AUDIO_CLK_CONFIG;
			DBG_Printf("Audio Clk Config3: 0x%x\n\r", tmp);

			clk_config = (AUDIO_CLK_CONFIGs *) &tmp;
			clk_config->audio_fnpll_n1 = (24/2 - 1);            //(1/24) spdif dec 1x
			//clk_config->audio_fnpll_n1 = 2;                     //(1/6) spdif dec 2x
			AUDIO_CLK_CONFIG = tmp;	
			DBG_Printf("Audio Clk Config4: 0x%x\n\r", tmp);
			
			
			tmp = AUDIO_PLL_CONFIG;

			pll_ctrl = (AUDIO_PLL_CONTROLs *) &tmp;
			DBG_Printf("Audio Pll Con3: 0x%x\n\r", tmp);

#if 0
			//18.432(384FS=48*2*2*2)
			pll_ctrl->M = 48;
			pll_ctrl->N = 2;
#else
			//12.288(256FS=32*2*2*2)
			//pll_ctrl->M = 32;
			#ifdef __USE_SRC_FUNCION__
			pll_ctrl->M = 96;
			#else
			pll_ctrl->M = 32*2;
			#endif
			pll_ctrl->N = 2;
#endif

			pll_ctrl->sleep = 0;
			AUDIO_PLL_CONFIG = tmp;
			DBG_Printf("Audio Pll Con4: 0x%x\n\r", tmp);
#endif

			audio_pll = SR_24000_SPDIF_1x;
			fn_pll = FN_Normal;
		}
		break;

	case SR_49000_SPDIF:
		{
			/*12,544,000 x 8 x 6 / 6000000 = 100.352, FRAC 0.352 x 1048576 (0x100000) =369099(0x5a1cb)*/
			tmp = AUDIO_FNPLL_CONFIG;
			
			fnpll_ctrl = (AUDIO_FNPLL_CONTROLs *) &tmp;
			
			fnpll_ctrl->M = 100;
			fnpll_ctrl->N = 4;
			
			AUDIO_FNPLL_CONFIG = tmp;
			
			AUDIO_FNPLL_FRAC = 0x5a1cb;				
			
			
			tmp = AUDIO_CLK_CONFIG;
			clk_config = (AUDIO_CLK_CONFIGs *) &tmp;
			//clk_config->audio_fnpll_n1 = 5;					//(1/12) spdif dec 1x
			clk_config->audio_fnpll_n1 = 2;					//(1/6) spdif dec 2x
			AUDIO_CLK_CONFIG = tmp;	
			
			
			tmp = AUDIO_PLL_CONFIG;
			pll_ctrl = (AUDIO_PLL_CONTROLs *) &tmp;				
			pll_ctrl->M = 48;
			pll_ctrl->N = 4;
			pll_ctrl->sleep = 0;
			AUDIO_PLL_CONFIG = tmp;
			
			audio_pll = SR_49000_SPDIF;
			fn_pll = FN_Normal;
		}
		break;
//	case SR_98000_SPDIF:
//		DBG_Assert(FALSE);
//		break;

	default:
	{
		/*11289600 x 8 x 6 / 6000000 = 90.3168, FRAC 0.3168 x 1048576 (0x100000) = 0x5119D*/

		tmp = AUDIO_FNPLL_CONFIG;
		
		fnpll_ctrl = (AUDIO_FNPLL_CONTROLs *) &tmp;
		
		fnpll_ctrl->M = 90;
		fnpll_ctrl->N = 4;
		
		AUDIO_FNPLL_CONFIG = tmp;
					
		AUDIO_FNPLL_FRAC = FN_FRAC_44100_NORMAL;						//44100


		tmp = AUDIO_CLK_CONFIG;
		clk_config = (AUDIO_CLK_CONFIGs *) &tmp;
		clk_config->audio_fnpll_n1 = 5;					//(1/12) spdif dec 1x
		//clk_config->audio_fnpll_n1 = 2;					//(1/6) spdif dec 2x
		AUDIO_CLK_CONFIG = tmp;	


		tmp = AUDIO_PLL_CONFIG;
		pll_ctrl = (AUDIO_PLL_CONTROLs *) &tmp;				
		pll_ctrl->M = 48;
		pll_ctrl->N = 2;
		pll_ctrl->sleep = 0;
		AUDIO_PLL_CONFIG = tmp;


		audio_pll = SR_44100_SPDIF_1x;
		fn_pll = FN_Normal;			

#ifdef BT_HEADPHONE
		//d2as
		DBG_Printf("size%d\n",optek_dsrc_alloc( 12, 512, OUT_SAMPLE_MASK, 2,PROCESSING_DATA_16b));

		hp_d2as_obj = optek_dsrc_open(hp_d2as_process_buffer, 12, 512, P160_M12_coeffs, 0,SPDIF_44100_BASE_STEP,SPDIF_44100_BASE_INTER_D,OUT_SAMPLE_MASK,2,PROCESSING_DATA_16b);				/*Nyquistx 160*/

		DBG_Assert (hp_d2as_obj != NULL);
#endif

	}	
		DBG_Assert(FALSE);
		break;
	}

	//for Mono channel output
	DA_PP_MUTE_EN = FALSE;

	//DA_PP_CLASSD_EN = 0x01;  //classd enable

	pre_audio_freq = freq;	
#endif
}

void audio_pll_set_fnpll_clk_in (void)
{
#if 0
	volatile U32 tmp;
	AUDIO_FNPLL_CONTROLs *fnpll_ctrl;
	AUDIO_PLL_CONTROLs *pll_ctrl;
	AUDIO_CLK_CONFIGs *clk_config;


	tmp = AUDIO_CLK_CONFIG;
	clk_config = (AUDIO_CLK_CONFIGs *) &tmp;

	clk_config->pll_xin_s = 3;					//select fn pll out
	//clk_config->pll_xin_s = 4;					//spdif bit 


#if (defined AUDIO_OUT_FROM_I2S1 || defined AUDIO_I2S2_OUT_ORIGINAL_WO_PWM)	
	clk_config->audio_pll_n1 = 0xB;					//11.2896*1, 1/24
#else

#ifdef PWM_8_BITS
	clk_config->audio_pll_n1 = 0x02;				//11.2896*4, 1/6
#endif	//PWM_8_BITS

#ifdef PWM_7_BITS
#ifdef PWM_PD
	//for monno channel
	clk_config->audio_pll_n1 = 0x02;				//11.2896*4, 1/6
#else
	//clk_config->audio_pll_n1 = 3;					//11.2896*2 for pll_ctrl->M = 32
	clk_config->audio_pll_n1 = 0x5;					//11.2896*2,1/12
	//clk_config->audio_pll_n1 = 0x2;					//11.2896*2,1/12
#endif //PWM_PD
#endif //PWM_7_BITS

#ifdef PWM_6_BITS
	//clk_config->audio_pll_n1 = 7;					//11.2896*1 for pll_ctrl->M = 32
	clk_config->audio_pll_n1 = 0xB;					//11.2896*1,1/24
#endif //PWM_6_BITS

#endif //AUDIO_OUT_FROM_I2S1


#ifdef MCLK_384
	//384x
	clk_config->audio_pll_n2 = 7;						//384x   (1/16)	16.9344
#else
	//256x
	clk_config->audio_pll_n2 = 0xB;						//256x   (1/24) 11.2896
#endif


	AUDIO_CLK_CONFIG = tmp;

	tmp = AUDIO_PLL_CONFIG;

	pll_ctrl = (AUDIO_PLL_CONTROLs *) &tmp;
	pll_ctrl->M = 48;				//be able to gen sample rate x 384	
	AUDIO_PLL_CONFIG = tmp;
#endif
}


void audio_pll_set_spdif_bitclk_in (U8 spdif_inx)
{
#if 0
	volatile U32 tmp;
	AUDIO_FNPLL_CONTROLs *fnpll_ctrl;
	AUDIO_PLL_CONTROLs *pll_ctrl;
	AUDIO_CLK_CONFIGs *clk_config;


	tmp = AUDIO_CLK_CONFIG;
	clk_config = (AUDIO_CLK_CONFIGs *) &tmp;

	//clk_config->pll_xin_s = 3;					//select fn pll out
	clk_config->pll_xin_s = 4;					//spdif bit 


#ifdef PWM_PD
	//clk_config->audio_pll_n1 = 0xB;					//11.2896*1, 1/24
	
	//clk_config->audio_pll_n1 = 0x5;					//11.2896*1, 1/12
	
#ifdef PWM_8_BITS
	clk_config->audio_pll_n1 = 0x0;		//need 11.2896*8,no support	//11.2896*4, 1/2
#endif
#ifdef PWM_7_BITS
	clk_config->audio_pll_n1 = 0x0;					//11.2896*2, 1/4
#endif
#ifdef PWM_6_BITS
	clk_config->audio_pll_n2 = 0x1;					//11.2896*1, 1/8
#endif
	AUDIO_CLK_CONFIG = tmp;

	tmp = AUDIO_PLL_CONFIG;

	pll_ctrl = (AUDIO_PLL_CONTROLs *) &tmp;
	if (spdif_inx == 4) {
		pll_ctrl->M = 32;			
	}
	else if (spdif_inx == 2) {
		pll_ctrl->M = 64;				
	}
	else {
		pll_ctrl->M = 128;			//((11.2896/2))/2*128 = 361.2672Mhz
	}

	pll_ctrl->N = 2;

	AUDIO_PLL_CONFIG = tmp;

#else

#ifdef PWM_7_BITS
	clk_config->audio_pll_n1 = 0x2;					//11.2896*2, 1/6
#endif

#ifdef PWM_6_BITS
	clk_config->audio_pll_n2 = 0x5;					//11.2896*1, 1/12
#endif

	//PWM_8_BITS?????

	AUDIO_CLK_CONFIG = tmp;

 
	tmp = AUDIO_PLL_CONFIG;

	pll_ctrl = (AUDIO_PLL_CONTROLs *) &tmp;

	//pll_ctrl->sleep = 0;
	//pll_ctrl->od = 1;
	if (spdif_inx == 4) {
		pll_ctrl->M = 48;			
		//pll_ctrl->M = 96*2;	
	}
	else if (spdif_inx == 2) {
		pll_ctrl->M = 96;				
		//pll_ctrl->M = 96*2;	
	}
	else {
		pll_ctrl->M = 96*2;	
	}

	pll_ctrl->N = 2;

	AUDIO_PLL_CONFIG = tmp;
#endif //PWM_PD

#endif
}


//void audio_pll_lock (i32 err) __INTERNAL_RAM_TEXT;


void otk_psm_ui_send_frac (u32 frac);

void audio_pll_set_lock_interval (u16 val)
{
	pll_lock_interval = val;
}

void audio_pll_lock (i32 err)
{
#if 0	
	U32 val, err_abs;
	U32 fn_franc;

	pll_lock_cn++;	
	
	err_abs = abs(err);

	//DBG_Assert (FALSE);

	/*if (err_abs > 2) 
	{
		DBG_Printf ("CLK err %d %d\n\r",err_abs,pll_lock_cn);
	}*/

	err_abs >>= 1;

	if (err_abs > 4)
	{
		err_abs = 4;
	}

	fn_franc = (err_abs * FNPLL_10PPM);


	/*if (fn_franc == 0)
	{
		if (pll_lock_cn == PLL_LOCK_TIME)
		{
			DBG_Printf ("SPDIF clk locked\n\r");
		}
		goto pll_lock_exit;
	}*/


	val = AUDIO_FNPLL_FRAC;

	if ((err > 0)&&(fnpll_adjust_frac >= 0))
	{
		pll_lock_cn_p++;
		pll_lock_cn_n = 0;

		if (pll_lock_cn_p >= pll_lock_interval)
		{
			pll_lock_cn = 0;	
			pll_lock_cn_p = 0;
			DBG_Printf ("Diff +%d in %x\n\r",err_abs,err);

			//pre_audio_freq = -1;
			fnpll_adjust_frac += err_abs;				//fast

			if ( (val + fn_franc) > 0xFFFFF)
			{
				val = 0xFFFFF;
			}
			else
			{
				val += fn_franc;
			}

#ifdef FNPLL_SUBW					
			otk_psm_ui_send_frac(val);
#endif

			AUDIO_FNPLL_FRAC = val;
		}
	}
	else if ((err < 0)&&(fnpll_adjust_frac <= 0))
	{
		pll_lock_cn_p = 0;
		pll_lock_cn_n++;
		if (pll_lock_cn_n >= pll_lock_interval)
		{
			pll_lock_cn = 0;	
			pll_lock_cn_n = 0;
			DBG_Printf ("Diff -%d in %x\n\r",err_abs,err);			
			//pre_audio_freq = -1;
			fnpll_adjust_frac -= err_abs;		//slow

			if ( val >= fn_franc )
			{
				val -= fn_franc;
			}
			else
			{
				val = 0;
			}

#ifdef FNPLL_SUBW					
			otk_psm_ui_send_frac(val);
#endif

			AUDIO_FNPLL_FRAC = val;
		}
	} 
	else
	{
		//pll_lock_cn = PLL_LOCK_TIME;
		//pll_lock_cn++;	
		pll_lock_cn_p = 0;
		pll_lock_cn_n = 0;
		if (pll_lock_cn >= (pll_lock_interval<<2))
		{
			pll_lock_cn = 0;
			DBG_Printf ("PLL clk locked\n\r");
			if (fnpll_adjust_frac != 0)
			{
				if (fnpll_adjust_frac > 0)
				{
					DBG_Printf ("fNPLL pre-adjust +%d\n\r",fnpll_adjust_frac);
#if 1
					fnpll_adjust_frac++;
					fnpll_adjust_frac >>= 1;

					DBG_Printf ("fNPLL adjust +%d\n\r",fnpll_adjust_frac);

					fn_franc = (fnpll_adjust_frac * FNPLL_10PPM);
					if ( val >= fn_franc )
					{
						val -= fn_franc;
					}
					else
					{
						val = 0;
					}

#ifdef FNPLL_SUBW					
					otk_psm_ui_send_frac(val);
#endif

					AUDIO_FNPLL_FRAC = val;
#endif
				} 
				else
				{
					//fnpll_adjust_frac < 0
					fnpll_adjust_frac = abs(fnpll_adjust_frac);
					DBG_Printf ("fNPLL pre-adjust -%d\n\r",fnpll_adjust_frac);		
#if 1				
					fnpll_adjust_frac++;
					fnpll_adjust_frac >>= 1;

					DBG_Printf ("fNPLL adjust -%d\n\r",fnpll_adjust_frac);

					fn_franc = (fnpll_adjust_frac * FNPLL_10PPM);
					if ( (val + fn_franc) > 0xFFFFF)
					{
						val = 0xFFFFF;
					}
					else
					{
						val += fn_franc;
					}
#ifdef FNPLL_SUBW					
					otk_psm_ui_send_frac(val);
#endif
					AUDIO_FNPLL_FRAC = val;		
#endif
				}

				fnpll_adjust_frac = 0;
			}
		}
    }

	/*
	pll_lock_exit:
	if (pll_lock_cn >= pll_lock_interval)
	{
		pll_lock_cn = 0;
	}
	*/

	return;	
#endif	
}

void audio_pll_set_frac (U32 frac)
{
#if 0	
	AUDIO_FNPLL_FRAC = frac;						//44100
	pre_audio_freq = -1;
#endif	
}