#include "os_config.h"

#include "c_def.h"
#include "debug.h"
#include "oem.h"

#include "regmap.h"

#include "hw_da_pp.h"
#include "hw_pll.h"
#include "hw_uart.h"
#include "hw_da_pp.h"
#include "hw_dma.h"
#include "flash_boot.h"
#include "app_main.h"


extern U32 SystemClock;

void hw_pll_bypass (void)
{
	volatile U32 tmp;	
#if 1 	
	MISC_CFG_CONTROLs *CFG_config;
	tmp = REG_MISC_CFG;
	CFG_config = (MISC_CFG_CONTROLs *) &tmp;
	
	//not sel 24M
	CFG_config->regConfig_cpuClkSel = 0;//not 24M
	REG_MISC_CFG = tmp;	
	asm("nop");
	asm("nop");
	asm("nop");
	asm("nop");
	asm("nop");
	asm("nop");
	asm("nop");
	asm("nop");
	asm("nop");
	asm("nop");
	asm("nop");
	asm("nop");
	asm("nop");
	asm("nop");
	asm("nop");
	asm("nop");
	
//	delayms(2);
#endif
}


/*
 * hw_pll.c
 *
 *  Created on: 2019-7-11
 *      Author: Windowns
 */
 
void hw_pll_set (u8 enable, u32 freq)
{
	MISC_PLL_CONTROLs *pll_config;
	volatile U32 tmp;	
	volatile U32 val;
	volatile U32 val1;

	hw_pll_bypass();

	tmp = 0;
	pll_config = (MISC_PLL_CONTROLs *) &tmp;
	
	pll_config->pll_PD = 1;
	pll_config->pll_REFDIV = 1;

	if (enable == 0)
	{
		REG_MISC_PLL = tmp;		
		return;	
	}
	
	if (freq == CPU_128MHz)
	{
		pll_config->pll_FBDIV = 32;
	}	
	else if (freq == CPU_120MHz)
	{
		pll_config->pll_FBDIV = 30;
	}	
	else
	{
		pll_config->pll_FBDIV = 24;
	}
		
	
	switch (freq)
	{
	case CPU_24MHz:
		/*24x24/24=24*/
		pll_config->pll_POSTDIV1 = 6;	
		pll_config->pll_POSTDIV2 = 4;	
		//pll_config->pll_Dynamic_DIV = 0;
		break;
	case CPU_32MHz:
		/*24x24/18=32*/
		pll_config->pll_POSTDIV1 = 6;	
		pll_config->pll_POSTDIV2 = 3;	
		//pll_config->pll_Dynamic_DIV = 0;
		break;
	case CPU_48MHz:
		/*24x24/12=48*/
		pll_config->pll_POSTDIV1 = 6;	
		pll_config->pll_POSTDIV2 = 2;	
		//pll_config->pll_Dynamic_DIV = 0;
		break;
	case CPU_64MHz:
		/*24*24/9=64*/
		pll_config->pll_POSTDIV1 = 3;	
		pll_config->pll_POSTDIV2 = 3;	
		//pll_config->pll_Dynamic_DIV = 0;
		break;
	case CPU_72MHz:
		/*24*24/8=64*/
		pll_config->pll_POSTDIV1 = 4;	
		pll_config->pll_POSTDIV2 = 2;	
		//pll_config->pll_Dynamic_DIV = 0;
		break;		
	case CPU_96MHz:
		/*24*24/6=96*/
		pll_config->pll_POSTDIV1 = 3;	
		pll_config->pll_POSTDIV2 = 2;	
		//pll_config->pll_Dynamic_DIV = 0;
		break;
	case CPU_120MHz:
		/*24*30/6=120*/
		pll_config->pll_POSTDIV1 = 3;	
		pll_config->pll_POSTDIV2 = 2;	
		//pll_config->pll_Dynamic_DIV = 0;
		break;
	case CPU_128MHz:
		/*24*32/6=128*/
		pll_config->pll_POSTDIV1 = 3;	
		pll_config->pll_POSTDIV2 = 2;	
		//pll_config->pll_Dynamic_DIV = 0;
		break;					
	default:
		DBG_Assert (FALSE);
		DBG_Printf("soc freq isn't the range definfed\n\r");
		return;
		//break;
	}

	SystemClock = freq;

	pll_config->pll_Dynamic_DIV = 0;
	pll_config->pll_DACDSMPD = 1;
	
	REG_MISC_PLL = tmp;	
	asm("nop");
	asm("nop");


	pll_config = (MISC_PLL_CONTROLs *) &tmp;
	pll_config->pll_PD = 0;
	REG_MISC_PLL = tmp;	
	asm("nop");
	asm("nop");
	
	while (1)
	{
		val = REG_MISC_PLL;
		pll_config = (MISC_PLL_CONTROLs *) &val;
		if (pll_config->pll_Lock)
		{
			delayus(10);
			break;
		}
		delayus(10);
	}


#if 1 	
	MISC_CFG_CONTROLs *CFG_config;
	tmp = REG_MISC_CFG;
	CFG_config = (MISC_CFG_CONTROLs *) &tmp;
	//sel pll_gated
	CFG_config->regConfig_pllRtcSel = 1;//pll or 32k
 #if 0
    /*set crystal_24M current triming*/
    CFG_config->clk24M_I_trim =7;    // 3=720uA defualt 3=800uA, 4=880uA,5=960uA,6=1040uA,7=1110uA,
	/*set crystal capacitance triming*/
	//CFG_config->clk24M_C_trim =0;   //0=5pF, defual is 9pF,in range 5pF to 12pF at 1pF/step.
#endif
	REG_MISC_CFG = tmp;	
	asm("nop");
	asm("nop");
	asm("nop");
	asm("nop");
	asm("nop");
	asm("nop");
	asm("nop");
	asm("nop");
	delayms(2);	

	
	delayms(200);	
	
	//not sel 24M
	CFG_config->regConfig_cpuClkSel = 1;//not 24M
	REG_MISC_CFG = tmp;	
	asm("nop");
	asm("nop");
	asm("nop");
	asm("nop");
	asm("nop");
	asm("nop");
	asm("nop");
	asm("nop");
	asm("nop");
	asm("nop");
	asm("nop");
	asm("nop");
	asm("nop");
	asm("nop");
	asm("nop");
	asm("nop");
	
	delayms(2);
#endif

	//app_gpio_MUXfunction_select(GPIO0_00_INDEX, MUX_SEL_FUNCTION1);
	//app_gpio_MUXfunction_select(GPIO2_06_INDEX, MUX_SEL_FUNCTION2);
	//CFG_config->mclk1_in_out = 1;
	//CFG_config->mclk2_in_out = 1;	
	//REG_MISC_CFG = tmp;
	
	MISC_BTDM_CONTROLs *btdm_config;
	val = REG_MISC_BTDM;
	btdm_config = (MISC_BTDM_CONTROLs *) &val;
	MISC_BTDM_2_CONTROLs *btdm_2_config;
	val1 = REG_MISC_BTDM_2;
	btdm_2_config = (MISC_BTDM_2_CONTROLs *) &val1;	

#ifdef BT_PA_ENABLE
	app_gpio_MUXfunction_select(GPIO0_10_INDEX, MUX_SEL_FUNCTION1);
	app_gpio_MUXfunction_select(GPIO0_11_INDEX, MUX_SEL_FUNCTION1);
	btdm_2_config->bt_PA_en = 3;
#endif

	btdm_2_config->bt_if_rssi_sel = 1;
	switch (freq)
	{
	case CPU_24MHz:
		btdm_2_config->bt_clksel = 12;
		btdm_config->BT_hclkratio = 1;                  //bt_clk = hclk
		break;
	case CPU_32MHz:
		btdm_2_config->bt_clksel = 16;
		btdm_config->BT_hclkratio = 1;                  //bt_clk = hclk		
		break;
	case CPU_48MHz:
		btdm_2_config->bt_clksel = 12;
		btdm_config->BT_hclkratio = 2;                  //bt_clk = hclk/2
		break;
	case CPU_64MHz:
		btdm_2_config->bt_clksel = 16;
		btdm_config->BT_hclkratio = 2;                  //bt_clk = hclk/2
		break;
	case CPU_72MHz:
		btdm_2_config->bt_clksel = 12;
		btdm_config->BT_hclkratio = 3;                  //bt_clk = hclk/3
		break;
	case CPU_96MHz:
		btdm_2_config->bt_clksel = 16;
		btdm_config->BT_hclkratio = 3;                  //bt_clk = hclk/3
		break;
	case CPU_120MHz:
		btdm_2_config->bt_clksel = 12;
		btdm_config->BT_hclkratio = 4;                  //bt_clk = hclk/4
		break;
	case CPU_128MHz:
		btdm_2_config->bt_clksel = 16;
		btdm_config->BT_hclkratio = 4;                  //bt_clk = hclk/4
		break;					
	default:
		DBG_Assert (FALSE);
		break;
	}

#ifdef BOOT_FROM_FLASH
	REG_MISC_BTDM_2 = val1;
#endif

	btdm_config->btrf_dd_adda_sync_clk_en = 1;
	btdm_config->btrf_ad_pwr_rstn_12d = 0;
	
	#if 1//def AUDIO_PWM_OUTPUT
	btdm_config->bt_dbg_sel_1 = 0;			
	btdm_config->bt_dbg_sel_2 = 0;
	btdm_config->bt_dbg_en = 0;
	#else
	btdm_config->bt_dbg_sel_1 = 4;			//check 1P clk(32Mhz) for bt connect problem
	btdm_config->bt_dbg_sel_2 = 4;
	btdm_config->bt_dbg_en = 1;
	#endif

	//btdm_config->bt_tx_rx_mux_en = 1;
	REG_MISC_BTDM = val;

	asm("nop");
	asm("nop");
	asm("nop");
	asm("nop");
	asm("nop");
	asm("nop");

	btdm_config->btrf_ad_pwr_rstn_12d = 1;
	REG_MISC_BTDM = val;
}

void hw_audio_pll_set (u8 enable, u8 CLKSSCG_en, u8 sf_base, u8 pwm_out_en, u8 pwm_mode, u8 spdif_dec_en, u8 spdif_dec_sf, u8 adda_en, u8 mclk_en)
{
	volatile U32 tmp;
	volatile U32 val;

	MISC_PLLFRAC1_CONTROLs *pllfrac1_config;
	MISC_PLLFRAC2_CONTROLs *pllfrac2_config;
	MISC_PLLFRAC3_CONTROLs *pllfrac3_config;
	MISC_SSMOD_CONTROLs *ssmod_config;

	#if 0	
	tmp = REG_MISC_AUDIO_PLL;
	#else
	tmp = 0;
	pllfrac1_config = (MISC_PLLFRAC1_CONTROLs *) &tmp;
	#endif
	pllfrac1_config->pllFrac_PD = 1;
	pllfrac1_config->pllFrac_REFDIV = 1;

	if (enable == 0)
	{
		REG_MISC_AUDIO_PLL = tmp;
		return;
	}

/***********************************************************************************
	12.288 12.288*8*6/24 = 24.576
	FBDIV	 24
	FRAC	 0.576 * 0x1000000 (16777216) = 9,663,676.42 = 9,663,676 

	11.2896 11.2896*8*6/24 = 22.5792
	FBDIV   22
	FRAC    0.5792 * 0x1000000 (16777216) = 9,717,363.51 = 9,717,364 

	8.192 8.192*8*6/24 = 16.384	(8.192 x 64 = 393.216MHz, PLL min VCO > 400MHz ?)
	FBDIV   16
	FRAC    0.384 * 0x1000000 (16777216) = 6442450.944 = 6442451 

	(49k*256) 12.544*8*6/24 = 25.088
	FBDIV	 25
	FRAC	 0.088 * 0x1000000 (16777216) = 1476395.008 = 1476395

************************************************************************************/	


	if (sf_base == SF_BASE_48000)
	{
		pllfrac1_config->pllFrac_FBDIV = 24;		
	}
	else if (sf_base == SF_BASE_44100)
	{
		pllfrac1_config->pllFrac_FBDIV = 22;
	}
	else if (sf_base == SF_BASE_32000)
	{
		pllfrac1_config->pllFrac_FBDIV = 16;
	}
	else if (sf_base == SF_BASE_DET)
	{
		pllfrac1_config->pllFrac_FBDIV = 25;		
	}
	else
	{
		DBG_Assert (FALSE);
	}
		

	if (pwm_out_en)
	{
		if (pwm_mode == PWM_768_4096x)
		{
			pllfrac1_config->pllFrac_POSTDIV1 = 3;		//48/3=16x
			pllfrac1_config->pllFrac_POSTDIV2 = 1;
		}
		else if (pwm_mode == PWM_2304)
		{
			pllfrac1_config->pllFrac_POSTDIV1 = 2;		//48/2=24, PH0 /2->12x
			pllfrac1_config->pllFrac_POSTDIV2 = 1;
		}
		else if (pwm_mode == PWM_384 || pwm_mode == PWM_768_2048x)
		{
			pllfrac1_config->pllFrac_POSTDIV1 = 3;		//48/6=8x
			pllfrac1_config->pllFrac_POSTDIV2 = 2;
		}
		else
		{
			DBG_Assert (FALSE);
		}
	}
	else if (spdif_dec_en)
	{
		pllfrac1_config->pllFrac_POSTDIV1 = 3;		//48/6=8x
		pllfrac1_config->pllFrac_POSTDIV2 = 2;
	}
	else
	{
		pllfrac1_config->pllFrac_POSTDIV1 = 3;		//48/6=8x
		pllfrac1_config->pllFrac_POSTDIV2 = 2;
	}

	pllfrac1_config->pllFrac_CLKSSCG_en = CLKSSCG_en;

	if (mclk_en | adda_en | spdif_dec_en)
	{
		pllfrac1_config->pllFrac_2048x_256x_en = 1;	
	}
	else
	{
		pllfrac1_config->pllFrac_2048x_256x_en = 0;	
	}


	if (spdif_dec_en)
	{
		pllfrac1_config->pllFrac_2048x_spdif_dec_en = 1;
	}
	else
	{
		pllfrac1_config->pllFrac_2048x_spdif_dec_en = 0;
	}

	if (adda_en)
	{		
		pllfrac1_config->pllFrac_2048x_spdif_enc_en = 1;
	}
	else
	{
		pllfrac1_config->pllFrac_2048x_spdif_enc_en = 0;
	}

	if (mclk_en)
	{
		pllfrac1_config->pllFrac_256x_en = 1;
	}

	REG_MISC_AUDIO_PLL = tmp;	

	pllfrac2_config = (MISC_PLLFRAC2_CONTROLs *) &tmp;
		
	if (sf_base == SF_BASE_48000)
	{
		pllfrac2_config->pllfrac_FBFRAC = 9663676;			
	}
	else if (sf_base == SF_BASE_44100)
	{
		pllfrac2_config->pllfrac_FBFRAC = 9717364;
	}
	else if (sf_base == SF_BASE_32000)
	{
		pllfrac2_config->pllfrac_FBFRAC = 6442451;		}
	else if (sf_base == SF_BASE_DET)
	{
		pllfrac2_config->pllfrac_FBFRAC = 1476395;
	}
	else
	{
		DBG_Assert (FALSE);
	}
		
	REG_MISC_AUDIO_PLL_2 = tmp;	

	tmp = REG_MISC_AUDIO_PLL_3;
    
	pllfrac3_config = (MISC_PLLFRAC3_CONTROLs *) &tmp; 

	if (pwm_out_en)
	{
		if (pwm_mode == PWM_2304)
		{
			//only 1024x
			pllfrac3_config->pllFrac_256x_n = 2;
			pllfrac3_config->pllFrac_spdif_enc_n = 2;
		}
		else
		{
			pllfrac3_config->pllFrac_256x_n = 4;
			pllfrac3_config->pllFrac_spdif_enc_n = 4;
		}
	}
	else if (spdif_dec_en)
	{		
		pllfrac3_config->pllFrac_256x_n = 4;
		pllfrac3_config->pllFrac_spdif_enc_n = 4;
	}
	else
	{
		//Freuency/1
		pllfrac3_config->pllFrac_256x_n = 0;
		pllfrac3_config->pllFrac_spdif_enc_n = 0;
	}

	if (spdif_dec_en) 
	{
		if (pwm_out_en == 1 && pwm_mode == PWM_2304)
		{
			//only 1024x
			switch (spdif_dec_sf)
			{
			case SPDIF_SF_1x:
				pllfrac3_config->pllFrac_spdif_dec_n = 1;			
				break;
			case SPDIF_SF_2x:
				pllfrac3_config->pllFrac_spdif_dec_n = 0;
				break;	
			case SPDIF_SF_4x:
				DBG_Assert (FALSE);		//at this condition, only support 96k
				break;		
			case SPDIF_SF_hx:
				pllfrac3_config->pllFrac_spdif_dec_n = 2;				//only suport 96k
				break;		
			default:
				DBG_Assert (FALSE);
				break;
			}
		}
		else
		{
			switch (spdif_dec_sf)
			{
			case SPDIF_SF_1x:
				pllfrac3_config->pllFrac_spdif_dec_n = 2;				
				break;
			case SPDIF_SF_2x:
				pllfrac3_config->pllFrac_spdif_dec_n = 1;				
				break;	
			case SPDIF_SF_4x:
				pllfrac3_config->pllFrac_spdif_dec_n = 0;				
				break;		
			case SPDIF_SF_hx:
				pllfrac3_config->pllFrac_spdif_dec_n = 4;				
				break;		
			default:
				DBG_Assert (FALSE);
				break;
			}
		}
	}

	if (pwm_out_en)
	{

		if (pwm_mode == PWM_2304)
		{
			pllfrac3_config->pllFrac_2048x_SEL = 3;		//sel pllFrac_FOUTPH3, only 1024x
			pllfrac3_config->pllFrac_pwm_clk_SEL = 0;	//sel FOUTPH0
			//pllfrac3_config->pllFrac_pwm_clk_SEL = 1;	//sel FOUTPH0
		}
		else if (pwm_mode == PWM_768_4096x)
		{
			pllfrac3_config->pllFrac_2048x_SEL = 1;		//sel FOUTPOSTDIV
			pllfrac3_config->pllFrac_pwm_clk_SEL = 1;	//sel FOUTPOSTDIV
		}	
		else
		{
			pllfrac3_config->pllFrac_2048x_SEL = 0;		//sel FOUTPOSTDIV
			pllfrac3_config->pllFrac_pwm_clk_SEL = 1;	//sel FOUTPOSTDIV
		}	

		pllfrac3_config->pllFrac_pwm_clk_en = 1;

	}

	else if (spdif_dec_en)
	{		
		pllfrac3_config->pllFrac_2048x_SEL = 0;		//sel FOUTPOSTDIV
		pllfrac3_config->pllFrac_pwm_clk_en = 0;
	}
	else
	{	
		pllfrac3_config->pllFrac_2048x_SEL = 2;
		pllfrac3_config->pllFrac_pwm_clk_en = 0;
	}

	pllfrac3_config->pllFrac_256x_SEL = 1;
    pllfrac3_config->pllFrac_FREF_SEL = 0;              //24MHz in
		
	REG_MISC_AUDIO_PLL_3 = tmp;	    		

	
	tmp = 0;
	ssmod_config = (MISC_SSMOD_CONTROLs *) &tmp;

	//at current time, disable SSCG
	ssmod_config->ssmod_RESET = 0;
	if (CLKSSCG_en)
		ssmod_config->ssmod_DISABLE_SSCG = 0;	//disable SSCG
	else
		ssmod_config->ssmod_DISABLE_SSCG = 1;	//enable SSCG

	ssmod_config->ssmod_SEL_EXTWAVE = 0;
	ssmod_config->ssmod_DOWNSPREAD = 0;
	//ssmod_config->ssmod_RESETPTR = 0;
	ssmod_config->ssmod_DIVVAL = SS_DIVVAL;
	ssmod_config->ssmod_SPREAD = SS_SPREAD;

	REG_MISC_AUDIO_PLL_4 = tmp;	

	val = REG_MISC_AUDIO_PLL;
	pllfrac1_config = (MISC_PLLFRAC1_CONTROLs *) &val;
	pllfrac1_config->pllFrac_PD = 0;
	REG_MISC_AUDIO_PLL = val;	
	asm("nop");
	asm("nop");
	while (1)
	{
		val = REG_MISC_AUDIO_PLL;
		pllfrac1_config = (MISC_PLLFRAC1_CONTROLs *) &val;
	
		if (pllfrac1_config->pllFrac_Lock)
		{
			delayus(10);		
			
			break;
		}
		delayus(10);		
	}	

}

void hw_audio_pll_clk_fre_set (u8 sf_base, u8 spdif_dec_sf)
{
	volatile U32 tmp,tmp2;

	DBG_Printf("%s\n\r", __func__);
	//DBG_Printf("%s, %d %d\n\r", __func__, sf_base, spdif_dec_sf);

	MISC_PLLFRAC1_CONTROLs *pllfrac1_config;
	MISC_PLLFRAC2_CONTROLs *pllfrac2_config;
	MISC_PLLFRAC3_CONTROLs *pllfrac3_config;

/***********************************************************************************
	12.288 12.288*8*6/24 = 24.576
	FBDIV	 24
	FRAC	 0.576 * 0x1000000 (16777216) = 9,663,676.42 = 9,663,676 

	11.2896 11.2896*8*6/24 = 22.5792
	FBDIV   22
	FRAC    0.5792 * 0x1000000 (16777216) = 9,717,363.51 = 9,717,364 

	8.192 8.192*8*6/24 = 16.384	(8.192 x 64 = 393.216MHz, PLL min VCO > 400MHz ?)
	FBDIV   16
	FRAC    0.384 * 0x1000000 (16777216) = 6442450.944 = 6442451 

	(49k*256) 12.544*8*6/24 = 25.088
	FBDIV	 25
	FRAC	 0.088 * 0x1000000 (16777216) = 1476395.008 = 1476395

************************************************************************************/	


	tmp = REG_MISC_AUDIO_PLL;
	pllfrac1_config = (MISC_PLLFRAC1_CONTROLs *) &tmp;
	
	tmp2 = 0;
	pllfrac2_config = (MISC_PLLFRAC2_CONTROLs *) &tmp2;

	if (sf_base == SF_BASE_48000)
	{
		pllfrac1_config->pllFrac_FBDIV = 24;
		pllfrac2_config->pllfrac_FBFRAC = 9663676;	
	}
	else if (sf_base == SF_BASE_44100)
	{
		pllfrac1_config->pllFrac_FBDIV = 22;
		pllfrac2_config->pllfrac_FBFRAC = 9717364;
	}
	else if (sf_base == SF_BASE_32000)
	{
		pllfrac1_config->pllFrac_FBDIV = 16;
		pllfrac2_config->pllfrac_FBFRAC = 6442451;
	}
	else if (sf_base == SF_BASE_DET)
	{
		pllfrac1_config->pllFrac_FBDIV = 25;
		pllfrac2_config->pllfrac_FBFRAC = 1476395;
	}
	else
	{
		DBG_Assert (FALSE);
	}

	REG_MISC_AUDIO_PLL = tmp;	

	asm("nop");
	asm("nop");

	REG_MISC_AUDIO_PLL_2 = tmp2;

	tmp = REG_MISC_AUDIO_PLL_3;
    
	pllfrac3_config = (MISC_PLLFRAC3_CONTROLs *) &tmp; 


	if (1) 
	{
		//if (pwm_out_en == 1 && pwm_mode == PWM_2304)
		if (0) // test
		{
			//only 1024x
			switch (spdif_dec_sf)
			{
			case SPDIF_SF_1x:
				pllfrac3_config->pllFrac_spdif_dec_n = 1;			
				break;
			case SPDIF_SF_2x:
				pllfrac3_config->pllFrac_spdif_dec_n = 0;
				break;	
			case SPDIF_SF_4x:
				DBG_Assert (FALSE);		//at this condition, only support 96k
				break;		
			case SPDIF_SF_hx:
				pllfrac3_config->pllFrac_spdif_dec_n = 2;				//only suport 96k
				break;		
			default:
				DBG_Assert (FALSE);
				break;
			}
		}
		else
		{
			switch (spdif_dec_sf)
			{
			case SPDIF_SF_1x:
				pllfrac3_config->pllFrac_spdif_dec_n = 2;				
				break;
			case SPDIF_SF_2x:
				pllfrac3_config->pllFrac_spdif_dec_n = 1;				
				break;	
			case SPDIF_SF_4x:
				pllfrac3_config->pllFrac_spdif_dec_n = 0;				
				break;		
			case SPDIF_SF_hx:
				pllfrac3_config->pllFrac_spdif_dec_n = 4;				
				break;		
			default:
				DBG_Assert (FALSE);
				break;
			}
		}
	}
		
	REG_MISC_AUDIO_PLL_3 = tmp;	    			

}
			
void hw_pll_headphone_sample_rate_set(int sample_rate)
{
#ifdef AUDIO_HEADPHONE_OUTPUT
	MISC_PLLFRAC3_CONTROLs *pllfrac3_config;
	volatile U32 temp;

	DBG_Printf("%s:%d\n\r", __func__, sample_rate);

	temp = REG_MISC_AUDIO_PLL_3;
	pllfrac3_config = (MISC_PLLFRAC3_CONTROLs *)&temp;

	switch (sample_rate)
	{
		case 192000:
		case 176400:
		case 128000:
		pllfrac3_config->pllFrac_spdif_enc_n = 1;
		break;

		case 96000:
		case 88200:
		case 64000:
		pllfrac3_config->pllFrac_spdif_enc_n = 2;
		break;

		case 48000:
		case 44100:
		case 32000:
		pllfrac3_config->pllFrac_spdif_enc_n = 4;
		break;

		default:
			DBG_Assert(FALSE);
			break;
	}

	REG_MISC_AUDIO_PLL_3 = temp;
#endif
}
void hw_audio_pll_clk_fre_frac_set (U32 fbfrac)
{
	volatile U32 tmp,tmp2;

	MISC_PLLFRAC1_CONTROLs *pllfrac1_config;
	MISC_PLLFRAC2_CONTROLs *pllfrac2_config;
	MISC_PLLFRAC3_CONTROLs *pllfrac3_config;
	
	tmp2 = 0;
	pllfrac2_config = (MISC_PLLFRAC2_CONTROLs *) &tmp2;

	pllfrac2_config->pllfrac_FBFRAC = fbfrac;///*9659640*/9667671-2000;//9667636	

	asm("nop");
	asm("nop");

	REG_MISC_AUDIO_PLL_2 = tmp2;
}

void hw_audio_pll_clk_adj_by_drift(double drift)
{
	U32 tmp,tmp2;

	MISC_PLLFRAC1_CONTROLs *pllfrac1_config;
	MISC_PLLFRAC2_CONTROLs *pllfrac2_config;
	double base_val,adjed_val;


	DBG_Printf("%d%%ppm\r\n",(int)(drift*100000000.0));
		//+-50ppm
	if (drift > 0.000050 || drift < -0.000050)
	{
		return;
	}

	if (app_main_data.playing_stream_sample_rate == 48000)
	{
		//12.288 12.288*8*6/24 = 24.576
		base_val = 24.576;
	}
	else if (app_main_data.playing_stream_sample_rate == 44100)
	{
		//11.2896 11.2896*8*6/24 = 22.5792
		base_val = 22.5792;
	}
	else 
	{
		//not support now,study later
		DBG_Assert(false);
		DBG_Printf("pll adj not support\r\n");
		return;
	}

	adjed_val = base_val - drift*base_val;


	tmp = REG_MISC_AUDIO_PLL;
	pllfrac1_config = (MISC_PLLFRAC1_CONTROLs *) &tmp;
	
	tmp2 = 0;
	pllfrac2_config = (MISC_PLLFRAC2_CONTROLs *) &tmp2;


	pllfrac1_config->pllFrac_FBDIV = (unsigned int)adjed_val;
	pllfrac2_config->pllfrac_FBFRAC = (adjed_val - (unsigned int)adjed_val)*0x1000000;


	DBG_Printf("audio clk adj int:%d,frac:%d\r\n",pllfrac1_config->pllFrac_FBDIV,pllfrac2_config->pllfrac_FBFRAC);

	REG_MISC_AUDIO_PLL = tmp;	

	asm("nop");
	asm("nop");

	REG_MISC_AUDIO_PLL_2 = tmp2;	
}

void hw_audio_pll_clk_adj_by_dist_offset(U32 local_distance,i32 offset)
{
	double drift = (double)offset/(double)local_distance;

	hw_audio_pll_clk_adj_by_drift(drift);
}


volatile U32 hcountms,devfirst_ccount = 0,devcur_ccount;

void clock_sync_init(void)
{
	//sofnum = 0;
	//devcur_ccount = 0;
	devfirst_ccount = 0;
}

int host_dev_clock_get(U32 *host_clk,U32 *dev_clk)
{
	if (devfirst_ccount == 0 || hcountms == 0)
	{
		// clk not present
		*host_clk = 1;
		*dev_clk = 1;
		return 0;
	}

	U32 first_cc,cur_cc,num;

	TX_DISABLE;
	first_cc = devfirst_ccount;
	cur_cc = devcur_ccount;
	num = hcountms;
	TX_RESTORE;	

	*host_clk = (num*(SYS_CLK_FREQ_DEFAULT/1000));

	if (cur_cc >= first_cc)
		*dev_clk = (cur_cc - first_cc);
	else
		*dev_clk = (0x100000000L + (cur_cc - first_cc));
	
	return 1;
}