#ifndef	_REGMAP_H
#define	_REGMAP_H

#include "c_def.h"

#if 0
typedef enum 
{
	FREQ_4MHZ,
	FREQ_12MHZ,
	FREQ_24MHZ,
	FREQ_36MHZ,
	FREQ_48MHZ,
	FREQ_60MHZ,
	FREQ_72MHZ,
	FREQ_84MHZ,
	FREQ_96MHZ,
	FREQ_108MHZ,
	FREQ_114MHZ,
	FREQ_120MHZ,
//	FREQ_128MHZ,
//	FREQ_132MHZ,
//	FREQ_144MHZ,

	FREQ_32kHZ,
	FREQ_DIV_12MHZ,
	FREQ_DIV_6MHZ,
	FREQ_DIV_4MHZ,
	FREQ_DIV_2MHZ,
	FREQ_DIV_1MHZ,
	LAST_FREQ
} ClockFreqIndex;

typedef enum 
{
	F12MHZ = 12,
	F24MHZ = 24,
	F36MHZ = 36,
	F48MHZ = 48,
	F72MHZ = 72,
	F84MHZ = 84,
	F96MHZ = 96,
	F108MHZ = 108,
	F120MHZ = 120,
	F128MHZ = 128,
	F132MHZ = 132,
	F144MHZ = 144
} ClockFreqValue;

//#define SYS_CLK_FREQ_DEFAULT    FREQ_24MHZ
//#define SYS_CLK_FREQ_DEFAULT    FREQ_36MHZ
//#define SYS_CLK_FREQ_DEFAULT    FREQ_48MHZ
#define SYS_CLK_FREQ_DEFAULT    FREQ_72MHZ
//#define SYS_CLK_FREQ_DEFAULT    FREQ_96MHZ
//#define SYS_CLK_FREQ_DEFAULT    FREQ_144MHZ
#endif

#define	REG8(addr)				(*(volatile U8 *)(addr))
#define	REG16(addr)				(*(volatile U16 *)(addr))
#define	REG32(addr)				(*(volatile U32 *)(addr))
#define	REG64(addr)				(*(volatile U64 *)(addr))

#define	REG(addr)				(*(volatile U32 *)(addr))



/*-----------------------------------------------------------------------------------------------------*/
/*
 * 	POWER_DOWN
 * 
 */

#define POWER_DOWN_BASE_REG				REG( MEM_SELECTOR_BASE_ADDR + 0x00 )

#define BIT_POWER_DOWN_NANDFLASH		bit0
#define BIT_POWER_DOWN_NANDFLASH_POS	0

#define BIT_POWER_DOWN_USB				bit1
#define BIT_POWER_DOWN_USB_POS			1

#define BIT_POWER_DOWN_SD				bit2
#define BIT_POWER_DOWN_SD_POS			2

#define	MEM_SELECTOR_REG				REG(MEM_SELECTOR_BASE_ADDR)

#define	MEM_SELECTOR_MASK				0x07
#define	MEM_SEL_SD_MASK					(1 << 2)
#define	MEM_SEL_USB_MASK				(1 << 1)
#define	MEM_SEL_NANDFLASH_MASK			(1 << 0)


/*-----------------------------------------------------------------------------------------------------*/
/*
 * 	CLKDIV
 * 
 */

#define CLKDIV_REG				REG( CLKDIV_BASE_ADDR + 0x00 )

#define BIT_SDRAM_CLKDIV		bit0
#define BIT_SDRAM_CLKDIV_POS	0

#define BIT_SD_CLKDIV			bit1
#define BIT_SD_CLKDIV_POS		1

#define BIT_NANF_CLKDIV			bit2
#define BIT_NANF_CLKDIV_POS		2

#define BIT_ADC_CLKDIV			bit3
#define BIT_ADC_CLKDIV_POS		3

#define BIT_SYS_CLKDIV			bit4
#define BIT_SYS_CLKDIV_POS		4

#define BIT_IRDA_CLKDIV			bit5
#define BIT_IRDA_CLKDIV_POS		5

/*-------------------------------------------------------------*/
//bit0 -- bit7, clock div = CLK / (2 to the power of N)
#define DIV_SDRAM_CLK_REG	REG( CLKDIV_BASE_ADDR + 0x04)
#define DIV_SD_CLK_REG		REG( CLKDIV_BASE_ADDR + 0x08)
#define DIV_NANF_CLK_REG	REG( CLKDIV_BASE_ADDR + 0x0c)
#define DIV_ADC_CLK_REG		REG( CLKDIV_BASE_ADDR + 0x10)
#define DIV_SYS_CLK_REG		REG( CLKDIV_BASE_ADDR + 0x14)
#define DIV_IRDA_CLK_REG	REG( CLKDIV_BASE_ADDR + 0x18)



/*---------------------------------------------------------------------------------------------
-----------------------Optek SOC Test Register-------------------------------------------------
----------------------------------------------------------------------------------------------*/
#define	INT_CONTROLLER_BASE_ADDR	0x10100000
#define	REG_INTCON_INT_ENA			REG( INT_CONTROLLER_BASE_ADDR + 0 )
#define	REG_INTCON_INT_STA			REG( INT_CONTROLLER_BASE_ADDR + 4 )
#define	REG_INTCON_INT_VER			REG( INT_CONTROLLER_BASE_ADDR + 8 )
#define	REG_INTCON_INT_TEST			REG( INT_CONTROLLER_BASE_ADDR + 12 )

typedef volatile struct{
	U32	day		: 8;	
	U32	month	: 8;	
	U32	year	: 8;	
	U32	ver		: 8;	
} IP_VERSIONs;

#define	bVERSION_DAY(a)		(*(IP_VERSIONs *)&(a)).day
#define	bVERSION_MONTH(a)	(*(IP_VERSIONs *)&(a)).month
#define	bVERSION_YEAR(a)	(*(IP_VERSIONs *)&(a)).year
#define	bVERSION_NUM(a)		(*(IP_VERSIONs *)&(a)).ver

typedef volatile struct{
	U32	uart	: 1;	//bit0 is uart
	U32	spi		: 1;	//bit1 is spi
	U32	i2s0	: 1;	//bit2 is i2s0
	U32	i2s1	: 1;	//bit3 is i2s1
	U32 i2c0	: 1;	//bit4 is i2c0
	U32 lcd		: 1;	//bit5 is lcd
	U32 sd		: 1;	//bit6 is sd card
	U32 rtc		: 1;	//bit7 is rtc
	U32			: 22;
	U32 i2c1	: 1;	//bit30 is i2c1
	U32	spi_test: 1;	//bit31 is spi
} INT_CONTROLs;

#define	bINT_ENABLE_UART		(*(INT_CONTROLs *)&REG_INTCON_INT_ENA).uart
#define	bINT_ENABLE_SPI			(*(INT_CONTROLs *)&REG_INTCON_INT_ENA).spi
#define	bINT_ENABLE_SPI_TEST	(*(INT_CONTROLs *)&REG_INTCON_INT_ENA).spi_test
#define bINT_ENABLE_I2S0		(*(INT_CONTROLs *)&REG_INTCON_INT_ENA).i2s0
#define bINT_ENABLE_I2S1		(*(INT_CONTROLs *)&REG_INTCON_INT_ENA).i2s1
#define bINT_ENABLE_I2C0		(*(INT_CONTROLs *)&REG_INTCON_INT_ENA).i2c0
#define bINT_ENABLE_I2C1		(*(INT_CONTROLs *)&REG_INTCON_INT_ENA).i2c1
#define bINT_ENABLE_LCD			(*(INT_CONTROLs *)&REG_INTCON_INT_ENA).lcd
#define bINT_ENABLE_SD			(*(INT_CONTROLs *)&REG_INTCON_INT_ENA).sd
#define bINT_ENABLE_RTC			(*(INT_CONTROLs *)&REG_INTCON_INT_ENA).rtc


/*-----------------------------------------------------------------------------------------------------*/
/*
 * 	UART
 * 
 */

#define	UART0_BASE_ADDR		0x10200000
#define	UART1_BASE_ADDR		0x10400000
#define	UART2_BASE_ADDR		0x10C00000//0x18000000//0x10C00000

#define	REG_UART0_TX_DATA	REG( UART0_BASE_ADDR + 20 )
#define	REG_UART0_RX_DATA	REG( UART0_BASE_ADDR + 24 )
#define	REG_UART0_VERSION	       REG( UART0_BASE_ADDR + 28 )

#define   MDM_BASE_ADDR                     0x10000000
#define	HDMICEC_BASE_ADDR		0x18000000
#define	CODEC_BASE_ADDR			0x18100000
#define   BTRF_AGC_BASE_ADDR           0x18400000
/*
 *	base addr define
 */
#define	BASE_ADDR_GPIO			0x10500000
#define	BASE_ADDR_MISC			0x10600000
#define	BASE_ADDR_INTC			0x10100000

/*
*
* TEST  CEVA MDM  and AGC
*/
#define   TEST_REG_MDM                         REG32(MDM_BASE_ADDR + (0xd8<<2))

#define   TEST_REG_AGC0                        REG32(BTRF_AGC_BASE_ADDR)
#define   TEST_REG_AGC1                        REG32(BTRF_AGC_BASE_ADDR + (1<<2))

typedef volatile struct {

U32 min_rf_signal_s      : 4;// = regConfig[3:0];
U32 rf_gain_stb             : 3;//= regConfig[6:4];
U32 rf_gain_init             : 3;//= regConfig[9:7];
U32 mac2rfdac_mode    : 2;//= regConfig[11:10];
U32 rfadc2mac_mode    : 2;//= regConfig[13:12];

} BTRF_AGC_CONTROL0;//TEST_REG_AGC0


typedef volatile struct {

U32 rf_adc_lev_max      : 10;//= regConfig_2[9:0];
U32 rf_adc_lev_min        : 10;//= regConfig_2[19:10];

} BTRF_AGC_CONTROL1;//TEST_REG_AGC1


/*audio codec**********/
#define	REG_CODEC_R01          REG8( CODEC_BASE_ADDR + (0x01<<2))
#define	REG_CODEC_R02          REG8( CODEC_BASE_ADDR + (0x02<<2))
#define	REG_CODEC_R03          REG8( CODEC_BASE_ADDR + (0x03<<2))
#define	REG_CODEC_R04          REG8( CODEC_BASE_ADDR + (0x04<<2))
#define	REG_CODEC_R05          REG8( CODEC_BASE_ADDR + (0x05<<2))
#define	REG_CODEC_R06          REG8( CODEC_BASE_ADDR + (0x06<<2))
#define	REG_CODEC_R07          REG8( CODEC_BASE_ADDR + (0x07<<2))
#define	REG_CODEC_R08          REG8( CODEC_BASE_ADDR + (0x08<<2))
#define	REG_CODEC_R09          REG8( CODEC_BASE_ADDR + (0x09<<2))

#define	REG_CODEC_R0B          REG8( CODEC_BASE_ADDR + (0x0B<<2))
#define	REG_CODEC_R0C          REG8( CODEC_BASE_ADDR + (0x0C<<2))
#define	REG_CODEC_R0D          REG8( CODEC_BASE_ADDR + (0x0D<<2))
#define	REG_CODEC_R0E          REG8( CODEC_BASE_ADDR + (0x0E<<2))
#define	REG_CODEC_R0F          REG8( CODEC_BASE_ADDR + (0x0F<<2))

#define	REG_CODEC_R10          REG8( CODEC_BASE_ADDR + (0x10<<2))
#define	REG_CODEC_R11          REG8( CODEC_BASE_ADDR + (0x11<<2))

#define	REG_CODEC_R12			REG8( CODEC_BASE_ADDR + (0x12<<2))
#define	REG_CODEC_R13			REG8( CODEC_BASE_ADDR + (0x13<<2))
#define	REG_CODEC_R14			REG8( CODEC_BASE_ADDR + (0x14<<2))
#define	REG_CODEC_R15			REG8( CODEC_BASE_ADDR + (0x15<<2))
#define	REG_CODEC_R16			REG8( CODEC_BASE_ADDR + (0x16<<2))
#define	REG_CODEC_R17			REG8( CODEC_BASE_ADDR + (0x17<<2))
#define	REG_CODEC_R18			REG8( CODEC_BASE_ADDR + (0x18<<2))
#define	REG_CODEC_R19			REG8( CODEC_BASE_ADDR + (0x19<<2))

#define	REG_CODEC_R1E			REG8( CODEC_BASE_ADDR + (0x1E<<2))

#define	REG_CODEC_R36           REG8( CODEC_BASE_ADDR + (0x36<<2))

#define	REG_CODEC_R40			REG8( CODEC_BASE_ADDR + (0x40<<2))
#define	REG_CODEC_R41			REG8( CODEC_BASE_ADDR + (0x41<<2))
#define	REG_CODEC_R42			REG8( CODEC_BASE_ADDR + (0x42<<2))
#define	REG_CODEC_R43			REG8( CODEC_BASE_ADDR + (0x43<<2))
#define	REG_CODEC_R44			REG8( CODEC_BASE_ADDR + (0x44<<2))
#define	REG_CODEC_R45			REG8( CODEC_BASE_ADDR + (0x45<<2))
#define	REG_CODEC_R47			REG8( CODEC_BASE_ADDR + (0x47<<2))
#define	REG_CODEC_R48			REG8( CODEC_BASE_ADDR + (0x48<<2))
#define	REG_CODEC_R49			REG8( CODEC_BASE_ADDR + (0x49<<2))
#define	REG_CODEC_R4A			REG8( CODEC_BASE_ADDR + (0x4A<<2))
#define	REG_CODEC_R4B			REG8( CODEC_BASE_ADDR + (0x4B<<2))
#define	REG_CODEC_R4C			REG8( CODEC_BASE_ADDR + (0x4C<<2))
#define	REG_CODEC_R4D			REG8( CODEC_BASE_ADDR + (0x4D<<2))
#define	REG_CODEC_R4E			REG8( CODEC_BASE_ADDR + (0x4E<<2))
#define	REG_CODEC_R4F			REG8( CODEC_BASE_ADDR + (0x4F<<2))

#define	REG_CODEC_R51			REG8( CODEC_BASE_ADDR + (0x51<<2))
#define	REG_CODEC_R52			REG8( CODEC_BASE_ADDR + (0x52<<2))
#define	REG_CODEC_R53			REG8( CODEC_BASE_ADDR + (0x53<<2))
#define	REG_CODEC_R54			REG8( CODEC_BASE_ADDR + (0x54<<2))
#define	REG_CODEC_R55			REG8( CODEC_BASE_ADDR + (0x55<<2))

#define	REG_CODEC_R57			REG8( CODEC_BASE_ADDR + (0x57<<2))

#define	REG_CODEC_R5A			REG8( CODEC_BASE_ADDR + (0x5A<<2))
#define	REG_CODEC_R5B			REG8( CODEC_BASE_ADDR + (0x5B<<2))


/*
 * 	gpio
 */

#define	REG_GPIO0_DIN			REG( BASE_ADDR_GPIO + 0 )
#define	REG_GPIO0_DOUT			REG( BASE_ADDR_GPIO + 4 )
#define	REG_GPIO0_DOE			REG( BASE_ADDR_GPIO + 8 )
#define REG_GPIO0_INTEN			REG( BASE_ADDR_GPIO + 12 )
#define	REG_GPIO0_INTST			REG( BASE_ADDR_GPIO + 16 )
#define	REG_GPIO0_INTTP0		REG( BASE_ADDR_GPIO + 20 )
#define	REG_GPIO0_INTTP1		REG( BASE_ADDR_GPIO + 24 )
#define	REG_GPIO0_FUNC			REG( BASE_ADDR_GPIO + 28 )

#define	REG_GPIO1_DIN			REG( BASE_ADDR_GPIO + 32 )
#define	REG_GPIO1_DOUT			REG( BASE_ADDR_GPIO + 36 )
#define	REG_GPIO1_DOE			REG( BASE_ADDR_GPIO + 40 )
#define REG_GPIO1_INTEN			REG( BASE_ADDR_GPIO + 44 )
#define	REG_GPIO1_INTST			REG( BASE_ADDR_GPIO + 48 )
#define	REG_GPIO1_INTTP0		REG( BASE_ADDR_GPIO + 52 )
#define	REG_GPIO1_INTTP1		REG( BASE_ADDR_GPIO + 56 )
#define	REG_GPIO1_FUNC			REG( BASE_ADDR_GPIO + 60 )

#define	REG_GPIO2_DIN			REG( BASE_ADDR_GPIO + 64 )
#define	REG_GPIO2_DOUT			REG( BASE_ADDR_GPIO + 68 )
#define	REG_GPIO2_DOE			REG( BASE_ADDR_GPIO + 72 )
#define REG_GPIO2_INTEN			REG( BASE_ADDR_GPIO + 76 )
#define	REG_GPIO2_INTST			REG( BASE_ADDR_GPIO + 80 )
#define	REG_GPIO2_INTTP0		REG( BASE_ADDR_GPIO + 84 )
#define	REG_GPIO2_INTTP1		REG( BASE_ADDR_GPIO + 88 )
#define	REG_GPIO2_FUNC			REG( BASE_ADDR_GPIO + 92 )


//OTK528x, only GPIO0 and GPIO1 can gen int
#define   REG_GPIO0_IE				REG( BASE_ADDR_GPIO + 100 )
#define   REG_GPIO1_IE				REG( BASE_ADDR_GPIO + 104 )
#define   REG_GPIO2_IE				REG( BASE_ADDR_GPIO + 108 )
#define	REG_GPIO3_FUNC			REG( BASE_ADDR_GPIO + 112 )


/*
 * 	misc
 */

#define	REG_MISC_CFG			REG( BASE_ADDR_MISC + 0 )
#define	REG_MISC_PLL			REG( BASE_ADDR_MISC + 4 )
#define	REG_MISC_CLKGATE		REG( BASE_ADDR_MISC + 8 )
#define	REG_MISC_ADC_CTL		REG( BASE_ADDR_MISC + 12 )
#define	REG_MISC_ADC_DATA		REG( BASE_ADDR_MISC + 16 )
#define	REG_MISC_SDRAM_CFG1		REG( BASE_ADDR_MISC + 20 )
#define	REG_MISC_SDRAM_CFG2     REG( BASE_ADDR_MISC + 24 )

#define REG_MISC_VERSION        REG( BASE_ADDR_MISC + 28 )
#define REG_MISC_IDRAM_SEL      REG( BASE_ADDR_MISC + 32 )
                                                                   
#define REG_MISC_CONTROL        REG( BASE_ADDR_MISC + 36 )   
#define REG_MISC_AUDIO_PLL      REG( BASE_ADDR_MISC + 40 )
#define REG_MISC_AUDIO_PLL_2    REG( BASE_ADDR_MISC + 44 )
#define REG_MISC_AUDIO_PLL_3    REG( BASE_ADDR_MISC + 48 )
#define REG_MISC_AUDIO_PLL_4    REG( BASE_ADDR_MISC + 52)
#define REG_MISC_BTDM           REG( BASE_ADDR_MISC + 56 )
#define REG_MISC_DCXO           REG( BASE_ADDR_MISC + 60 )
#define REG_MISC_AUDIO_CODEC    REG( BASE_ADDR_MISC + 64)
#define REG_MISC_USBPHY         REG( BASE_ADDR_MISC + 68)
#define REG_MISC_RTCWD          REG( BASE_ADDR_MISC + 72)
#define REG_MISC_RTCRD          REG( BASE_ADDR_MISC + 76)
#define REG_MISC_RTC            REG( BASE_ADDR_MISC + 80)
#define REG_MISC_BTDM_2         REG( BASE_ADDR_MISC + 84)

//bit
#define	REG_MISC_SDRAM_CFG2_BIT_SFLASH		(1 << 16)
#define	REG_MISC_SDRAM_CFG2_BIT_DBG			(1 << 17)

/*
`define APB_gate				1			//reset is on, soc global
`define boot_gate                               2                       //not through bus, reset is on
`define AHBSdram_gate                           3                       //reset is on for debug
`define AHBSpiFlash_gate                        4                       //not through bus, reset is on
`define DMA_AHB_gate				5			//0 is global ahb clk enable, reset is on
`define APB_misc_gate                           6                       //0 is global ahb clk enable, reset is on



`define AHB_Audio_Controller_gate	0
`define sd_gate						1
`define usbOtgSd_gate				2
`define AHB_BTDM_IF_gate			3
`define AHB_BTDM_IF_pclk_gate		4
`define u_uart0_gate				5
`define u_uart1_gate				6
`define u_uart2_gate				7
`define hdmi_cec_gate				8
`define spi_gate					9
`define codec_apb_gate				10
`define i2c_gate					11
`define u_pwm_gate					12
`define u_pwm2_gate					13
`define u_pwm3_gate					14
`define u_pwm5_gate					15
`define	u_rotary_gate				16
`define u_rotary2_gate				17
`define IR_controller_gate			19		
`define lp_bt_usb_gate                      20
*/


typedef volatile struct {
U32	AHB_Audio_Controller_gate		:1; 
U32	 sd_gate            					:1;	
U32	usbOtgSd_gate               			:1;    
U32  AHB_BTDM_IF_gate          		:1;    
U32	AHB_BTDM_IF_pclk_gate   		:1;  
U32  u_uart0_gate					:1;		
U32  u_uart1_gate      					:1;	
U32  u_uart2_gate      					:1;	
U32  hdmi_cec_gate   					:1;	
U32  spi_gate   						:1;	
U32  codec_apb_gate 					:1;	
U32  i2c_gate           					:1;	   
U32	u_pwm_gate 					:1;	
U32	 u_pwm2_gate     				:1;	            			
U32	u_pwm3_gate    					:1;	                  
U32  u_pwm5_gate    					:1;	          
U32	u_rotary_gate     					:1;	
U32  u_rotary2_gate					:1;					
U32  res_1							:1;					
U32  IR_controller_gate   				:1;	
U32  lp_bt_usb_gate 					:1;	
U32  res_2 							:12;	
} MISC_CLKGATE_CONTROLs;


typedef volatile struct {
U32	codec_Resetn                       : 1;//  
U32	codec_I2C_mode                 : 1;// reserve
U32	codec_MODE                         : 1;// 0:I2C; 1:MCU	
U32  codec_CSB                           : 1;// 0:I2c addr 10h; 1 :I2c addr 14h;
U32	codec_EXT_CLK_div             : 4;//
U32  uart1rx_pin_sel                :1; // 1 sel from sdram mux pin
U32  uart2rx_pin_sel                 :1; // 1 sel from sdram mux pin
U32  mi2sin_pin_sel                  :1;    // 1 sel from sdram mux pin
U32  i2s_st_pin_sel                 :1;     // 1 sel from sdram mux pin
U32  spi_pin_sel                    :1;     // 1 sel from sdram mux pin
U32  bt_mdm_iq_swap                 :2; 

} MISC_AUDIO_CODEC_CONTROLs;//REG_MISC_AUDIO_CODEC

typedef volatile struct {

	U32	dcxo_rg_dcxo_en_12d                            : 1;// regDCXO[0];
	U32	dcxo_rg_dcxo_enout_12d                       : 1;// regDCXO[1];
	U32	dcxo_rg_dcxo_pwr_int_en_12d              : 1;// regDCXO[2];
	U32	dcxo_rg_dcxo_ldo_en_12d                     : 1;// regDCXO[3];
	U32	dcxo_rg_dcxo_enfst_12d                        : 1;// regDCXO[4];
	U32	dcxo_rg_dcxo_acl_type_12d                   : 1;// regDCXO[5];
	U32	dcxo_rg_dcxo_pwr_tmuxen_12d             : 1;// regDCXO[6];
	U32	dcxo_rg_dcxo_trim_12d                          : 9;// regDCXO[15:7];
	U32	dcxo_rg_dcxo_tmuxen_12d                     : 1;// regDCXO[16];
	U32	dcxo_rg_dcxo_ldo_short_en_12d            : 1;// regDCXO[17];
	U32	dcxo_rg_dcxo_ldo_vout_set_12d             : 3;// regDCXO[20:18];
	U32	dcxo_rg_dcxo_ldo_fcen_12d                     : 1;// regDCXO[21];
	U32	dcxo_rg_dcxo_rssi_en_12d                       : 1;// regDCXO[22];
	U32	dcxo_da_dcxo_icnst_12d                           : 4;// regDCXO[26:23];

} MISC_DCXO_CONTROLs;//REG_MISC_DCXO



typedef volatile struct {
	U32 BT_hclkratio                                 : 4;// regBTDM [3:0];
	U32 btrf_dd_adda_sync_clk_en         : 1;// regBTDM [4];
	U32 btrf_ad_pwr_rstn_12d                 : 1;// regBTDM [5];
	U32 bt_dbg_sel_1                                : 3;// regBTDM [8:6];
	U32 bt_dbg_sel_2                                : 3;// regBTDM [11:9];
	U32 bt_dbg_en                                     : 1;// regBTDM [12];		
	//U32 bt_mdm_iq_swap                                : 1;// regBTDM [13];
	U32 bt_rf_adc_max                                 : 9;//regBTDM [21:13]
	U32 bt_rf_adc_min                                 : 9;//regBTDM [30:22]
    U32 bt_if_2M                                      : 1;//regBTDM [31]        
        
} MISC_BTDM_CONTROLs;//REG_MISC_BTDM

/*
assign bt_clksel = regBTDM_2[4:0];				
assign bt_rf_gain_start = regBTDM_2[7:5];		  
assign bt_rf_agc_update_time = regBTDM_2[14:8];			
assign bt_if_rssi_sel = regBTDM_2[15];				
assign bt_rf_stb_act_time = regBTDM_2[22:16];
assign bt_rf_dc_block_filter = regBTDM_2[24:23];
assign bt_PA_en =  regBTDM_2[26:25];				

assign bt_rf_dc_block_filter_en = regBTDM_2[27];
assign bt_WCI_en = regBTDM_2[29:28];
*/

typedef volatile struct {
    U32 bt_clksel : 5;
    U32 bt_rf_gain_start : 3;
    U32 bt_rf_agc_update_time : 7;
    U32 bt_if_rssi_sel : 1;
    U32 bt_rf_stb_act_time : 7;
    U32 bt_rf_dc_block_filter : 2;
    U32 bt_PA_en : 2;
    U32 bt_rf_dc_block_filter_en : 1;
    U32 bt_WCI_en : 2; 
    U32 bt_tx_disable : 1;
    U32 bt_tx_packet_disable : 1;
} MISC_BTDM_2_CONTROLs;//REG_MISC_BTDM


typedef volatile struct {

	//U32	rtc_wdata->REG_MISC_RTCWD
	//U32	rtc_rdata->REG_MISC_RTCRD

	U32 rtc_addr                            : 4;// regRTC[3:0];
	//U32 rtc_rd                              : 1;// regRTC[4]; active high
	//U32 rtc_wr                              : 1;// regRTC[5]; active high	
	U32 rtc_spi_rwn                        : 1; //rd :1  ;wr :0;rtc_rd_wrn
	U32 rtc_spi_go                          : 1;  // rd_wr :1;  
	//U32 rtc_rw_tag                        : 4;// regRTC[9:6]; 4'b1010 write, 4'b0101 read;		
	U32 rtc_en                                : 1;
	U32 btdm_en                             : 1;
	U32 cpu_mem_emaw                : 2;
	U32 cpu_mem_ema                  :3;
	U32 cpu_mem_iram0_rtein      : 1;// regRTC[15];
	U32 cpu_mem_dram0_rtein     : 1;
	U32 cpu_mem_dram1_rtein     : 1;
	U32 rtc_rw_fini                         : 1;
	U32 rtc_rw_go_fini                    :1;
	
	//U32 rtc_csn                 : 1;// regRTC[10];	low active
	//U32	rtc_rw_fini           : 1;// regRTC[11]; read/write finish	
	//U32 reg_rw_fini_32k   : 1;
	
} MISC_RTC_CONTROLs;//REG_MISC_RTC

/*
parameter
	ADDR_CTRL			=	4'd1,
	ADDR_TIMER_WT		=	4'd2,
	ADDR_ALARM0			=	4'd3,
	ADDR_ALARM1			=	4'd4,
	ADDR_ALARM2			=	4'd5,
	ADDR_TIMER_RD		=	4'd6,
	ADDR_TIMER32k_RD	=	4'd7,

	ADDR_EEROM_1		=	4'd8,
	ADDR_EEROM_2		=	4'd9,			
	ADDR_VER			=	4'd10;
*/

#define RTC_CTRL_ADDR			 	 1
#define RTC_TIMER_WT_ADDR		 	 2
#define RTC_ALARM0_ADDR			 3
#define RTC_ALARM1_ADDR			 4
#define RTC_ALARM2_ADDR			 5
#define RTC_TIMER_RD_ADDR		 	 6
#define RTC_TIMER32k_RD_ADDR	 	 7
#define RTC_EEROM_1_ADDR		 	 8
#define RTC_EEROM_2_ADDR		 	 9	
#define RTC_CTRL2_ADDR			 	 10
#define RTC_VER_ADDR			 	 11



typedef volatile struct {
	U32	rtc_Sel		       : 1;//		regCtl[0]; 1'b0 select rc_32k, 1'b1 selelct crystal 32k
	U32	rtc_pd		       : 1;//		regCtl[1];	1'b1 rc 32k power down	
	U32 alarm0En		: 1;//		regCtl[2]; 
	U32 alarm1En		: 1;//		regCtl[3];
	U32 alarm2En		: 1;//		regCtl[4];
	U32 alarm0Int               : 1;//		write 1'b1 clear alarm0 int, read alarm0 int status
	U32 alarm1Int               : 1;//		write 1'b1 clear alarm0 int, read alarm0 int status
	U32 alarm2Int               : 1;//		write 1'b1 clear alarm0 int, read alarm0 int status		
	U32 rtc_DF		          : 7;//		regCtl[14:8] trimming rc 32k;
	U32 rtc_crystal_en        : 1;//	regCtl[15]; 	
	U32	minPoweronWidth  : 10;// regCtl[25:16]; min low level width for power on about 16ms
	U32 reg_power              : 1;// regCtl[26];	1'b1 power on, 1'b0 power off
	U32 reg_power_key_en : 1;// regCtl[27];
	U32 reg_ir_en                 : 1;// regCtl[28];
	U32 reg_hdmicec_en      : 1;// regCtl[29];

} RTC_CTRL_ST;//RTC_CTRL_ADDR

typedef volatile struct {
	U32 trim                  : 3;
	U32 lp_clk_en         : 1;

} RTC_CTRL2_ST;//RTC_CTRL_ADDR

typedef volatile struct {
//write only
//	bit16:bit0->seconds
//	bit31:bit17->days

	U32 sec        :17;
	U32 days       :15;

} RTC_TIMER_ST;

typedef volatile struct {
//ADDR_ALARM0,ADDR_ALARM1
//read/write, reset 32'hffffffff	
//	bit16:bit0->seconds
//	bit31:bit17->days						if days is zero, means every alarm

	U32 sec        :17;
	U32 days       :15;

} RTC_DAY_SEC_ST;


typedef volatile struct {
//ADDR_ALARM2
//read/write, reset 32'hffffffff
//	bit31:bit15->seconds
//	bit14:bit0->32k

	U32 count_32K  : 15;
       U32 sec              : 17;

}RTC_SEC_32K_ST;

typedef volatile struct {


	U32 usbphy_cfg_rdata    : 8;// regUSBPHY[7:0];
	U32 usbphy_cfg_wdata   : 8;// regUSBPHY[15:8];
	U32 usbphy_cfg_addr     : 6;// regUSBPHY[21:16];
	U32 usbphy_cfg_wren    : 1;// regUSBPHY[22];
	U32 usbphy_cfg_rden     : 1;// regUSBPHY[23];
	U32 usbphy_cfg_rstn	     : 1;// regUSBPHY[24];

	U32 utmi_iddig_src         : 1;// regUSBPHY[25];
	U32 utmi_iddig_sw          : 1;// regUSBPHY[26];
	U32 utmi_vbus_src         : 1;// regUSBPHY[27];

	
} MISC_USBPHY_CONTROLs;//REG_MISC_USBPHY



typedef volatile struct {
	U32	regConfig_cpuClkSel	                : 2;//2'b10 sel 24M crystal, 2'b01 sel pll or rtc
	U32 regConfig_pllRtcSel	                : 2; //2'b01 sel pll, 2'b10 sel rtc	//	regConfig[3:2];
	U32 regConfig_crystalDivSel	         : 2;//	regConfig[5:4];
	U32 regConfig_crystalEna		         : 1;//	regConfig[6];
	U32 regConfig_crystalDiv	                : 6;//	regConfig[12:7];	//6 bits div
	U32 regConfig_mclkOutEna		  : 1;//	regConfig[13];
	U32 regConfig_clk12M_AVclk_sel	  : 1;//	regConfig[14];
	U32 regConfig_padAVclk_sel		  : 1;//	regConfig[15];
	U32 lp_clk_from_24M_en                  : 1;// regConfig[16];
	U32 lp_clk_sel                                   : 1;// regConfig[17];			
	U32 lp_clk_en                                    : 1;// regConfig[18];
	U32 CLK_12M_en                                : 1;// regConfig[19];
	U32 CLK_24Div_gen_en                     : 1;// regConfig[20];

	U32 mclk1_s : 1;// regConfig[21];            // 0: mclk_1_out = pllFrac_256x;  1: mclk_1_out = CLK_12M;
	U32 mclk2_s : 1;// regConfig[22];            // 0: mclk_2_out = pllFrac_256x;  1: mclk_2_out = lp_clk;
	U32 mclk1_in_out : 1;// regConfig[23];   // 0: input   1: output
	U32 mclk2_in_out : 1;//regConfig[24];   // 0: input    1:output
	U32 clk24M_I_trim : 3;// regConfig[30:25];
	U32 clk24M_C_trim : 3;
} MISC_CFG_CONTROLs;//REG_MISC_CFG


typedef volatile struct {
	U32	pll_PD	                : 1;//regPLL[0];
	U32 pll_REFDIV             : 6;//regPLL[6:1];
	U32 pll_FBDIV               : 12;//regPLL[18:7];
	U32 pll_POSTDIV1         : 3;//regPLL[21:19];
	U32 pll_POSTDIV2         : 3;//regPLL[24:22];
	U32 pll_Dynamic_DIV    : 5; //0 bypass, orthers /2*div	//regPLL[29:25];
	U32 pll_DACDSMPD    : 1;//regPLL[30]
	U32 pll_Lock                    : 1;//regPLL[31]

	
} MISC_PLL_CONTROLs;//REG_MISC_PLL


typedef volatile struct {
	U32 pllFrac_PD                                     : 1;// regAudioPLL[0];
	U32 pllFrac_REFDIV                              : 6;// regAudioPLL[6:1];
	U32 pllFrac_FBDIV                                : 12;// regAudioPLL[18:7];
	U32 pllFrac_POSTDIV1                          : 3;// regAudioPLL[21:19];
	U32 pllFrac_POSTDIV2                          : 3;// regAudioPLL[24:22];
	U32 pllFrac_CLKSSCG_en                      : 1;// regAudioPLL[25];
	U32 pllFrac_2048x_256x_en                : 1;// regAudioPLL[26];
	U32 pllFrac_2048x_spdif_dec_en        : 1;// regAudioPLL[27];
	U32 pllFrac_2048x_spdif_enc_en        : 1;// regAudioPLL[28];
	U32 pllFrac_256x_en                            : 1;// regAudioPLL[29];
	U32 reserve                                          : 1;// regAudioPLL[30];
	U32 pllFrac_Lock                                      : 1;//regAudioPLL[31];
	
} MISC_PLLFRAC1_CONTROLs;//REG_MISC_AUDIO_PLL

typedef volatile struct {

	U32 pllfrac_FBFRAC : 24;// regAudioPLL_2[23:0];

	
} MISC_PLLFRAC2_CONTROLs;


typedef volatile struct {

	U32 pllFrac_256x_n                  : 5;// regAudioPLL_3[4:0];
	U32 pllFrac_spdif_dec_n          : 5;//  regAudioPLL_3[9:5];
	U32 pllFrac_spdif_enc_n          : 5;// regAudioPLL_3[14:10];
	U32 pllFrac_dmic_n                  : 5;// regAudioPLL_3[19:15];
	U32 pllFrac_2048x_SEL            : 2;// regAudioPLL_3[21:20];
	U32 pllFrac_256x_SEL              : 1;// regAudioPLL_3[22];
	U32 pllFrac_FREF_SEL              : 2;// regAudioPLL_3[24:23];
	U32 pllFrac_pwm_clk_SEL        : 1;// regAudioPLL_3[25];
	U32 pllFrac_pwm_clk_en          : 1;// regAudioPLL_3[26];
	U32 pllFrac_256x_dmic_en                 : 1;// regAudioPLL_3[27];
	U32 pllFrac_dmic_clk_en        : 1;// regAudioPLL_3[28];
	U32 pllFrac_spdif_dec_en          : 1;// regAudioPLL_3[29];
	U32 pllFrac_spdif_enc_en                 : 1;// regAudioPLL_3[30];


	
} MISC_PLLFRAC3_CONTROLs;



typedef volatile struct {

	U32 ssmod_RESET                         : 1;// regAudioPLL_4[0];
	U32 ssmod_DISABLE_SSCG           : 1;// regAudioPLL_4[1];
	U32 ssmod_SEL_EXTWAVE            : 1;// regAudioPLL_4[2];
	U32 ssmod_DOWNSPREAD             : 1;// regAudioPLL_4[3];
	U32 ssmod_RESETPTR                    : 1;// regAudioPLL_4[4];
	U32 ssmod_DIVVAL                      : 6;// regAudioPLL_4[10:5];
	U32 ssmod_SPREAD                       : 5;// regAudioPLL_4[15:11];


	//pad mux
	U32 sd_data_4bit_en                            : 1;// regAudioPLL_4[16];
	U32 i2c_hw_en                                      : 1;// regAudioPLL_4[17];
	U32 dmic_data_in_0_sel                       : 2;// regAudioPLL_4[19:18];
	U32 dmic_data_in_1_sel                       : 2;// regAudioPLL_4[21:20];
	U32 dmic_data_in_2_sel                       : 2;// regAudioPLL_4[23:22];
	U32 dmic_data_in_3_sel                       : 2;// regAudioPLL_4[25:24];
	U32 spdif_out_en                                   : 1;// regAudioPLL_4[26];
	U32 sdram_en                                         : 1;// regAudioPLL_4[27];
	U32 crystal_12m                                     : 1;// regAudioPLL_4[28];

		
} MISC_SSMOD_CONTROLs;



typedef volatile struct {

U32	reserve             : 1; //	
U32	regAdcCtl_adcen		: 1; //power down/PD, 1 : off
U32	regAdcCtl_start		: 1; //soc, 1 : start 
U32	reserve1            : 1; //			
U32	regAdcCtl_clkDiv    : 10;//			
U32	regAdcCtl_addr	    : 4; //when start is high, it should be changed last			

U32	regAdcCtl_diff		: 1; //differetial input ; 0:single end    1:differential
U32	regAdcCtl_df	    : 1; //data format, 0:unsigned or 1:signed			
U32 regAdc_int_en		: 1; //    		
U32	adc_eoc	            : 1; //	
U32 adc_int_staus		: 1; //cleaed when reading adc data
	
} MISC_ADC_CONTROLs;


/*-----------------------------------------------------------------------------------------------------*/
/*
 * 	SPI
 * 
 */
#define	BASE_ADDR_SPI		0x10300000
#define	BASE_ADDR_SPI_TEST	0x10f00000

//-------------------------------------------------------------------------------------------
#define	REG_SPI_CONTROL	REG( BASE_ADDR_SPI + 0 )
typedef volatile struct{
	U32	reset		: 1;		//-	1 reset, 0 normal
	U32	slave		: 1;		//slave=1, 0 master
	U32 enable		: 1;		//enable=1
#ifdef OPTEK_SOC2_VERSION
	U32 txFifoRst	: 1;
	U32 rxFifoRst	: 1;
#endif
} SPI_CONTROLs;

#define	bSPI_RESET			(*(SPI_CONTROLs *)&REG_SPI_CONTROL).reset
#define	bSPI_SLAVE_MODE		(*(SPI_CONTROLs *)&REG_SPI_CONTROL).slave
#define	bSPI_ENABLE			(*(SPI_CONTROLs *)&REG_SPI_CONTROL).enable

//-------------------------------------------------------------------------------------------
#define	REG_SPI_FORMAT	REG( BASE_ADDR_SPI + 4)
typedef volatile struct{
	U32	cpha		: 1;	//0=sck low in idle,1=sck high
	U32 cpol		: 1;	//0=data valid at sck high,1=valid at low
	U32 div			: 4;	//clkDivisor=2,4,8,16,32,64,128,256,512,1024,2048,4096
	U32 bits		: 4;	//7=8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,
	U32 manual		: 1;	//0=auto, 1=manual
	U32 csvalue		: 1;	// 1 -> ----, 0->  ____
	U32 csinactivev : 1;	// 1 -> ----, 0->  ____
	U32 autocsActive :1;	//0 -> ----|____|---- , 1 -> ____|----|____
	U32 delay		: 3;	//inactive cs hold time
	U32 cssel		: 2;	
} SPI_FORMATs;

#define	bSPI_CPHA				(*(SPI_FORMATs *)&REG_SPI_FORMAT).cpha
#define	bSPI_CPOL				(*(SPI_FORMATs *)&REG_SPI_FORMAT).cpol
#define	bSPI_DIVISOR			(*(SPI_FORMATs *)&REG_SPI_FORMAT).div
#define	bSPI_BITS				(*(SPI_FORMATs *)&REG_SPI_FORMAT).bits
#define	bSPI_MANUAL				(*(SPI_FORMATs *)&REG_SPI_FORMAT).manual
#define	bSPI_MLCS_VALUE			(*(SPI_FORMATs *)&REG_SPI_FORMAT).csvalue
#define	bSPI_MLCS_INACTIVE		(*(SPI_FORMATs *)&REG_SPI_FORMAT).csinactivev
#define	bSPI_AUTOCS_ACTIVE		(*(SPI_FORMATs *)&REG_SPI_FORMAT).autocsActive
#define	bSPI_DELAY				(*(SPI_FORMATs *)&REG_SPI_FORMAT).delay
#define	bSPI_CS_SEL				(*(SPI_FORMATs *)&REG_SPI_FORMAT).cssel

//-------------------------------------------------------------------------------------------
#define	REG_SPI_INT_ENABLE	REG( BASE_ADDR_SPI + 8)
#define	REG_SPI_INT_STATUS	REG( BASE_ADDR_SPI + 12)
typedef volatile struct{
	U32	txBufEmpty			: 1;	//txBufEmpty
#ifdef OPTEK_SOC2_VERSION
	U32 txBufHalfEmpty		: 1 ;	//txBufHalfEmpty
	U32 txBufFull			: 1;	// txBufFull
	U32 txBufUnderrun		: 1;	//txBufUnderrun

	U32 rxBufEmpty			: 1;	//RXBufFull
	U32 rxBufNotEmpty		: 1;	//rxBufNotEmpty
	U32 rxBufFull			: 1;
	U32 rxBufHalfFull		: 1;	//rxBufHalfFull,
	U32 rxOverrun			: 1;	//busy
	U32 idle				: 1;	//idle
#else
	U32 rxBufFull			: 1;	//txBufFull
	U32 txBufUnderrun		: 1;	//txBufUnderrun
	U32 rxBufOverrun		: 1;	//rxBufOverrun,slave only
	U32 busy				: 1;	//busy
	U32 idle				: 1;	//idle
#endif
} SPI_INTs;

#define	bSPI_INT_TX				(*(SPI_INTs *)&REG_SPI_INT_ENABLE).txBufEmpty
#define	bSPI_INT_RX				(*(SPI_INTs *)&REG_SPI_INT_ENABLE).rxBufFull
#define	bSPI_INT_UNDER_RUN		(*(SPI_INTs *)&REG_SPI_INT_ENABLE).txBufUnderrun
#define	bSPI_INT_OVER_RUN		(*(SPI_INTs *)&REG_SPI_INT_ENABLE).rxBufOverrun
#define	bSPI_INT_BUSY			(*(SPI_INTs *)&REG_SPI_INT_ENABLE).busy
#define	bSPI_INT_IDLE			(*(SPI_INTs *)&REG_SPI_INT_ENABLE).idle

//-------------------------------------------------------------------------------------------
#define	REG_SPI_TX_DATA	REG( BASE_ADDR_SPI + 16 )
#define	REG_SPI_RX_DATA	REG( BASE_ADDR_SPI + 20 )
#define	REG_SPI_VERSION	REG( BASE_ADDR_SPI + 24 )

typedef volatile struct {
	SPI_CONTROLs	control;
	SPI_FORMATs	format;
	SPI_INTs	int_enable;
	SPI_INTs	int_status;
	U32	tx;
	U32	rx;
	U32	version;
} SPI_REGISTER;


/*-----------------------------------------------------------------------------------------------------*/
/*
 * 	I2S
 * 
 *------------------------------------------------------------------------------------*/
#define BASE_ADDR_I2S 		0x14000000

#define I2S_RESET_REG		REG(BASE_ADDR_I2S + 0)

//-------------------------------------------------------------------------------------------
#define I2S0_CONTR_REG		REG(BASE_ADDR_I2S + 4)
#define I2S1_CONTR_REG		REG(BASE_ADDR_I2S + 20)
typedef volatile struct {
	U32 modesel				:1;	// 0 is slave , 1 is master
	U32 txenable			:1;	//assume:no dynamic change of tx/rx enable
	U32 rxenable			:1;	//config is done on init time
	U32 cd_cdromenable		:1;	//Cd/Cdrom rx enable
	U32 cd_cdrom_sel		:1;	//Select cd or cdrom
	U32 cdrom_discb_enable	:1;	//CD Rom discramble enable
	U32 cdrommode			:2;	//Cdrom Mode
	U32 resync				:1;	//ReSync
} I2S_CONTROLs;

//-------------------------------------------------------------------------------------------
#define I2S0_FFORMAT_REG	REG(BASE_ADDR_I2S + 8)
#define I2S1_FFORMAT_REG	REG(BASE_ADDR_I2S + 24)

typedef volatile struct {
	U32 format		:2;		//2bits (00 is format i2s, 01 is format Ljustify, 10 is format Rjustify)
	U32 lr			:1;		//L/R switch
	U32 wordsz		:1;		//0 is word size is 16 bits, 1 word size is 24 bits
	U32 bckdiv		:8;		//divider from mclk ,only master mode)
	U32 lrckdiv		:12;		//divider from mclk,only master mode
	U32 dvalid		:8;		//how many bcks when data is valid, only for Right Justify mode	
} I2S_FFORMATs;

//-------------------------------------------------------------------------------------------
#define I2S_EF_CRC_REG REG(BASE_ADDR_I2S + 36)

typedef volatile struct {
		U32 ef_cnt	:12;	//tx threshold full enable
		U32 crc		:1;		//tx full enable
}I2S_CRCs;

#define I2S_AUDIO_EFFECT_REG REG(BASE_ADDR_I2S + 40)

typedef volatile struct {
		U32 SP_En			:1;		//spacial effect enable
		U32 P_Prescale		:1;		//spacial prescale
		U32 P_Width			:1;		//spacial width
		U32 Bass_En			:1;		//bass enable
		U32 EQ_En			:1;		//eq enable
		U32 EQ_Gain_5		:5;		//band 5 (16kHz) gain
		U32 EQ_Gain_4		:5;		//band 4 (4kHz) gain
		U32 EQ_Gain_3		:5;		//band 3 (1kHz) gain
		U32 EQ_Gain_2		:5;		//band 2(250Hz)  gain
		U32 EQ_Gain_1		:5;		//band 1 (63Hz)gain
		U32 Reserved		:2;	//reserved
} I2S_EFFECTs;



//-------------------------------------------------------------------------------------------
#define I2S0_TX_DATA_REG	REG(BASE_ADDR_I2S + 128)
#define I2S1_TX_DATA_REG	REG(BASE_ADDR_I2S + 384)

#define I2S0_RX_DATA_REG	REG(BASE_ADDR_I2S + 256)
#define I2S1_RX_DATA_REG	REG(BASE_ADDR_I2S + 512)


/*--------------------------------------------------------------------------------------------*/
//MISC
/*--------------------------------------------------------------------------------------------*/

#define BASE_ADDR_MISC	0x10600000
#define MISC_CONFIG_REG REG(BASE_ADDR_MISC)
typedef volatile struct {
	U32	mclksel		: 2;	// set 2bit( 01 is internal PLL,	10 is external PLL)
} MISC_CLKSELs;

#define bI2SMISC_CLKSEL	(*(MISC_CLKSELs*)&MISC_CONFIG_REG).mclksel

#define MISC_VERSION_REG REG(BASE_ADDR_MISC + 0x04)


/*------------------------------------------------------------------------------
*
*	I2C
*/
#define I2C0_BASE_ADDR			0x10700000
#define I2C1_BASE_ADDR			0x10E00000

#define I2C0_RESET_REG			REG(I2C0_BASE_ADDR)
typedef volatile struct{
		U32 reset		: 1;
		U32 txfiforst	: 1;
		U32 rxfiforst	: 1;
} I2C_RESETs;

//------------------------------------------------------------------
#define I2C0_CONTR_REG			REG(I2C0_BASE_ADDR + 4)
typedef volatile struct{
		U32 enable		: 1;
		U32 mode		: 1;
		U32 clkstretch	: 1;
		U32 clkdiv		: 16;
} I2C_CONTs;


//---------------------------------------------------------------------
#define I2C0_FFORMAT_REG		REG(I2C0_BASE_ADDR + 8)
typedef volatile struct {
		U32	i2c_addr		: 7;
		U32 framtype		: 2;
		U32 sndBusRecovery	: 1;
} I2C_FFORMATs;

#define bI2C_FFRM_I2CADDR		(*(I2C_FFORMATs *)&I2C0_FFORMAT_REG).i2c_addr
#define bI2C_FFRM_MFRMTYPE		(*(I2C_FFORMATs *)&I2C0_FFORMAT_REG).framtype

//--------------------------------------------------------
#define I2C0_FSIZE_REG			REG(I2C0_BASE_ADDR + 12)
typedef volatile struct {
		U32	txBytes : 10;
		U32 rxBytes : 10;
} I2C_FSIZEs;

#define bI2C_FSIZES_TXBYTE			(*(I2C_FSIZEs *)&I2C0_FSIZE_REG).txBytes
#define bI2C_FSIZES_RXBYTE			(*(I2C_FSIZEs *)&I2C0_FSIZE_REG).rxBytes

//--------------------------------------------------------
#define I2C0_INT_ENABLE_REG	REG(I2C0_BASE_ADDR + 16)
typedef volatile struct {
		U32	txFifoEmpty		: 1;
		U32 txFifoHEmpty	: 1;
		U32 txFifoUnderrun	: 1;
		U32 txFifoFull		: 1;
		
		U32 rxFifoFull		: 1;
		U32 rxFifoHFull		: 1;
		U32 rxFifoOverrun	: 1;
		U32 rxFifoEmpty		: 1;
		
		U32 wtAddrMatch		: 1;
		U32 rdAddrMatch		: 1;
		U32 rptStart		: 1;
		U32 frameEnd		: 1;

		U32 errBusStick		: 1;
		U32 errNack			: 1;
		U32 errBusFrame		: 1;
		U32 errClkStretch	: 1;
} I2C_INT_ENABLE;

//-------------------------------------------------------------
#define I2C0_INT_STATUS_REG	REG(I2C0_BASE_ADDR + 20)
typedef volatile struct {
		U32	txFifoEmpty		: 1;
		U32 txFifoHEmpty	: 1;
		U32 txFifoUnderrun	: 1;
		U32 txFifoFull		: 1;
		
		U32 rxFifoFull		: 1;
		U32 rxFifoHFull		: 1;
		U32 rxFifoOverrun	: 1;
		U32 rxFifoEmpty		: 1;
		
		U32 wtAddrMatch		: 1;
		U32 rdAddrMatch		: 1;
		U32 rptStart		: 1;
		U32 frameEnd		: 1;

		U32 errBusStick		: 1;
		U32 errNack			: 1;
		U32 errBusFrame		: 1;
		U32 errClkStretch	: 1;

		U32 busBusy			: 1;
		U32 clkStretched	: 1;
} I2C_INT_STATUS;


//-------------------------------------------------------------
#define I2C0_TX_DATA_REG		REG(I2C0_BASE_ADDR + 24)
#define I2C0_RX_DATA_REG		REG(I2C0_BASE_ADDR + 28)
#define I2C0_VERSION_REG		REG(I2C0_BASE_ADDR + 32)


#define I2C1_RESET_REG			REG(I2C1_BASE_ADDR)
#define I2C1_CONTR_REG			REG(I2C1_BASE_ADDR + 4)
#define I2C1_FFORMAT_REG		REG(I2C1_BASE_ADDR + 8)
#define I2C1_FSIZE_REG			REG(I2C1_BASE_ADDR + 12)
#define I2C1_INT_ENABLE_REG		REG(I2C1_BASE_ADDR + 16)
#define I2C1_INT_STATUS_REG		REG(I2C1_BASE_ADDR + 20)
#define I2C1_TX_DATA_REG		REG(I2C1_BASE_ADDR + 24)
#define I2C1_RX_DATA_REG		REG(I2C1_BASE_ADDR + 28)
#define I2C1_VERSION_REG		REG(I2C1_BASE_ADDR + 32)


/*-----------------------------------------------------------------------------------------------------*/
/*
 * 	RTC 
 * 
 */

#define RTC_BASE_ADDR			0x10800000

//------------------------------------------------------------------------------------
#define REG_RTC_BATT_MODE		REG(RTC_BASE_ADDR)

//------------------------------------------------------------------------------------
#define REG_RTC_CONTROL			REG(RTC_BASE_ADDR + 4)

typedef volatile struct {
	U32 enable			: 1;		//Control RTC enable
	U32 preset_ena		: 1;		//Preset permitted (read only)
	U32 second_int_ena	: 1;		//Second int enable
	U32 alm0_int_ena	: 1;		//Alarm0 int enable
	U32 alm1_int_ena	: 1;		//Alarm1 int enable
	U32 second_intstat	: 1;		//int status (write 1 clear int)
	U32 alm0_intstat	: 1;		//(write 1 clear)
	U32 alm1_intstat	: 1;		//(write 1 clear)
} RTC_CONTROLs;

#define bRTC_CTL_ENA			(*(RTC_CONTROLs *)&REG_RTC_CONTROL).enable
#define bRTC_CTL_PRESETENA		(*(RTC_CONTROLs *)&REG_RTC_CONTROL).preset_ena
#define bRTC_CTL_SECINTENA		(*(RTC_CONTROLs *)&REG_RTC_CONTROL).second_int_ena
#define bRTC_CTL_ALM0INTENA		(*(RTC_CONTROLs *)&REG_RTC_CONTROL).alm0_int_ena
#define bRTC_CTL_ALM1INTENA		(*(RTC_CONTROLs *)&REG_RTC_CONTROL).alm1_int_ena
#define bRTC_CTL_SECINTSTA 		(*(RTC_CONTROLs *)&REG_RTC_CONTROL).second_intstat
#define bRTC_CTL_ALM0INTSTA 	(*(RTC_CONTROLs *)&REG_RTC_CONTROL).alm0_intstat
#define bRTC_CTL_ALM1INTSTA 	(*(RTC_CONTROLs *)&REG_RTC_CONTROL).alm1_intstat

//---------------------------------------------------------------------------------
#define REG_RTC_TIMER				REG(RTC_BASE_ADDR + 8)
#define REG_RTC_TIMER_RD			REG(RTC_BASE_ADDR + 24)
#define REG_RTC_TIMER_WT			REG(RTC_BASE_ADDR + 8)

typedef volatile struct {
	U32 daily_times : 17;			//Every day of timer(bit0~bit16)
	U32 days		: 15;			//all days (bit17~bit31)	
} RTC_TIMERs;

#define bRTC_TIMER_DAILY_TIMES		(*(RTC_TIMERs *)&REG_RTC_TIMER).daily_times
#define bRTC_TIMER_DAYS				(*(RTC_TIMERs *)&REG_RTC_TIMER).days

//---------------------------------------------------------------------------------
#define REG_RTC_ALARM0				REG(RTC_BASE_ADDR + 12)
#define REG_RTC_ALARM1				REG(RTC_BASE_ADDR + 16)

typedef volatile struct {
	U32 daily : 17;				//Set 0 is every day alarm(bit0~bit16)
	U32 days : 15;				//If daily != 0, enable normal alarm(daily+days)
} RTC_ALARMs;

#define bRTC_ALARM0_DAILY			(*(RTC_ALARMs *)&REG_RTC_ALARM0).daily
#define bRTC_ALARM0_DAYS			(*(RTC_ALARMs *)&REG_RTC_ALARM0).days

#define bRTC_ALARM1_DAILY			(*(RTC_ALARMs *)&REG_RTC_ALARM1).daily
#define bRTC_ALARM1_DAYS			(*(RTC_ALARMs *)&REG_RTC_ALARM1).days

//---------------------------------------------------------------------------------
#define REG_RTC_VERSION			REG(RTC_BASE_ADDR + 20)


/*-----------------------------------------------------------------------------------------------------*/
/*
 * 	PWM
 * 
 *------------------------------------------------------------------------------------*/
#define PWM_BASE_ADDR			0x10900000
#define REG_PWM_CTL				REG(PWM_BASE_ADDR)
#define REG_PWM_CLK				REG(PWM_BASE_ADDR + 4)
#define REG_PWM_DUTY			REG(PWM_BASE_ADDR + 8)
#define REG_PWM_VERSION			REG(PWM_BASE_ADDR + 12)

#define PWM1_BASE_ADDR			0x10f00000
#define REG_PWM1_CTL			REG(PWM1_BASE_ADDR)
#define REG_PWM1_CLK			REG(PWM1_BASE_ADDR + 4)
#define REG_PWM1_DUTY			REG(PWM1_BASE_ADDR + 8)
#define REG_PWM1_VERSION		REG(PWM1_BASE_ADDR + 12)

#define	PWM3_BASE_ADDR			0x18200000
#define REG_PWM2_CTL			REG(PWM3_BASE_ADDR)
#define REG_PWM2_CLK			REG(PWM3_BASE_ADDR + 4)
#define REG_PWM2_DUTY			REG(PWM3_BASE_ADDR + 8)
#define REG_PWM2_VERSION		REG(PWM3_BASE_ADDR + 12)

#define	BATT_BASE_ADDR			0x18300000
#define REG_PWM3_CTL			REG(BATT_BASE_ADDR)
#define REG_PWM3_CLK			REG(BATT_BASE_ADDR + 4)
#define REG_PWM3_DUTY			REG(BATT_BASE_ADDR + 8)
#define REG_PWM3_VERSION		REG(BATT_BASE_ADDR + 12)





/*-----------------------------------------------------------------------------------------------------*/
/*
 * 	ROTARY 
 * 
 *------------------------------------------------------------------------------------*/
#define ROTARY_BASE_ADDR			0x10A00000
#define REG_ROTARY_RESET			REG(ROTARY_BASE_ADDR)
#define REG_ROTARY_CTL				REG(ROTARY_BASE_ADDR + 4)
#define REG_ROTARY_CLK				REG(ROTARY_BASE_ADDR + 8)
#define REG_ROTARY_CNT				REG(ROTARY_BASE_ADDR + 12)
#define REG_ROTARY_VERSION			REG(ROTARY_BASE_ADDR + 16)


#define ROTARY1_BASE_ADDR			0x10D00000
#define REG_ROTARY1_RESET			REG(ROTARY1_BASE_ADDR)
#define REG_ROTARY1_CTL				REG(ROTARY1_BASE_ADDR + 4)
#define REG_ROTARY1_CLK				REG(ROTARY1_BASE_ADDR + 8)
#define REG_ROTARY1_CNT				REG(ROTARY1_BASE_ADDR + 12)
#define REG_ROTARY1_VERSION			REG(ROTARY1_BASE_ADDR + 16)
/*------------------------------------------------------------------------------------*/
/*
 * 	WATCH DOG
 * 
 *------------------------------------------------------------------------------------*/
#define WATDOG_BASE_ADDR		0x10B00000

#define REG_WATDOG_CTRL			REG(WATDOG_BASE_ADDR)
#define REG_WATDOG_UNLOCK		REG(WATDOG_BASE_ADDR + 4)
#define REG_WATDOG_RESET		REG(WATDOG_BASE_ADDR + 8)
#define REG_WATDOG_VERSION		REG(WATDOG_BASE_ADDR + 12)




/*------------------------------------------------------------------------------------*/
/*
 *  SPI Flash
 *
 *------------------------------------------------------------------------------------*/

#define ADDR_SPI_CMD                0x11FF0000
#define ADDR_SPI_DATA               0x58000000

#define ADDR_SPI_STATUS             REG8(ADDR_SPI_CMD + 0x0500)	//read status
#define ADDR_SPI_4_NO_FAST          REG8(ADDR_SPI_CMD + 0x0520)	//read status, set 4 bit interface, no fast read
#define ADDR_SPI_4_FAST             REG8(ADDR_SPI_CMD + 0x0530)	//read status, set 4 bit interface, fast read
#define ADDR_SPI_1_NO_FAST          REG8(ADDR_SPI_CMD + 0x0510)	//read status, set 1 bit interface, no fast read
#define ADDR_SPI_STATUS2            REG8(ADDR_SPI_CMD + 0x3500)	//read status2, only for Winbond
#define ADDR_SPI_WR_DISABLE         REG8(ADDR_SPI_CMD + 0x0400)	//write disable
#define ADDR_SPI_WR_ENABLE          REG8(ADDR_SPI_CMD + 0x0600)	//write enable
#define ADDR_SPI_WR_STATUS_1BYTE    REG8(ADDR_SPI_CMD + 0x0100)	//write status, one byte
#define ADDR_SPI_WR_STATUS_2BYTES   REG16(ADDR_SPI_CMD + 0x0110)//write status, two bytes for Winbond Q series
#define ADDR_SPI_JEDEC_ID           REG32(ADDR_SPI_CMD + 0x9F00)//read JEDEC ID
#define ADDR_SPI_UNIQUE_ID          REG64(ADDR_SPI_CMD + 0x4B00)//read UNIQUE ID
#define ADDR_SPI_MODE_BIT_RESET     REG32(ADDR_SPI_CMD + 0xFF00)//Mode bit reset
#define ADDR_SPI_HIGH_PERFOMANCE    REG32(ADDR_SPI_CMD + 0xA300)//High perfomance
#define ADDR_SPI_POWER_DOWN         REG8(ADDR_SPI_CMD + 0xB900)	//Deep power down
#define ADDR_SPI_POWER_ON           REG8(ADDR_SPI_CMD + 0xAB00)	//Relase power down
#define ADDR_SPI_BLOCK_ERASE        REG32(ADDR_SPI_CMD + 0xD800)//Block Erase
#define ADDR_SPI_SECTOR_ERASE       REG32(ADDR_SPI_CMD + 0x2000)//SECTOR Erase

#define ADDR_SPI_PAGE_PROGRAM       REG32(ADDR_SPI_CMD + 0x0200)//page program

//#ifdef SPI_FLASH_WINBOND
#define ADDR_SPI_FAST_PAGE_PROGRAM  REG32(ADDR_SPI_CMD + 0x3200)//page program
//#endif

//#ifdef SPI_FLASH_MX
//#define ADDR_SPI_FAST_PAGE_PROGRAM  REG32(ADDR_SPI_CMD + 0x3800)//page program
//#endif

#define ADDR_SPI_NORMAL_READ        REG8(ADDR_SPI_CMD + 0x0300)	//normal read
#define ADDR_SPI_CHIP_ERASE         REG8(ADDR_SPI_CMD + 0xc700)	//chip erase



//OTG
#define	USB_BASE_ADDR			0x16000000


#define	USB_OTG_REG_OFFSET		0x1bc
#define	USB_HOST_REG_OFFSET		0
#define	USB_DEVICE_REG_OFFSET	0

#define	USB_OTG_BASE_ADDR		(USB_BASE_ADDR + USB_OTG_REG_OFFSET)
#define	USB_HOST_BASE_ADDR		(USB_BASE_ADDR + USB_HOST_REG_OFFSET)
#define	USB_DEVICE_BASE_ADDR	(USB_BASE_ADDR + USB_DEVICE_REG_OFFSET)


#define	OTG_CTL_REG_ADDR		(USB_BASE_ADDR + 0x400)

#define	OTG_DMA_BASE_ADDR		(USB_BASE_ADDR + 0x800)
#define	OTG_DMA_ENDP1_ADDR		OTG_DMA_BASE_ADDR
#define	OTG_DMA_ENDP2_ADDR		(OTG_DMA_BASE_ADDR + 0x100)
#define	OTG_DMA_ENDP3_ADDR		(OTG_DMA_BASE_ADDR + 0x200)

#if 0
//enhanced ctrl reg
#define	ENH_CTRL_RESET			(1<<0)
#define	ENH_CTRL_ENA_CONTROLLER	(1<<1)
#define	ENH_CTRL_ENA_PHY		(1<<2)
#define	ENH_CTRL_RESET_PHY		(1<<3)
#define	ENH_CTRL_DIS_HSPEED		(1<<4)


#define	ENH_CTRL_INT_ENA_MASK	(7<<5)
#define	ENH_CTRL_INT_STAT_MASK	(7<<8)

#define	ENH_CTRL_INT_ENA_SHIFT	(5)
#define	ENH_CTRL_INT_STAT_SHIFT	(8)

#define	ENH_CTRL_INT_USB		(1<<0)
#define	ENH_CTRL_INT_FIFO		(1<<1)
#define	ENH_CTRL_INT_WKUP		(1<<2)
#else
//enhanced ctrl reg
#define	ENH_CTRL_RESET			(1<<0)
#define	ENH_CTRL_PHY_CLK_ENA	(1<<1)
#define	ENH_CTRL_PHY_REG_ENA	(1<<2)
#define	ENH_CTRL_PHY_PLL_ENA	(1<<3)
#define	ENH_CTRL_DIS_HSPEED		(1<<4)

#define	ENH_CTRL_INT_ENA_MASK	(7<<5)
#define	ENH_CTRL_INT_STAT_MASK	(7<<8)

#define	ENH_CTRL_INT_ENA_SHIFT	(5)
#define	ENH_CTRL_INT_STAT_SHIFT	(8)

#define	ENH_CTRL_INT_USB		(1<<0)
#define	ENH_CTRL_INT_FIFO		(1<<1)
#define	ENH_CTRL_INT_WKUP		(1<<2)
#define	ENH_CTRL_PHY_NO_SUSPEND	(1<<26)

#endif

/*-----------------------------------------------------------------------------------------------------*/
/*
 * 	IR
 * 
 *------------------------------------------------------------------------------------*/
#define IR_BASE_ADDR			0x10E00000
#define REG_IR_CTL				REG(IR_BASE_ADDR)					/*bit5-bit2 min, bit 1 eco, bit 0 en*/
#define REG_IR_INTSTAT			REG(IR_BASE_ADDR + 4)				/*bit 1 eco release, bit 0 rx not Empty*/
#define REG_IR_RXFIFO			REG(IR_BASE_ADDR + 8)				/*4 byte contect, bit 7 ir H/L, bit [6:0] lev width based on 32k (0.0305ms)*/


/*
#define REG_IR_CTL				REG(IR_BASE_ADDR)
#define REG_IR_CLKDIV			REG(IR_BASE_ADDR + 4)
#define REG_IR_SIGMINCNT		REG(IR_BASE_ADDR + 8)
#define REG_IR_SIGMAXCNT		REG(IR_BASE_ADDR + 12)
#define REG_IR_RXFIFO			REG(IR_BASE_ADDR + 16)
#define REG_IR_INTENA			REG(IR_BASE_ADDR + 20)
#define REG_IR_INTSTAT			REG(IR_BASE_ADDR + 24)
#define REG_IR_STARTMINCNT		REG(IR_BASE_ADDR + 28)
#define REG_IR_STARTMAXCNT		REG(IR_BASE_ADDR + 32)
#define REG_IR_VERSION			REG(IR_BASE_ADDR + 36)
*/

typedef volatile struct{
	U32	FifoNotEmpty	: 1;	
	U32 FifoHalfFull	: 1;	
	U32 FifoFull		: 1;	
	U32 FifoOverRun		: 1;	
	
	U32 CntOverRun		: 1;
	U32 CntUnderRun		: 1;	
	
	U32 FrameErr 		: 1;	
	U32 FrameStart		: 1 ;
	U32 FrameEnd		: 1 ;
} IR_INTS;

typedef volatile struct{
	U32	FifoNotEmpty	: 1;
	U32 FifoHalfFull	: 1;
	U32 FifoFull		: 1;
	U32 FifoOverRun		: 1;
	
	U32 CntOverRun		: 1;
	U32 CntUnderRun		: 1;	
	
	U32 FrameErr 		: 1;	
	U32 FrameStart		: 1;
	U32 FrameEnd		: 1;
} IR_INT_STATUS;


#if 0
//OLD
#define	ROM_MP3_DECODER_ADDR        0x5401d7f4
#define	ROM_MP3_ENCODER_ADDR        0x54029a08
#define	ROM_WMA_DECODER_ADDR        0x5402f624
#define	ROM_AAC_DECOER_ADDR         0x5403d290
#else
//NEW
#define	ROM_MP3_DECODER_ADDR        0x5405898c
#define	ROM_MP3_ENCODER_ADDR        0x5406e390

#define	ROM_DOBLY_AC3_DECODER_ADDR  0x54077408

#define	ROM_FLAC_DECODER_ADDR       0x5407e1c0

#define	ROM_MSBC_DECODER_ADDR       0x5407ff90
#define	ROM_MSBC_ENCODER_ADDR       0x54081e38
#define	ROM_SBC_DECODER_ADDR        0x54083158
#define	ROM_SBC_ENCODER_ADDR        0x54085750

#define	ROM_DAB_PLUS_DECODER_ADDR   0x54099814

#define	ROM_DOBLY_PLII_DECODER_ADDR 0x540a87d0

#define	ROM_AAC_DECODER_ADDR        0x540addf4
#endif


#endif //_REGMAP_H