////////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2009 Optek.
//
//! \file app_uart.c
//! \brief
//! \version 0.1
//! \date Mar, 2005
//!
//! \see ThreadX User Guide
////////////////////////////////////////////////////////////////////////////////

#include "os_config.h"

#include "c_def.h"
#include "debug.h"
#include "oem.h"

#include "regmap.h"

#include "hw_uart.h"

#include "string.h"
#include "printf.h"
#include "fifo.h"
#include "printf_fifo.h"
#include "app_uart.h"
#include "flash_boot.h"

#include "hw_dma.h"
#include "interrupt.h"

#define IMPROVE_EFFICIENCY_ENABLE

// set this to '1' if you want to make direct ISR calls and bypass OS
//#define ISR_DIRECT        0
#define ISR_DIRECT        1


#define TX_FIFO_EMPTY               0
#define TX_FIFO_ONE_QUARTER         1
#define TX_FIFO_ONE_HALF            2
#define TX_FIFO_THREE_QUARTERS      3
#define TX_FIFO_SEVEN_EIGHT         4

#define RX_FIFO_NOT_EMPTY           0
#define RX_FIFO_ONE_QUARTER         1
#define RX_FIFO_ONE_HALF            2
#define RX_FIFO_THREE_QUARTERS      3
#define RX_FIFO_SEVEN_EIGHT         4


#if 1//def UART0_ENABLE
U8 *Uart0RcvPtr;
U32 Uart0RcvLen;

#if 0//def UART0_RX_DMA
FIFO Uart0_DMARxFifo;
U8 uart0_dmafifo_Rxbuf[2048+512];
static U8 hci_uart_rx_state;
U32 uart0_rx_dma_buf [UART0_RX_DMA_BUF_SIZE];
#else
//As we don't use the uart for bt now, we should reduce buffer size.
FIFO Uart0_DMARxFifo;
U8 uart0_dmafifo_Rxbuf[512]; //??
static U8 hci_uart_rx_state; //??
//U32 uart0_rx_dma_buf [UART0_RX_DMA_BUF_SIZE]; //??
U8 uart0_rx_dma_buf [UART0_RX_DMA_BUF_SIZE]; //??
#endif

#endif //UART0_ENABLE


#if 1//def UART1_ENABLE
U8 uart1_receive_enable;
FIFO Uart1RcvFifo;
FIFO *pUart1RcvFifo = (FIFO *)&Uart1RcvFifo;
//U8 uart1_fifo_buf[1024];
U8 uart1_fifo_buf[576];
#endif


extern PRINTF_FIFO *ptxfifo;
extern PRINTF_FIFO *prxfifo;
extern FIFO printf_fifo;

void app_uart_data_init(int num)
{	
	printf_init();
	
#ifdef SCANF_ENABLE
	scanf_init();
#endif
}



#if (defined UART0_ENABLE && defined UART0_INT_ENABLE)
void Uart0_IsrHandler(void)
{
	U8 num = en_UART0;
	volatile UART_REGISTERS *pregs	=	(UART_REGISTERS *)UART0_BASE_ADDR;
	volatile U32 reg32 = pregs->status;

	U32 tmp;
	U32 dlen;
	int	ret;
	U8 send_char;

#ifdef UART0_TX_ENABLE
	if( reg32 & INT_TX_BUF_HALF_EMPTY )
	{
		while( ptxfifo->size && ( !(pregs->status & STAT_TX_BUF_FULL) ) )
		{
			U8 *pBuf = (U8*)&tmp;
			ret = FiFo_iGet( ptxfifo, pBuf, 1 );
			if (ret)
			{
				pregs->txBuf = tmp;
			}
		}

		if( ! ptxfifo->size )
		{
			pregs->intEnable &= ~INT_TX_BUF_HALF_EMPTY;
		}
	}
#endif //UART0_TX_ENABLE

#ifdef UART0_RX_ENABLE
	if( (reg32 & INT_RX_BUF_HALF_FULL) || (reg32 & INT_RX_BUF_NOT_EMPTY) )
	{
		while( pregs->status & STAT_RX_BUF_NOT_EMPTY )
		{
			tmp = pregs->rxBuf;
			
		#ifdef DSPEQ_TUNING_ENABLE
			app_nav_eq_tuning_data_receive(tmp);
		#endif
		}
	}
#endif

	if( reg32 & (INT_ERR | INT_RX_OVERRUN) )
	{
		DBG_assert(0);
	}
}
#endif //(defined UART0_ENABLE && defined UART0_INT_ENABLE)


#if (defined UART1_ENABLE && defined UART1_INT_ENABLE)

void Uart1_IsrHandler(void)
{
	U8 num = en_UART1;
	volatile UART_REGISTERS *pregs	=	(UART_REGISTERS *)UART1_BASE_ADDR;
	//volatile U32 reg32 = pregs->intStat;
	volatile U32 reg32 = pregs->status;
	U32 tmp;
	int ret;

	DBG_assert( num < en_NUM_MAX );

#ifdef UART1_RX_ENABLE
	if( (reg32 & INT_RX_BUF_HALF_FULL) || (reg32 & INT_RX_BUF_NOT_EMPTY) )
	{
		while( pregs->status & STAT_RX_BUF_NOT_EMPTY )
		{
			tmp = pregs->rxBuf;
			
		#ifdef DSPEQ_TUNING_ENABLE
			app_nav_eq_tuning_data_receive(tmp);
		#endif		
		}
	}
#endif

	if( reg32 & (INT_ERR | INT_RX_OVERRUN) )
	{
		DBG_assert(0);
	}
}

#endif //(defined UART1_ENABLE && defined UART1_INT_ENABLE)


#if (defined UART2_ENABLE && defined UART2_INT_ENABLE)

#ifdef UART_PRINTF_FIFO_ENABLE
U32 dlen; //for missing more uart's datas
#endif

void Uart2_IsrHandler(void)
{
	U8 num = en_UART2;
	volatile UART_REGISTERS *pregs	=	(UART_REGISTERS *)UART2_BASE_ADDR;
	volatile U32 reg32 = pregs->status;

	U32 tmp;
#ifndef UART_PRINTF_FIFO_ENABLE
	U32 dlen;
#endif
	int	ret;
	U8 send_char;

	DBG_assert( num < en_NUM_MAX );

#ifdef UART2_USED_FOR_UI_DEBUG

#ifdef UART_TX_FIFO_ENABLE

#ifndef UART_PRINTF_FIFO_ENABLE
	{
		if( reg32 & INT_TX_BUF_HALF_EMPTY )
		{
			//DBG_Assert( !(!(reg32 & pregs->intEnable) ) );
			//DBG_Assert( !(!(reg32 & INT_TX_BUF_HALF_EMPTY) ) );

			while( ptxfifo->size && ( !(pregs->status & STAT_TX_BUF_FULL) ) )
			{
#ifndef IMPROVE_EFFICIENCY_ENABLE
				ret = fifo_iget( ptxfifo, (U8*)&tmp, 1 );
#else
				U8 *pBuf = (U8*)&tmp;
				ret = FiFo_iGet( ptxfifo, pBuf, 1 );
#endif
				//DBG_Assert( ret == 1 );
				if (ret)
				{
					pregs->txBuf	=	tmp;
				}
			}

#if 1
			if( ! ptxfifo->size )
			{
				pregs->intEnable	&=	~INT_TX_BUF_HALF_EMPTY;
				//pregs->intEnable	|=	INT_TX_BUF_FULL;
				
#ifdef UART_TX_EVENT_FIFO_EMPTY_ENABLE
				UART_TX_EVENT_FIFO_EMPTY_iSET;
#endif
			}
#endif
		}
	}
#else
	{
		if( reg32 & INT_TX_BUF_HALF_EMPTY )
		{	
			DBG_assert( (reg32 & pregs->intEnable) & INT_TX_BUF_HALF_EMPTY );

			//dlen = fifo_get_fifo_data_len (&printf_fifo);
			dlen = (printf_fifo.wLen - printf_fifo.rLen);
			
			while( dlen  && ( !(pregs->status & STAT_TX_BUF_FULL) ) )
			{
#if 1
				fifo_get_data(&printf_fifo, &send_char, 1);
#else
				fifo_get_data_one_byte(&printf_fifo, &send_char);
#endif
				pregs->txBuf = send_char;
				dlen--;
			}

			//if( dlen == 0 )
			{
				pregs->intEnable &= ~INT_TX_BUF_HALF_EMPTY;
			}

#ifdef UART_TX_EVENT_FIFO_EMPTY_ENABLE
			UART_TX_EVENT_FIFO_EMPTY_iSET;
#endif
		}
	}
#endif //UART_PRINTF_FIFO_ENABLE

#else
	{
		if( reg32 & INT_TX_BUF_HALF_EMPTY )
		//if( !(reg32 & STAT_TX_BUF_FULL) )
		{
			//DBG_Assert( !(!(reg32 & pregs->intEnable) ) );
			//DBG_Assert( !(!(reg32 & STAT_TX_BUF_FULL) ) );

			//if( ( ptxfifo->size ) )
			while( ( ptxfifo->size ) && ( !(pregs->status & STAT_TX_BUF_FULL) ) )
			{
				ret	=	fifo_iget( ptxfifo, (U8*)&tmp, 1 );
				//DBG_Assert( ret == 1 );
				if (ret)
				{
					pregs->txBuf	=	tmp;
				}
			}
	
#if 0
			if( ! ptxfifo->size )
			{
				//pregs->intEnable	&=	~INT_TX_BUF_EMPTY;
				pregs->intEnable	&=	~INT_TX_BUF_FULL;
			}
#endif
		}
	}
#endif //UART_TX_FIFO_ENABLE

#endif //(defined UART2_ENABLE && defined UART2_INT_ENABLE)

#ifdef UART2_RX_ENABLE
	if( (reg32 & INT_RX_BUF_HALF_FULL) || (reg32 & INT_RX_BUF_NOT_EMPTY) )
	{
		while( pregs->status & STAT_RX_BUF_NOT_EMPTY )
		{
			tmp =	pregs->rxBuf;
			app_uart1_receive(tmp);
		}
	}
#endif

	if( reg32 & (INT_ERR | INT_RX_OVERRUN) )
	{
		DBG_assert(0);
	}
}
#endif //UART2_ENABLE

void app_uart_test(void)
{
}

void app_uart_fifo_test(void)
{
}

void UartDbg_RxInt_Disable(void)
{
}

void UartDbg_RxInt_Enable(void)
{
}


void app_uart0_init(void)
{
#ifdef UART0_ENABLE
	Uart0RcvLen = 0;

#if 1//def BTDM_CONTROLLER_ONLY
	app_uart_data_init(en_UART0);

	//Setup hardware
	uart_init( en_UART0 );

	uart_open( en_UART0 );
#endif //BTDM_CONTROLLER_ONLY

#endif //UART0_ENABLE


#if 1//def UART0_RX_DMA
		U32 *pDmaSource;

		hci_uart_rx_state = HCI_UART_STATE_RX_TYPE;
		fifo_init (&Uart0_DMARxFifo, uart0_dmafifo_Rxbuf, sizeof(uart0_dmafifo_Rxbuf), TRUE);

#ifdef BTDM_CONTROLLER_ONLY
		//init Uart0 rx DMA
		//pDmaSource = (U32 *)( UART0_BASE_ADDR + 24 );
		pDmaSource = (U32 *)(&REG_UART0_RX_DATA);
		DMA_Channel4_Init(uart0_rx_dma_buf, pDmaSource, 1, SOURCE_DMA_UART_0_RX);
#endif

#endif //UART0_RX_DMA
}

void app_uart1_init(void)
{
#ifdef UART1_ENABLE
	app_uart_data_init(en_UART1);

	//Setup hardware
	uart_init( en_UART1 );

	uart_open( en_UART1 );
#endif
}

void app_uart2_init(void)
{
#ifdef UART2_ENABLE
	app_uart_data_init(en_UART2);

	//Setup hardware
	uart_init( en_UART2 );

	uart_open( en_UART2 );
#endif
}

void app_uart_receive_enable(int num)
{

#ifdef UART1_USED_FOR_APP_UI
	if (num == en_UART1)
	{
		uart1_receive_enable = TRUE;
	}
#endif
}

void app_uart_receive_disable(int num)
{
#ifdef UART0_USED_FOR_APP_UI
	if (num == en_UART0)
	{
		uart_receive_enable = FALSE;
	}
#endif

#ifdef UART1_USED_FOR_APP_UI
	if (num == en_UART1)
	{

		uart1_receive_enable = FALSE;
	}
#endif
}


#if 1

#ifdef UART0_RX_DMA
U32 dma_rx_len=0;

void UART0_DMA_Rx_handle (void)  __attribute__ ((section (".internal_ram_1_text")));
void UART0_DMA_Rx_handle(void)
{
	U32 dlen,wlen,len;
	U8 *pRxbuf;
	static U8 hci_type=0;   
	static U16 count;

	pRxbuf = (U8 *)uart0_rx_dma_buf;
	

	switch(hci_uart_rx_state)
	{
		case HCI_UART_H4_SYNC_ERR:
		case HCI_UART_STATE_RX_TYPE:
			hci_uart_rx_state = HCI_UART_STATE_RX_HEADER;
			fifo_put_data_one_byte(&Uart0_DMARxFifo, pRxbuf);	
			
			if (pRxbuf[0]==1)//comm
			{
				hci_type = 1;
				DMA_4_COUNT = 3;// for byte
			}
			else if(pRxbuf[0]==2)
			{
				//ACL
				hci_type = 2;
				DMA_4_COUNT = 4;
			}
			else if(pRxbuf[0]==3)
			{
				//SCO
				hci_type = 3;
				DMA_4_COUNT = 3;
			}
			else if(pRxbuf[0]==4)
			{
				//EVENT
				hci_type =4;
				DMA_4_COUNT = 2;			
			}
			else
			{
				//for err
				fifo_discard_all_data(&Uart0_DMARxFifo);
				hci_type = 0;
				hci_uart_rx_state = HCI_UART_H4_SYNC_ERR;
				DMA_4_DEST = (U32 *)&uart0_rx_dma_buf[0];
				DMA_4_COUNT = 1;
			}
			//hci_uart_read_check();
			xEventGroupSetBitsFromISR(event_grop, BT_CONTROLLER_RX_EVENT,NULL);
		break;

		case HCI_UART_STATE_RX_HEADER:
			if (hci_type == 1 || hci_type == 3)
			{
				dma_rx_len = pRxbuf[3];
				fifo_put_data(&Uart0_DMARxFifo, pRxbuf+1,3);
				
				if (dma_rx_len)
				{
					hci_uart_rx_state = HCI_UART_CHECK_DATA;
					DMA_4_COUNT = dma_rx_len;
				}
				else
				{
					//fifo_put_data(&Uart0_DMARxFifo, pRxbuf,4);
					hci_type = 0;
					hci_uart_rx_state = HCI_UART_STATE_RX_TYPE;
										
					DMA_4_DEST = (U32 *)&uart0_rx_dma_buf[0];
					DMA_4_COUNT = 1;	
					//asm ("break 1,1");
				}
			}
			else if (hci_type == 2)
			{
				dma_rx_len = (pRxbuf[4]<<8) | (pRxbuf[3]);
				fifo_put_data(&Uart0_DMARxFifo, pRxbuf+1,4);
				//asm ("break 1,1");
				
				if (dma_rx_len)
				{
					hci_uart_rx_state = HCI_UART_CHECK_DATA;
					DMA_4_COUNT = dma_rx_len;
				}
				else
				{
					//fifo_put_data(&Uart0_DMARxFifo, pRxbuf,5);					
					hci_type = 0;
					hci_uart_rx_state = HCI_UART_STATE_RX_TYPE;
					DMA_4_DEST = (U32 *)&uart0_rx_dma_buf[0];
					DMA_4_COUNT = 1;	
				}
			}
			else if (hci_type == 4)
			{
				dma_rx_len = pRxbuf[2];
				fifo_put_data(&Uart0_DMARxFifo, pRxbuf+1,2);
				//asm ("break 1,1");
				DBG_Printf("dma_rx_len =4\n"); 
				if (dma_rx_len)
				{
					hci_uart_rx_state = HCI_UART_CHECK_DATA;
					DMA_4_COUNT = dma_rx_len;
				}
				else
				{
					//fifo_put_data(&Uart0_DMARxFifo, pRxbuf,3);					
					hci_type = 0;
					hci_uart_rx_state = HCI_UART_STATE_RX_TYPE;
					DMA_4_DEST = (U32 *)&uart0_rx_dma_buf[0];
					DMA_4_COUNT = 1;	
				}
			}
			else
			{
				//for Err
				fifo_discard_all_data(&Uart0_DMARxFifo);				
				hci_type = 0;
				hci_uart_rx_state = HCI_UART_H4_SYNC_ERR;
				DMA_4_DEST = (U32 *)&uart0_rx_dma_buf[0];
				DMA_4_COUNT = 1;
			}
			//hci_uart_read_check();
			xEventGroupSetBitsFromISR(event_grop, BT_CONTROLLER_RX_EVENT,NULL);
		break;

		
		case HCI_UART_CHECK_DATA:
			if (hci_type == 1 || hci_type == 3)
			{
				//dma_rx_len = pRxbuf[3];
				//fifo_put_data(&Uart0_DMARxFifo, pRxbuf,dma_rx_len+4);
				fifo_put_data(&Uart0_DMARxFifo, pRxbuf+4,dma_rx_len);
			}
			else if (hci_type == 2)
			{
				//dma_rx_len = pRxbuf[3]<<16 | pRxbuf[4];
				//fifo_put_data(&Uart0_DMARxFifo, pRxbuf,dma_rx_len+5);
				fifo_put_data(&Uart0_DMARxFifo, pRxbuf+5,dma_rx_len);
			}
			else if (hci_type == 4)
			{
				//dma_rx_len = pRxbuf[2];
				//fifo_put_data(&Uart0_DMARxFifo, pRxbuf,dma_rx_len+3);
				fifo_put_data(&Uart0_DMARxFifo, pRxbuf+3,dma_rx_len);
			}
			//hci_uart_read_check();
			xEventGroupSetBitsFromISR(event_grop, BT_CONTROLLER_RX_EVENT,NULL);
			hci_type = 0;
			hci_uart_rx_state = HCI_UART_STATE_RX_TYPE;

			DMA_4_DEST = (U32 *)&uart0_rx_dma_buf[0];
			DMA_4_COUNT = 1;
		break;
		
		default:
			fifo_discard_all_data(&Uart0_DMARxFifo);
			hci_type = 0;
			hci_uart_rx_state = HCI_UART_H4_SYNC_ERR;
			DMA_4_DEST = (U32 *)&uart0_rx_dma_buf[0];
			DMA_4_COUNT = 1;			
		break;
	}	
}

#endif//UART0_RX_DMA


void uart_read_end(void);
void uart_write_end(void);


const U8 cmd_rend[4] = {0xee,0xee,0xee,0xee};

void hci_uart_read_check (void)  __attribute__ ((section (".internal_ram_1_text")));

void hci_uart_read_check (void)
{
	U32 len;

#if 1//def UART0_RX_DMA	
		if (Uart0RcvLen > 0)
		{
			len = fifo_get_fifo_data_len(&Uart0_DMARxFifo);
	
			if (len >= Uart0RcvLen)
			{
				//if ((++count)>=6)
				//	asm ("break 1,1");
				fifo_get_data(&Uart0_DMARxFifo, Uart0RcvPtr, Uart0RcvLen);
#if 0
				for (i=0; i<Uart0RcvLen; i++)
				{
					DBG_Printf(",0x%x", Uart0RcvPtr[i]); 
				}
				DBG_Printf("\n\n"); 
#endif
				//in real application, should disable interrupt 		

				Uart0RcvLen = 0;
				uart_read_end();
			}
		}
	
#else
	
		if (Uart0RcvLen > 0)
		{
			len = fifo_get_fifo_data_len(&Uart0RxFifo);
	
			if (len >= Uart0RcvLen)
			{
				fifo_get_data(&Uart0RxFifo, Uart0RcvPtr, Uart0RcvLen);
				for (i=0; i<Uart0RcvLen; i++)
				{
					DBG_Printf(",0x%x\n", Uart0RcvPtr[i]); 
				}
	
				//in real application, should disable interrupt 		
				Uart0RcvLen = 0;
				
				uart_read_end();
			}
		}
#endif


/*
	if (pregs->status & STAT_TX_BUF_EMPTY)
	{
		//int disable
		pregs->intEnable	&=	~INT_TX_BUF_HALF_EMPTY;
		len = fifo_get_fifo_data_len(&Uart0TxFifo);

		if (len > 0)
		{
			fifo_get_data( &Uart0TxFifo, (U8*)&tmp, 1 );


			pregs->txBuf	=	tmp;	

			
			pregs->intEnable	|=	INT_TX_BUF_HALF_EMPTY;		
		}
	}
*/	


#if	0//def UART0_TX_DMA
	int i;
	U32 ret;
	U32 *pDmaDest;
	U32 data;

	len = fifo_get_fifo_data_len(&Uart0TxFifo);

	if (len > UART0_TX_DMA_BUF_SIZE) {
		//DBG_Assert (FALSE);
		len = UART0_TX_DMA_BUF_SIZE;
	}

	//checking uart0 dma busy
	//waiting for uart0 tx ready
	//tx_event_flags_get(&event_grop, UART0_TX_EVENT, TX_OR_CLEAR, &eventMask, TX_WAIT_FOREVER);
	if (uart0_tx_dma_send_en && (len > 0))
	{
		for (i=0; i<len; i++) 
		{
			fifo_get_data( &Uart0TxFifo, (U8*)&data, 1 );
			uart0_tx_dma_buf[i] = (U32) data;	
		}

		//dma
		pDmaDest = (U32 *)(&REG_UART0_TX_DATA);
		DMA_Channel5_Init(pDmaDest, uart0_tx_dma_buf, len, SOURCE_DMA_UART_0_TX);

		uart0_tx_dma_send_en = 0;
	}
#else

#if 0//no int

	int i;

	gpio0_SetOutput(UART2_RX);	

	if (pregs->status & STAT_TX_BUF_HALF_EMPTY)
	{
		//int disable
		//pregs->intEnable	&=	~INT_TX_BUF_HALF_EMPTY;
		len = fifo_get_fifo_data_len(&Uart0TxFifo);

		if (len > 8)
		{
			len = 8;
		}
		
		for (i=0;i<len;i++)
		{
			fifo_get_data( &Uart0TxFifo, (U8*)&tmp, 1 );
			pregs->txBuf	=	tmp;	
			
			//pregs->intEnable	|=	INT_TX_BUF_HALF_EMPTY;		
		}
	}
	
	gpio0_ClrOutput(UART2_RX);
#endif

#endif
}

void uart0_tx_send(char *buf, int size)
{
#if 1//def UART0_TX_DMA
	fifo_put_data(&Uart0_DMARxFifo, buf, size);
	xEventGroupSetBits(event_grop, BT_CONTROLLER_RX_EVENT);

	//SOFT1_INT_SET;
	//hci_uart_read_check();
	//if (((rwip_env.prevent_sleep&0x0001) == 0)&&ke_event_env.event_field)
	{
		//xEventGroupSetBits(event_grop, BT_CONTROLLER_EVENT);
	}
	//UART0_TX_EVENT_SET;
	//UART0_TX_EVENT_GET;
	//UART0_RX_EVENT_SET;
#endif
}

void hci_uart_fifo_init (FIFO *pFifo)
{
#if 1//def UART0_RX_DMA
	fifo_init (pFifo, uart0_rx_dma_buf, UART0_RX_DMA_BUF_SIZE,TRUE);
#endif
}

//#define BT_UART_RCV_DMA

//u32 uart_dma_buf[1024*2];

u32 uart_rcv_len;

void uart_read_set(U8 *bufptr, U32 size) __attribute__ ((section (".internal_ram_1_text")));

void uart_read_set(U8 *bufptr, U32 size)
{
#ifndef BT_UART_RCV_DMA

	Uart0RcvPtr = bufptr;
	Uart0RcvLen = size;
	xEventGroupSetBits(event_grop, BT_CONTROLLER_RX_EVENT);
	//SOFT1_INT_SET;
//	hci_uart_read_check();
	//xEventGroupSetBits(event_grop, BT_CONTROLLER_EVENT);
#else

	U32 *pUart0Dest;

	pUart0Dest = DMA_4_DEST;			//current fifo write address
	fifo_put_data_by_dma (pHcipUartRcvFifo, pUart0Dest);

/*
	u32 len;
	u32 rv_dma_size;

	Uart0RcvPtr = bufptr;
	Uart0RcvLen = size;

	//uart rcv intdisable
		
	uart_rcv_len= fifo_get_fifo_data_len(&Uart0RxFifo);
	if (uart_rcv_len > size) {
		//uart rcv enable
		return;
	}
	else {
		//copy fifo to bufptr
		rv_dma_size = size - uart_rcv_len;
		//enable dma recv


		//copy fifo to bufptr
		fifo_get_data(&Uart0RxFifo, Uart0RcvPtr, uart_rcv_len);
	
	}
*/
#endif //BT_UART_RCV_DMA	

}


extern FIFO *pHcipUartRcvFifo;
const U8 cmd_wend[4] = {0xff,0xff,0xff,0xff};

void uart_write_set(U8 *bufptr, U32 size) __attribute__ ((section (".internal_ram_1_text")));

void uart_write_set(U8 *bufptr, U32 size)
{
#if 1
	int i;
	U32 ret;
	U32 *pDmaDest;
	U32 data;

	if (size > UART0_TX_DMA_BUF_SIZE) {
		DBG_Assert (FALSE);
		//size = UART0_TX_DMA_BUF_SIZE;
	}
#ifndef BTDM_CONTROLLER_ONLY
	fifo_put_data(pHcipUartRcvFifo, bufptr, size);
#else
	while(get_DMA5_size() != 0);

	//checking uart0 dma busy
	if (size > 0)
	{
		for (i=0; i<size; i++) 
		{
#ifdef UART0_TX_DMA_8bit            
			uart0_tx_dma_buf[i] = bufptr[i];//(U32) bufptr[i];	
#else
			uart0_tx_dma_buf[i] = (U32) bufptr[i];
#endif
		}
#if 0
		DBG_Printf("U-");
		for (i=0; i<size; i++)
		{
			DBG_Printf(",0x%x", uart0_tx_dma_buf[i]); 
		}
		DBG_Printf("\n\n"); 
#endif
		//dma
		pDmaDest = (U32 *)(&REG_UART0_TX_DATA);
		DMA_Channel5_Init(pDmaDest, uart0_tx_dma_buf, size, SOURCE_DMA_UART_0_TX);

	}
#endif
#endif
	uart_write_end();

#ifndef BTDM_CONTROLLER_ONLY
	UART0_RX_EVENT_SET;
#endif

}

#if 0
void app_uart_receive(U8 data)
{
#ifdef UART0_USED_FOR_APP_UI
	U32 len;
	if (uart_receive_enable)
	{
		len = fifo_put_data_one_byte(pUartRcvFifo, &data);
	}
#endif
}

void app_uart0_receive(U8 data)
{
	U32 len;

	fifo_put_data_one_byte(&Uart0RxFifo, &data);

}


void app_uart1_receive(U8 data)
{
#if defined UART1_ENABLE && defined UART1_RX_ENABLE
	U32 len;
	U8 buf[18];
	
	if (1)//(uart_receive_enable & UART1_EN_BIT)
	{

		buf[0] = 'a';
		buf[1] = 'c';
		len = fifo_put_data_one_byte(&Uart1RcvFifo,&data);

		uart1_tx_send(buf,2);
	}

#endif
}
#endif

#endif //DAB_FRONTIER_FSAPI