audio_pll.h
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#ifndef AUDIO_PLL_H
#define AUDIO_PLL_H
enum {
FNPLL_FOR_44P1K,
FNPLL_FOR_48K
};
typedef volatile struct {
U32 sleep :1;
//U32 od :2;
U32 reset :1;
U32 od :1; //fnpll od = {this bit, 1'b1}
U32 M :8;
U32 N :4;
U32 select :1; //Integer M mode control
U32 fs :1; //Fraction R value selector
} AUDIO_FNPLL_CONTROLs;
typedef volatile struct {
U32 sleep :1;
U32 od :2;
U32 M :8;
U32 N :4;
} AUDIO_PLL_CONTROLs;
typedef volatile struct {
U32 fnpll_xin_s :2; //@2'b00:CLK_24M;2'b01:mclk_1_in;2'b10:mclk_2_in;
U32 pll_xin_s :3; //@3'b000:CLK_24M;3'b001:mclk_1_in;3'b010:mclk_2_in;3'b011:audio_fn_pll_clk;3'b100:spdif_dec_bit_clk;
U32 audio_pll_n1 :5;
U32 audio_pll_n2 :5;
U32 audio_fnpll_n1 :5;
U32 mclk1_s :1; //@1'b0:mclk_1_out = audio_pll_clk1;1'b1:mclk_1_out = audio_fn_pll_clk;
U32 mclk2_s :1; //@1'b0:mclk_2_out = audio_pll_clk2;1'b1:mclk_2_out = CLK_12M;
U32 mclk1_in_out :1; //@1b0:mclk1 in;1b1:mclk1 out
U32 mclk2_in_out :1; //@1b0:mclk2 in;1b1:mclk2 out
U32 mclk_s :2; //@2'b00:audio_pll_clk1;2'b01:mclk_1_in;2'b10:mclk_2_in;2'b11:CLK_12M;
} AUDIO_CLK_CONFIGs;
enum {
SPDIFDEC_1x = 0,
SPDIFDEC_2x,
SPDIFDEC_4x
};
enum {
SR_32000 = 0,
SR_44100,
SR_48000
};
enum {
MCLK_192 = 0,
MCLK_256,
MCLK_384
};
enum {
SR_44100_SPDIF_1x = 0,
SR_44100_SPDIF_2x,
SR_44100_SPDIF_4x,
SR_48000_SPDIF_1x,
SR_48000_SPDIF_2x,
SR_48000_SPDIF_4x,
SR_32000_SPDIF_1x,
SR_32000_SPDIF_2x,
SR_32000_SPDIF_4x,
SR_24000_SPDIF_1x,
SR_49000_SPDIF,
SR_98000_SPDIF,
SR_SPDIF_END,
};
enum {
FN_Normal = 0,
FN_P100PP, /*@0.01%*/
FN_P200PP, /*@0.02%*/
FN_P400PP, /*@0.04%*/
FN_M100PP, /*@-0.01%*/
FN_M200PP, /*@-0.02%*/
FN_M400PP /*@-0.04%*/
};
extern U8 audio_pll;
extern U16 pre_audio_freq;
U32 audio_fnpll_adjust(U32 step);
void audio_pll_init (void);
void audio_pll_open (void);
void audio_pll_clsoe(void);
void audio_pll_fini(void);
void audio_pll_adjust_d16 (U16 size);
void audio_pll_adjust_d24 (U16 size);
void audio_pll_set (U16 freq);
void audio_spdif_pll_set (U16 freq);
void audio_pll_set_fnpll_clk_in (void);
void audio_pll_set_spdif_bitclk_in (U8 spdif_inx);
void audio_pll_n2_set (U8 clk_double);
void audio_pll_set_mclk_in(void);
void audio_pll_CLK_set (U8 clk_double);
//#define SPDIF_LOCK_INTERVAL ((1000*60)/) /*250 * 4*/
#define SPDIF_LOCK_INTERVAL ((1000*60)/4) /*250 * 4*/
#define BT_LOCK_INTERVAL ((1000*60)/9) /*250 * 26*/
//#define BT_LOCK_INTERVAL ((1000*60)/130) /*250 * 130*/
#define BT_SLAVE_LOCK_INTERVAL ((1000*60)/130) /*250 * 26*/
void audio_pll_set_lock_interval (u16 val);
#endif