////////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2009 Optek.
//
//! \file interrupt.c
//! \brief
//! \version 0.1
//! \date Mar, 2005
//!
//! \see ThreadX User Guide
////////////////////////////////////////////////////////////////////////////////

#include "os_config.h"

#include "c_def.h"
#include "debug.h"
#include "oem.h"

#include "regmap.h"

#include "mem_reloc.h"

#include "hw_dma.h"
#include "hw_uart.h"
#include "interrupt.h"
#include "hw_pll.h"

#include "app_gpio_OEM.h"
//#include "app_uart.h"
//#include "app_rtc.h"
//#include "app_main.h"
//#include "remote.h"

//#include "test.h"
#include "otg.h"
#include "hw_timer.h"
#ifndef FREE_RTOS_DEBUG
/* FreeRTOS includes. */
#include "FreeRTOS.h"
#include "task.h"
#include "timers.h"
#include "event_groups.h"
#endif

void L1_int0_extlevel(void *param) __INTERNAL_RAM_TEXT;
void L1_int1_extlevel(void *param) __INTERNAL_RAM_TEXT;
void L1_int5_extlevel(void *param) __INTERNAL_RAM_TEXT;
void L1_int6_timer0(void *param) __INTERNAL_RAM_TEXT;
void L2_int8_extlevel(void *param) __INTERNAL_RAM_TEXT;
void L3_int9_extlevel(void *param) __INTERNAL_RAM_TEXT;
void L3_int10_timer1(void *param) __INTERNAL_RAM_TEXT;
void L2_int18_extlevel(void *param)  __INTERNAL_RAM_TEXT;
void L2_int19_extlevel(void *param)  __INTERNAL_RAM_TEXT;
void L1_int2_extlevel(void *param) __INTERNAL_RAM_TEXT;
void L2_int20_extlevel(void *param)__INTERNAL_RAM_TEXT;

//the level of xchal int0 is 1

void L1_int0_extlevel(void *param)
{
#ifdef POWER_KEY_ENABLE
	volatile U32 temp;
	temp = app_gpio_interrupt_st_read_use_index(POWER_KEY_PIN);
	if (temp)
	{
		hw_power_off();
	}
#endif		
}


void L1_int1_extlevel(void *param)
{
	U32 temp;
	int ret;

	do
	{
		temp = REG_INTCON_INT_STA;
		temp &= REG_INTCON_INT_ENA;

		if (temp & SOFT2_INT_MASK)
		{
			SoftInt2Isr();
		}

		if (temp & SOFT3_INT_MASK)
		{	
			SOFT3_INT_CLR;
			#if 1
			os_event_iset(AUDIO_DECODE_EVENT);
			#else
			ret = xEventGroupSetBitsFromISR(event_grop, AUDIO_DECODE_EVENT, NULL);
			if( ret == pdTRUE )
			{
				portYIELD_FROM_ISR();
			}
			#endif
		}

#ifdef USB_INT_CHANGEs_TO_LEVEL1
		if (temp & SOFT5_INT_MASK)
		{			
			SOFT5_INT_CLR;
			usbotg_isr();
		}
#endif

#if (defined UART2_ENABLE && defined UART2_INT_ENABLE)
		if (temp & UART2_INT_MASK)
		{
			Uart2_IsrHandler();
		}
#endif

#if (defined UART0_ENABLE && defined UART0_INT_ENABLE)
		if (temp & UART_INT_MASK)
		{
			Uart0_IsrHandler();
		}
#endif

#if (defined UART1_ENABLE && defined UART1_INT_ENABLE)
		if (temp & UART1_INT_MASK)
		{

			Uart1_IsrHandler();
		}
#endif
/*
		if (temp & SOFT2_INT_MASK)
		{
			SoftInt2Isr();
		}
*/
		if (temp & SOFT7_INT_MASK)
		{
			SOFT7_INT_CLR;
			#if 1
			os_event_iset(BT_CONTROLLER_EVENT);
			#else
			ret = xEventGroupSetBitsFromISR(event_grop, BT_CONTROLLER_EVENT, NULL);
			if( ret == pdTRUE )
			{
				portYIELD_FROM_ISR();
			}
			#endif
		}

#ifdef HDMI_CEC_BY_OPTEK
		if (temp & SOFT8_INT_MASK)
		{
			SoftInt8Isr();
		}
#endif

//------------------------------------------------------------
#ifdef SD_ENABLE
		if (temp & SD_INT_MASK)
		{
			sd_isr();
		}

#ifdef SD_DMA_TRANSFER
		if( temp & SD_DMA_SOFT_INT_MASK )
		{
			SD_DMA_SOFT_INT_CLR;

			if(	sdDma7 )
			{
				sd_dma7TxCompleteCallback();
			}
			else
			{
				sd_dma8RxCompleteCallback();
			}
		}
#endif //SD_ENABLE

#endif //SD_ENABLE

	} while( temp );

}


void L1_int2_extlevel(void *param)
{
}

void L1_int3_extlevel(void *param)
{
#ifdef REMOTE_ENABLE
	U32 ir_buf;
	
	ir_buf = REG_IR_RXFIFO;
	app_ir_buf_recive(ir_buf);
#endif
}

void L1_int4_extlevel(void *param)
{
}

#ifdef ADC_INT_ENABLE
void L1_int5_extlevel(void *param)
{
	app_adc_isrHandler();
}
#endif

//timer 0:the level of xchal int6 is 1
void L1_int6_timer0(void *param)
{
	//xtensa_timer0_updata();
}

void L1_int7_software(void)
{
}

#ifdef SYSTEM_CRASH_CHECK_ENABLE
volatile U8 usbotg_isr_check_cnt;
#endif

extern volatile U32 devfirst_ccount,hcountms,devcur_ccount;

void usbotg_isr( void );
void L2_int8_extlevel(void *param)
{
#ifdef USB_HOST_ENABLE
	U32 reg32;
	volatile U8	reg8; //jj+
#ifdef SYSTEM_CRASH_CHECK_ENABLE
	usbotg_isr_check_cnt = 1;
#endif

	reg32 = *otgEnhCtrl->ctrl;
	*otgEnhCtrl->ctrl	&=	~ENH_CTRL_INT_STAT_MASK;
	reg32 &= ENH_CTRL_INT_STAT_MASK;
	reg32 >>= ENH_CTRL_INT_STAT_SHIFT;
	
/*	if( reg32 & ENH_CTRL_INT_FIFO )
	{
		DBG_assert(0);
	}
	if( reg32 & ENH_CTRL_INT_WKUP )
	{
		DBG_assert(0);
	}
*/		
	if( reg32 & ENH_CTRL_INT_USB )
	{
#ifdef USB_INT_CHANGEs_TO_LEVEL1
		//jj+
		reg8	=	*usbdevReg->irq->usbirq;    //[des] 2.18.20 usbirq
		//reg8	&=	*usbdevReg->irq->usbien;    //[des] 2.18.31 usbien
		if( reg8 & 0x02 )
		{
			//[des] 2.18.20 usbirq sofir: receive a SOF pkt

			devcur_ccount = read_ccount();
			hcountms++;

			if (devfirst_ccount == 0)
			{
				devfirst_ccount = devcur_ccount;
				hcountms = 0;
			}
		}		
		SOFT5_INT_SET;
#else
		usbotg_isr();
#endif		
	}

#ifdef SYSTEM_CRASH_CHECK_ENABLE
	usbotg_isr_check_cnt = 2;
#endif

#endif
}

void L2_int18_extlevel(void *param)
{
//bt
#ifdef BTDM5_DIV_3INT
	rwbt_isr();
#else
	rwbt_isr();  
	rwble_isr();
	rwip_isr();
#endif
}

void L2_int19_extlevel(void *param)
{
//ble
#ifdef BTDM5_DIV_3INT   
	rwble_isr();
#endif
}

void L2_int20_extlevel(void *param)
{
//btdm
#ifdef BTDM5_DIV_3INT		
	rwip_isr();
#endif

#if 0
	if (((rwip_env.prevent_sleep&0x0001) == 0)&&ke_event_env.event_field)
	{
		//xEventGroupSetBitsFromISR(event_grop, BT_CONTROLLER_EVENT,NULL);
	}
#endif	
}

void Dma_0_TransmitIsr(void);
void Dma_8_TransmitIsr (void);
void Dma_2_RcvIsr (void);
void L3_int9_extlevel(void *param)
{
	
	static U8 status = TRUE;
	U32 dma_channel;

	dma_channel = DMA_GLOBAL_CNTR;

	if ((dma_channel & DMA_0_CHANNEL) == DMA_0_CHANNEL)
	{
		//Clear dma channel 0
		DMA_GLOBAL_CNTR = (0x00001000 | DMA_0_CHANNEL);
		Dma_0_TransmitIsr();
	}

	if ((dma_channel & DMA_8_CHANNEL) == DMA_8_CHANNEL)
	{
		//Clear dma channel 8
		DMA_GLOBAL_CNTR = (0x00001000 | DMA_8_CHANNEL);
		Dma_8_TransmitIsr();
	}

	if ((dma_channel & DMA_2_CHANNEL) == DMA_2_CHANNEL)
	{	
		//Clear dma channel 0
		DMA_GLOBAL_CNTR = (0x00001000 | DMA_2_CHANNEL);
		Dma_2_RcvIsr();	
	}

#ifdef OPTEK_DSP_MX1	
	if ((dma_channel & DMA_3_CHANNEL) == DMA_3_CHANNEL)
	{
		//Clear dma channel 3
		DMA_GLOBAL_CNTR = (0x00001000 | DMA_3_CHANNEL);
		Dma_3_RcvIsr();
	}
#endif //OPTEK_DSP_MX1

#ifdef UART0_RX_DMA
	if ((dma_channel & DMA_4_CHANNEL) == DMA_4_CHANNEL)
	{
		//Clear dma channel 4
		DMA_GLOBAL_CNTR = (0x00001000 | DMA_4_CHANNEL);
		UART0_DMA_Rx_handle();
	}
#endif //UART0_RX_DMA

#if	1//def UART0_TX_DMA
	if ((dma_channel & DMA_5_CHANNEL) == DMA_5_CHANNEL)
	{
		//Clear dma channel 5
		DMA_GLOBAL_CNTR = (0x00001000 | DMA_5_CHANNEL);
		
		//SOFT0_INT_SET;
	}
#endif //UART0_TX_DMA

#ifdef SD_ENABLE

#ifdef SD_DMA_TRANSFER
	//for sd tx
	if ((dma_channel & DMA_7_CHANNEL) == DMA_7_CHANNEL)
	{
		//disable dma
		DMA_7_CNTR = 0x00000000;
#ifdef DMA_CLEAR_MODE
		DMA_GLOBAL_CNTR = (0x00001000 | DMA_7_CHANNEL);
#else
		DMA_GLOBAL_CNTR |= (0x00001000 | DMA_7_CHANNEL);
#endif

		sdDma7 = TRUE;
		SD_DMA_SOFT_INT_SET;
	}

	//for sd rx
	if ((dma_channel & DMA_8_CHANNEL) == DMA_8_CHANNEL) {
		//disable dma
		DMA_8_CNTR = 0x00000000;

#ifdef DMA_CLEAR_MODE
		DMA_GLOBAL_CNTR = (0x00001000 | DMA_8_CHANNEL);
#else
		DMA_GLOBAL_CNTR |= (0x00001000 | DMA_8_CHANNEL);
#endif

		sdDma7 = FALSE;
		SD_DMA_SOFT_INT_SET;
	}
#endif //SD_DMA_TRANSFER

#endif //SD_ENABLE

}

#ifdef HDMI_CEC_BY_OPTEK
//U8 bt_hci_tick;
void HdmiCEC_handle (void);
#endif //HDMI_CEC_BY_OPTEK

//time 1:the level of xchal int10 is 3
void L3_int10_timer1(void *param)
{
#if 1//def TIMER1_ENABLE

	xtensa_timer1_updata();

#endif //TIMER1_ENABLE
}

extern unsigned int _xt_tick1_divisor;

/*
void optek_link_timer_int (void *param)
{
	DBG_PIN_HIGH;
	DBG_PIN_LOW;
	_xt_tick1_divisor = 0;
	xtensa_timer1_updata();
}
*/

/*unit is 0.5us*/
void optek_link_timer_set(U32 hus)
{
	_xt_tick1_divisor = XT_CLOCK_FREQ/(2*1000000)*hus;

	xtensa_timer1_updata();
	
}

void L3_int11_software(void *param)
{
}

void L4_int12_extlevel(void *param)
{
}

//time 2:the level of xchal int13 is 5
void L5_int13_timer2(void *param)
{
}

void L6_int14_NMI(void *param)
{
}