/*
 *  app_i2c3.c
 *
 *  Created on: 2020-1-9
 *  Author: 
 *  discription: the i2c3.c is dedicated to Optek's own PMU control and built-in OTK5283P and OTK5282P.
 */
#include "os_config.h"

#include "c_def.h"
#include "debug.h"
#include "oem.h"

#include "regmap.h"
#include "app_i2c.h"
#include "app_timer.h"
#include "app_gpio.h"
#include "hw_da_pp.h"


#define OTK5286_B_D

#if(defined OTK5286_B_D)
#define I2C_SCLK_PIN		GPIO_UNDEFINE_INDEX
#define I2C_SDATA_PIN		GPIO_UNDEFINE_INDEX

#elif (defined OTK5283P)
#undef PWM_CH8_AS_LRCK_BCK_OF_MI2S_OUT
#define I2C_SCLK_PIN		GPIO2_15_INDEX
#define I2C_SDATA_PIN		GPIO2_16_INDEX

#else (defined OTK5282P)
#undef PWM_CH8_AS_LRCK_BCK_OF_MI2S_OUT
#define I2C_SCLK_PIN		GPIO2_16_INDEX
#define I2C_SDATA_PIN		GPIO2_18_INDEX
#endif

#ifndef OTK5286_B_D

#define RTOS
#define I2C_Retries			3
    

/*** Fcpu = 8.4673*13MHz ***/

#define I2C_DELAY			delayus(4)
#define I2C_DELAY_DATA		delayus(2)

#define BIT1_MASK	0x01
#define BIT3_MASK	0x04
#define BIT4_MASK	0x08

#define PMU_ADDR	0x78
/***** PMU registor *****/
#define PMU_CURRENT_ADDR		0x01
#define PMU_BUCK_ADDR		    0x02
#define PMU_LDO_CODEC_ADDR		0x03

#define I2C_CLK_HIGH		GPIO_MUXFUNCTION_SELECT(I2C_SCLK_PIN,MUX_SEL_GPIO_INPUT)
#define I2C_CLK_LOW			GPIO_MUXFUNCTION_SELECT(I2C_SCLK_PIN,MUX_SEL_GPIO_OUTPUT); \
						    GPIO_OUTPUT_LEVEL_SET(I2C_SCLK_PIN,GPIO_LOW)

#define I2C_DATA_HIGH		GPIO_MUXFUNCTION_SELECT(I2C_SDATA_PIN,MUX_SEL_GPIO_INPUT)
#define I2C_DATA_LOW		GPIO_MUXFUNCTION_SELECT(I2C_SDATA_PIN,MUX_SEL_GPIO_OUTPUT); \
						    GPIO_OUTPUT_LEVEL_SET(I2C_SDATA_PIN,GPIO_LOW)

#define I2C_CLK_PIN			GPIO_INPUT_LEVEL_READ(I2C_SCLK_PIN)
#define I2C_DATA_PIN		GPIO_INPUT_LEVEL_READ(I2C_SDATA_PIN)

    
    
void app_i2c3_init (void)
{                                               
    //i2c clk,it is set to open drain pin
    GPIO_MUXFUNCTION_SELECT(I2C_SCLK_PIN, MUX_SEL_GPIO_INPUT);
    
    //i2c data,it is set to open drain pin
    GPIO_MUXFUNCTION_SELECT(I2C_SDATA_PIN, MUX_SEL_GPIO_INPUT);
}
/*STOP condition: SDA form Low to High while SCL is High*/
static void I2C_STOP (void)
{
    I2C_DATA_LOW;
    I2C_DELAY;
    I2C_CLK_HIGH;
    I2C_DELAY;
    I2C_DATA_HIGH;
    I2C_DELAY;
}

/* Bus not busy:both SDA and SCL lines remain High.******/
/*STAT condition: SDA form High to Low while SCL is high*/
static I2C_RETURN I2C_START (void)
{
    BYTE i;
    
    I2C_DATA_HIGH;
    I2C_DELAY_DATA;
    
    I2C_CLK_HIGH;
    I2C_DELAY;
   

    if (I2C_DATA_PIN) {
    	I2C_DATA_LOW;
    	I2C_DELAY;
    	I2C_DELAY;
    //		I2C_DELAY;
    	I2C_CLK_LOW;
    
    	I2C_DELAY_DATA;
    
    	return I2C_SUCCESS;
    }
    else {
        	/*DATA is locked, so unlock it*/
        	I2C_CLK_LOW;
        	I2C_DELAY;
        
        	for (i=0; i<9; i++) {
        		I2C_CLK_HIGH;
        		I2C_DELAY;
        		I2C_CLK_LOW;
        		I2C_DELAY;
        	}		
        	I2C_STOP ();
        
        	return I2C_ERROR;
        }
}


/**Get data at SCL rising edge, changing of the data at scl is falling**/ 
/** MSB is first sent out while data transfers ***/
static I2C_RETURN I2C_write_byte (BYTE b)
{
BYTE i;
BYTE bit_mask = 0x80;

for (i=0; i<8; i++) 
{

	if (b & bit_mask) {
		I2C_DATA_HIGH;
	}
	else {
		I2C_DATA_LOW;
	}

	I2C_DELAY_DATA;
	I2C_CLK_HIGH;    // get data while SCL rising edge
	I2C_DELAY;
	bit_mask >>= 1;

	I2C_CLK_LOW;
 //		I2C_DELAY_DATA;
 }

I2C_DATA_HIGH;
I2C_DELAY;
I2C_DELAY;

if (I2C_DATA_PIN) 
{
	I2C_CLK_HIGH;
	I2C_DELAY;

	I2C_CLK_LOW;
	I2C_DELAY_DATA;
	I2C_STOP ();
	return I2C_ERROR;
}
else 
{
	I2C_CLK_HIGH;
	I2C_DELAY;

	I2C_CLK_LOW;
	I2C_DELAY_DATA;
	return I2C_SUCCESS;
}
}


static BYTE I2C_read_byte (void)
{
    BYTE i;
    BYTE b=0;
    BYTE bit_mask = 0x80;
        
        I2C_DATA_HIGH;  // status
        
        for (i=0; i<8; i++, bit_mask >>= 1) {
        
        	I2C_DELAY;
        	I2C_CLK_HIGH;
        
        	if (I2C_DATA_PIN)
        		b |= bit_mask;
        
        	I2C_DELAY;
        	I2C_CLK_LOW;
    }
    
    I2C_DELAY_DATA;
    
    I2C_DATA_LOW;
    I2C_DELAY;
    I2C_CLK_HIGH;
    I2C_DELAY;
    I2C_CLK_LOW;
    
    I2C_DELAY_DATA;
    
    I2C_DATA_HIGH;
    
    return b;
}
    
static BYTE I2C_read_last_byte (void)
{
    BYTE i;
    BYTE b=0;
    BYTE bit_mask = 0x80;
    
    I2C_DATA_HIGH;
    
    for (i=0; i<8; i++, bit_mask >>= 1) {
    
    	I2C_DELAY;
    	I2C_CLK_HIGH;
    
    	if (I2C_DATA_PIN)
    		b |= bit_mask;
    
    	I2C_DELAY;
    	I2C_CLK_LOW;
}

I2C_DELAY_DATA;

I2C_DATA_HIGH;
I2C_DELAY;
I2C_CLK_HIGH;
I2C_DELAY;
I2C_CLK_LOW;
I2C_DELAY_DATA;

return b;
}

I2C_RETURN I2C3_write (BYTE i2c_addr, BYTE *wbuf, WORD len)
{
    U32 i,r,num_error = 0;
    
    #if 0//def RTOS
    OS_MUTEX_I2C0_LOCK;
    #endif

    do {
    	r = I2C_START();
    
    	if (r == I2C_SUCCESS) {
    		
    		r = I2C_write_byte (i2c_addr);
    	}
    
    	for (i=0; i<len; i++) {
    		if (r == I2C_SUCCESS) {
    
    			r = I2C_write_byte (*wbuf++);
    		}
    	}
    
    	if (r == I2C_SUCCESS) {
    		I2C_STOP();
    	}
    
} while ( (r != I2C_SUCCESS) && (num_error++ < I2C_Retries) );

if (r != I2C_SUCCESS) {
	I2C_STOP();
	DBG_Printf ("I2C3 writes no response 0x%x\n\r", i2c_addr);
}

#if 0//def RTOS
OS_MUTEX_I2C0_UNLOCK;
#endif

return r;
}
    
I2C_RETURN I2C3_read (BYTE i2c_addr, BYTE *rbuf, WORD len)
{
    #if (defined OTK5283P || defined OTK5282P)
      return;
    #endif

    U32 i,r,num_error = 0;
    BYTE read_addr;
    BYTE *pBuf;
    
    #if 0//def RTOS
    OS_MUTEX_I2C3_LOCK;
    #endif
    
    //	len *= 2;
    do
    {
    	pBuf = (BYTE *) rbuf;
    
    	r = I2C_START();
    
    	read_addr = i2c_addr | 0x01;				/*read addr*/
    
        #if 1
    	if (r == I2C_SUCCESS) {
    		r = I2C_write_byte (read_addr);
    	}
       #endif
    
       #if 0
    	if (r == I2C_SUCCESS) {
    		r = I2C_write_byte (i2c_addr);
    	}
    
    	if (r == I2C_SUCCESS) {
    		r = I2C_write_byte (sub_addr);
    	}
    
    //		if (r == I2C_SUCCESS) {
    //			I2C_STOP();
    //		}
    
    	if (r == I2C_SUCCESS) {
    		r = I2C_START();
    	}
    
    	if (r == I2C_SUCCESS) {
    		r = I2C_write_byte (read_addr);
    	}
        #endif
    
    	for (i=0; i<len-1; i++) {
    		*pBuf++ = I2C_read_byte ();
    	}
    
    	*pBuf = I2C_read_last_byte ();
    
    	if (r == I2C_SUCCESS) {
    		I2C_STOP();
    	}
    
    } while ( (r != I2C_SUCCESS) && (num_error++ < I2C_Retries) );
    
    if (r != I2C_SUCCESS) {
    	I2C_STOP();
    	DBG_Printf ("I2C3 writes no response 0x%x\n\r", i2c_addr);
    }
    
    #if 0//def RTOS
    OS_MUTEX_I2C0_UNLOCK;
    #endif
    
    return r;
}
    
I2C_RETURN I2C3_write_sub (BYTE i2c_addr, BYTE sub_addr, BYTE *wbuf, WORD len)
{
U32 i,r,num_error = 0;

#if 0//def RTOS
OS_MUTEX_I2C3_LOCK;
#endif

do
{
	r = I2C_START();

	if (r == I2C_SUCCESS) {
		r = I2C_write_byte (i2c_addr);
	}

	if (r == I2C_SUCCESS) {
		r = I2C_write_byte (sub_addr);
	}

	for (i=0; i<len; i++) {
		if (r == I2C_SUCCESS) {
			r = I2C_write_byte (*wbuf++);
		}
	}

	if (r == I2C_SUCCESS) {
		I2C_STOP();
	}

} while ( (r != I2C_SUCCESS) && (num_error++ < I2C_Retries) );

if (r != I2C_SUCCESS) {
	I2C_STOP();
	DBG_Printf ("I2C3 writes no response to the device 0x%x\n\r", i2c_addr);
}

#if 0//def RTOS
OS_MUTEX_I2C3_UNLOCK;
#endif

return r;
}

    #if 0
    I2C_RETURN I2C3_read_sub (BYTE i2c_addr, BYTE sub_addr, BYTE *rbuf, WORD len)
    {
        U32 i,r,num_error = 0;
        BYTE read_addr;
        BYTE *pBuf;
        
        #if 0//def RTOS
        OS_MUTEX_I2C3_LOCK;
        #endif
        
        //	len *= 2;
        do
        {
        	pBuf = (BYTE *) rbuf;
        
        	r = I2C_START();
        	if (r == I2C_SUCCESS) {
        		r = I2C_write_byte (i2c_addr);
        	}
    
        	if (r == I2C_SUCCESS) {
        		r = I2C_write_byte (sub_addr);
        	}
        
        //		if (r == I2C_SUCCESS) {
        //			I2C_STOP();
        //		}
        
        	read_addr = i2c_addr | 0x01;				/*read addr*/
        
        	if (r == I2C_SUCCESS) {
        		r = I2C_START();
        	}
        
        	if (r == I2C_SUCCESS) {
        		r = I2C_write_byte (read_addr);
        	}
        
        	for (i=0; i<len-1; i++) {
        		*pBuf++ = I2C_read_byte ();
        	}
        
    	*pBuf = I2C_read_last_byte ();
    
    	if (r == I2C_SUCCESS) {
    		I2C_STOP();
    	}
    
    } while ( (r != I2C_SUCCESS) && (num_error++ < I2C_Retries) );
    
    if (r != I2C_SUCCESS) {
    	I2C_STOP();
    	DBG_Printf ("I2C3 writes response to the device 0x%x\n\r", i2c_addr);
    }
    
    #if 0//def RTOS
    OS_MUTEX_I2C3_UNLOCK;
    #endif
    
    return r;
    }
#endif

void app_otk5310_pmu_init(void)
{
    DBG_Printf ("app otk5310 pmu init\n\r");
    U8 temp;

    //temp = 0x00;		//0mA
    //temp = 0x07;		//150mA
    //I2C3_write_sub(PMU_ADDR,PMU_CURRENT_ADDR,&temp,1);


    //temp = 0x00;	//   DC-DC  1.6V   LDO 1.1V  Default.
    //temp = 0x01;	//   DC-DC  1.6V   LDO 1.0V
    //temp = 0x31;	//   DC-DC  1.5 V   LDO 1.0V
    //temp = 0x11;  // DC-DC  1.35 V  LDO 1.0V
    temp = 0x21;    // DC-DC  1.20 V  LDO 1.0V
	I2C3_write_sub(PMU_ADDR,PMU_BUCK_ADDR,&temp,1);

    temp = 0x01;    //2.5V
    //temp = 0x00;	  //3.2V
    //temp = 0x03;    //1.8V
    I2C3_write_sub(PMU_ADDR,PMU_LDO_CODEC_ADDR,&temp,1);

}

void app_otk5310_pmu_recharge_ctl(U8 charge_mA)
{



     U8 tmp1;

     switch(charge_mA)
     {
       case 0:
            tmp1 = enCHARGE_0mA;
            break;

       case 1:
            tmp1 = enCHARGE_5mA;
            break;

       case 2:
            tmp1 = enCHARGE_10mA;
            break;
         
       case 3:
            tmp1 = enCHARGE_20mA;
            break;

       case 4:
            tmp1 = enCHARGE_50mA;
            break;
       case 5:
            tmp1 = enCHARGE_75mA;
            break;

       case 6:
            tmp1 = enCHARGE_100mA;
            break;

       case 7:
            tmp1 = enCHARGE_150mA;
            break;

       default:
            break;
     };
     I2C3_write_sub(PMU_ADDR,PMU_CURRENT_ADDR,&tmp1,1);

}

void app_pmu_voltage_ctl(U8 back_v, U8 core_v, U8 codec_v)
{

    U8 tmp1=0;
    switch(back_v)
    {
       case 0:
       tmp1 = enDC_BUCK_1V6;
       break;

       case 1:
       tmp1 = enDC_BUCK_1V3;
       break;

       case 2:
       tmp1 = enDC_BUCK_1V2;
       break;

       case 3:
       tmp1 = enDC_BUCK_1V5;
       break;

       default:
       break;
    }

    tmp1 = tmp1 <<4;

    switch(core_v)
    {
       case 0:
       tmp1 = tmp1 | enLDO_CORE1V1;
       break;

       case 1:
       tmp1 = tmp1 | enLDO_CORE1V0;
       break;

       case 2:
       tmp1 = tmp1 | enLDO_CORE1V2;
       break;

       default:
       break;
    }

    I2C3_write_sub(PMU_ADDR,PMU_BUCK_ADDR,&tmp1,1);

    tmp1 = 0;
    switch(codec_v)
    {
       case 0:
       tmp1 = enCODEC_LDO_3V2;
       break;

       case 1:
       tmp1 = enCODEC_LDO_2V5;
       break;

       case 2:
       tmp1 = enCODEC_LDO_1V8;
       break;

       default:
       break;
    }

    I2C3_write_sub(PMU_ADDR,PMU_LDO_CODEC_ADDR,&tmp1,1);


}

#endif //EMBEDED_HW_I2C