#include "os_config.h"

#include "c_def.h"
#include "debug.h"
#include "oem.h"

#include "regmap.h"

#include "hw_dma.h"

#include "app_main.h"
#include "optek_link.h"

//DMA used for SOURCE_DMA_SPDIF_DAC_OUT
void DMA_Channel0_Init(U32 *dest, U32 *src, U32 byte_count, U8 dma_source)
{
	volatile U32 tmp = 0;
	DMA_CNTRs *pCtrl = (DMA_CNTRs *) &tmp;
	
	DMA_0_CNTR = 0;
	
	DMA_0_SOURCE = (U32)src;
	DMA_0_DEST = (U32)dest;
	
	DMA_0_COUNT = byte_count;
	
	pCtrl->size = DMA_TRANSMIT_SIZE_WORD;	//Transfer size
	pCtrl->burst_size = DMA_BURST_SINGLE;	    //1
	pCtrl->saddr_inc = DMA_SRC_ADDR_INC;;	//Source address inc select
	pCtrl->daddr_inc = DMA_SRC_ADDR_FIXED;	//Destination address inc select
	pCtrl->source = dma_source;			    //Dma source select
	pCtrl->start = 0;						//not software dma start
	pCtrl->channel_enb = 1;					//Channel enable
	pCtrl->int_enb = 1;						//interrupt enable
	//pCtrl->int_enb = 0;						//interrupt disable
	
	DMA_0_CNTR = tmp;	
}

void DMA_Channel0_Disable(void)
{
	DMA_0_CNTR = 0;
	DMA_0_COUNT = 0;
}


//dma 2 for adc or iis1 in
void DMA_Channel2_Init(U32 *dest, U32 *src, U32 byte_count, U8 dma_source)
{
	TX_INTERRUPT_SAVE_AREA;
	volatile U32 tmp = 0;
	DMA_CNTRs *pCtrl = (DMA_CNTRs *) &tmp;
	
	TX_DISABLE;
	DMA_2_CNTR = 0;
	
	DMA_2_SOURCE = (U32)src;
	DMA_2_DEST = (U32)dest;
	
	DMA_2_COUNT = byte_count;
	
	pCtrl->size = DMA_TRANSMIT_SIZE_WORD;   //Transfer size
	if (app_main_data.share_link_role == SL_ROLE_SLAVE)
		pCtrl->burst_size = DMA_BURST_SINGLE;     //DMA_BURST_EIGHT;		//burst size select
	else if (optek_link_mode == GAME_HEADPHONE_PT7P5MS_T7R3E || optek_link_mode == BC_SF48K_PT7P5MS)
		pCtrl->burst_size = DMA_BURST_EIGHT;     //DMA_BURST_EIGHT;		//burst size select
	else
		pCtrl->burst_size = DMA_BURST_SIXTEEN;     //DMA_BURST_EIGHT;		//burst size select
	pCtrl->saddr_inc = DMA_SRC_ADDR_FIXED;  //Source address inc select
	pCtrl->daddr_inc = DMA_DEST_ADDR_INC;   //Destination address inc select
	pCtrl->source = dma_source;             //Dma source select
	pCtrl->start = 0;                       //not software dma start
	pCtrl->channel_enb = 1;                 //Channel enable
	pCtrl->int_enb = 1;                     //interrupt enable
	//pCtrl->int_enb = 0;

	DMA_2_CNTR = tmp;
	
	TX_RESTORE;	
}

void DMA_Channel2_Disable(void)
{
	TX_INTERRUPT_SAVE_AREA;

	TX_DISABLE;
	DMA_2_CNTR = 0;
	DMA_2_COUNT = 0;
	TX_RESTORE;
}


#ifdef OPTEK_DSP_MX1
//dma 3 for adc or iis1 in
void DMA_Channel3_Init(U32 *dest, U32 *src, U32 byte_count, U8 dma_source)
{
	TX_INTERRUPT_SAVE_AREA;
	volatile U32 tmp = 0;
	DMA_CNTRs *pCtrl = (DMA_CNTRs *) &tmp;
	
	TX_DISABLE;
	DMA_3_CNTR = 0;
	
	DMA_3_SOURCE = (U32)src;
	DMA_3_DEST = (U32)dest;
	
	DMA_3_COUNT = byte_count;
	
	pCtrl->size = DMA_TRANSMIT_SIZE_WORD;   //Transfer size
	pCtrl->burst_size = DMA_BURST_FOUR;     //DMA_BURST_EIGHT;		//burst size select
	pCtrl->saddr_inc = DMA_SRC_ADDR_FIXED;  //Source address inc select
	pCtrl->daddr_inc = DMA_DEST_ADDR_INC;   //Destination address inc select
	pCtrl->source = dma_source;             //Dma source select
	pCtrl->start = 0;                       //not software dma start
	pCtrl->channel_enb = 1;                 //Channel enable
	pCtrl->int_enb = 1;                     //interrupt enable
	
	DMA_3_CNTR = tmp;
	
	TX_RESTORE;	
}

void DMA_Channel3_Disable(void)
{
	TX_INTERRUPT_SAVE_AREA;

	TX_DISABLE;
	DMA_3_CNTR = 0;
	DMA_3_COUNT = 0;
	TX_RESTORE;
}
#endif //OPTEK_DSP_MX1


//DMA used as UART0 RX
#if	1//def BT_HCI_ENABLE

extern U8 BtHCI_uart_rx_enable;

void DMA_Channel4_Init(U32 *dest, U32 *src, U32 byte_count, U8 dma_source)
{
	volatile U32 tmp = 0;
	DMA_CNTRs *pCtrl = (DMA_CNTRs *) &tmp;
	
	DMA_4_CNTR = 0;
	
	DMA_4_SOURCE = (U32)src;
	DMA_4_DEST = (U32)dest;
	
	DMA_4_COUNT = byte_count;

#ifdef UART0_RX_DMA	
	pCtrl->size = DMA_TRANSMIT_SIZE_BYTE;	//Transfer size
#else
	pCtrl->size = DMA_TRANSMIT_SIZE_WORD;	//Transfer size
#endif
	pCtrl->burst_size = DMA_BURST_SINGLE;		//1/
	pCtrl->saddr_inc = DMA_SRC_ADDR_FIXED;	//Source address inc select
	pCtrl->daddr_inc = DMA_DEST_ADDR_INC;	//Destination address inc select
	pCtrl->source = dma_source;			//Dma source select
	pCtrl->start = 0;						//not software dma start
	pCtrl->channel_enb = 1;					//Channel enable
	pCtrl->int_enb = 1;						//interrupt enable
	
	DMA_4_CNTR = tmp;

//	BtHCI_uart_rx_enable = 1;
	
}

void DMA_Channel4_Disable(void)
{
//	BtHCI_uart_rx_enable = 0;
	
	DMA_4_CNTR = 0;
	DMA_4_COUNT = 0;
}

//DMA used as UART0 TX
void DMA_Channel5_Init(U32 *dest, U32 *src, U32 byte_count, U8 dma_source)
{
	volatile U32 tmp = 0;
	DMA_CNTRs *pCtrl = (DMA_CNTRs *) &tmp;
	
	DMA_5_CNTR = 0;
	
	DMA_5_SOURCE = (U32)src;
	DMA_5_DEST = (U32)dest;
	
	DMA_5_COUNT = byte_count;
	
#ifdef UART0_TX_DMA_8bit
	pCtrl->size = DMA_TRANSMIT_SIZE_BYTE;	//DMA_TRANSMIT_SIZE_WORD;	//Transfer size
#else
	pCtrl->size = DMA_TRANSMIT_SIZE_WORD;	//Transfer size
#endif

	pCtrl->burst_size = DMA_BURST_SINGLE;		//1/ 
	pCtrl->saddr_inc = DMA_SRC_ADDR_INC;	//Source address inc select
	pCtrl->daddr_inc = DMA_DEST_ADDR_FIXED;	//Destination address inc select
	pCtrl->source = dma_source;			//Dma source select
	pCtrl->start = 0;						//not software dma start
	pCtrl->channel_enb = 1;					//Channel enable
	pCtrl->int_enb = 1;						//interrupt enable
	
	DMA_5_CNTR = tmp;
	
}

void DMA_Channel5_Disable(void)
{
	DMA_5_CNTR = 0;
	DMA_5_COUNT = 0;
}

U32 get_DMA5_size(void)
{
	return DMA_5_COUNT;
}

//dma 9 for bc slave
void DMA_Channel8_Init(U32 *dest, U32 *src, U32 byte_count, U8 dma_source)
{
	volatile U32 tmp = 0;
	DMA_CNTRs *pCtrl = (DMA_CNTRs *) &tmp;
	
	DMA_8_CNTR = 0;
	
	DMA_8_SOURCE = (U32)src;
	DMA_8_DEST = (U32)dest;
	
	DMA_8_COUNT = byte_count;
	
	pCtrl->size = DMA_TRANSMIT_SIZE_WORD;	//Transfer size
	pCtrl->burst_size = DMA_BURST_SINGLE;	    //1
	pCtrl->saddr_inc = DMA_SRC_ADDR_INC;;	//Source address inc select
	pCtrl->daddr_inc = DMA_SRC_ADDR_FIXED;	//Destination address inc select
	pCtrl->source = dma_source;			    //Dma source select
	pCtrl->start = 0;						//not software dma start
	pCtrl->channel_enb = 1;					//Channel enable
	pCtrl->int_enb = 1;						//interrupt enable
	//pCtrl->int_enb = 0;						//interrupt disable
	
	DMA_8_CNTR = tmp;		
}

void DMA_Channel8_Disable(void)
{
	TX_INTERRUPT_SAVE_AREA;

	TX_DISABLE;
	DMA_8_CNTR = 0;
	DMA_8_COUNT = 0;
	TX_RESTORE;
}


//dma 9 for bc slave
void DMA_Channel9_Init(U32 *dest, U32 *src, U32 byte_count, U8 dma_source)
{
	TX_INTERRUPT_SAVE_AREA;
	volatile U32 tmp = 0;
	DMA_CNTRs *pCtrl = (DMA_CNTRs *) &tmp;
	
	TX_DISABLE;
	DMA_9_CNTR = 0;
	
	DMA_9_SOURCE = (U32)src;
	DMA_9_DEST = (U32)dest;
	
	DMA_9_COUNT = byte_count;
	
	pCtrl->size = DMA_TRANSMIT_SIZE_WORD;   //Transfer size
	pCtrl->burst_size = DMA_BURST_SINGLE;     //DMA_BURST_EIGHT;		//burst size select
	pCtrl->saddr_inc = DMA_SRC_ADDR_FIXED;  //Source address inc select
	pCtrl->daddr_inc = DMA_DEST_ADDR_INC;   //Destination address inc select
	pCtrl->source = dma_source;             //Dma source select
	pCtrl->start = 0;                       //not software dma start
	pCtrl->channel_enb = 1;                 //Channel enable
	pCtrl->int_enb = 1;                     //interrupt enable
	//pCtrl->int_enb = 0;

	DMA_9_CNTR = tmp;
	
	TX_RESTORE;	
}

void DMA_Channel9_Disable(void)
{
	TX_INTERRUPT_SAVE_AREA;

	TX_DISABLE;
	DMA_9_CNTR = 0;
	DMA_9_COUNT = 0;
	TX_RESTORE;
}

#endif	//BT_HCI_ENABLE



#if 0

#ifdef SD_DMA_TRANSFER
void dma_transf_init(u32 *reg, u32 *sou, u32 *dest, u32 len)
{
	u16 i;

	*reg = sou;			//dma source register		
	reg += 2;
	*reg = dest;		//dma dest register
	
	reg += 2;
	*reg  = len;		//dma counter register
}

void dma_transf_contrl_set(u32 *p, u8 b_sizes, BOOL sInc, BOOL dInc, u8 trig)
{
	volatile u32 dma_ctl = 0;
	DMA_CNTRs *pCtl;

	pCtl = (DMA_CNTRs *)&dma_ctl;
	
	pCtl->size = sizeof(WORD);		//Transfer size
	pCtl->burst_size = b_sizes;		//burst size select
	pCtl->saddr_inc = sInc;			//Source address inc select
	pCtl->daddr_inc = dInc;			//Destination address inc select
	pCtl->source = trig;			//Dma source select
	pCtl->start = 0;				//not software dma start
	pCtl->channel_enb = 1;			//Channel enable
	pCtl->int_enb = 1;				//interrupt disable

	*p = dma_ctl;
//	p->start = 1;					//channel start	
}
#endif //SD_DMA_TRANSFER


//OTK526x
//dma 0 for da_pp or iis1 tx
void DMA_Channel0_Init(U32 *dest, U32 *src, U32 byte_count, U8 dma_source)
{
	volatile U32 tmp = 0;
	DMA_CNTRs *pCtrl = (DMA_CNTRs *) &tmp;
	
	DMA_0_SOURCE = (U32)src;
	DMA_0_DEST = (U32)dest;
	
	DMA_0_COUNT = byte_count;
	
	pCtrl->size = DMA_TRANSMIT_SIZE_WORD;	//Transfer size
	pCtrl->burst_size = DMA_BURST_FOUR;	//DMA_BURST_EIGHT;		//burst size select
	pCtrl->saddr_inc =	DMA_SRC_ADDR_INC;	//Source address inc select
	pCtrl->daddr_inc = 	DMA_DEST_ADDR_FIXED;//Destination address inc select
	pCtrl->source = dma_source;			//Dma source select
	pCtrl->start = 0;						//not software dma start
	pCtrl->channel_enb = 1;					//Channel enable
	pCtrl->int_enb = 1;						//interrupt enable
	
	DMA_0_CNTR = tmp;
	
}

void DMA_Channel0_Disable(void)
{
	DMA_0_CNTR = 0;
	DMA_0_COUNT = 0;
}


//dma 1 for iis0, iis1 in or spdif in
void DMA_Channel1_Init(U32 *dest, U32 *src, U32 byte_count, U8 dma_source)
{
	volatile U32 tmp = 0;
	DMA_CNTRs *pCtrl = (DMA_CNTRs *) &tmp;
	
	DMA_1_CNTR = 0;
	
	DMA_1_SOURCE = (U32)src;
	DMA_1_DEST = (U32)dest;
	
	DMA_1_COUNT = byte_count;
	
	pCtrl->size = DMA_TRANSMIT_SIZE_WORD;   //Transfer size
	pCtrl->burst_size = DMA_BURST_FOUR;     //DMA_BURST_EIGHT; //burst size select
	pCtrl->saddr_inc = DMA_SRC_ADDR_FIXED;  //Source address inc select
	pCtrl->daddr_inc = DMA_DEST_ADDR_INC;   //Destination address inc select
	pCtrl->source = dma_source;             //Dma source select
	pCtrl->start = 0;                       //not software dma start
	pCtrl->channel_enb = 1;                 //Channel enable
	pCtrl->int_enb = 1;                     //interrupt enable
	
	DMA_1_CNTR = tmp;
	
}

void DMA_Channel1_Disable(void)
{
	DMA_1_CNTR = 0;
	DMA_1_COUNT = 0;
}

//dma 2 for adc or iis1 in
void DMA_Channel2_Init(U32 *dest, U32 *src, U32 byte_count, U8 dma_source)
{
	TX_INTERRUPT_SAVE_AREA;
	volatile U32 tmp = 0;
	DMA_CNTRs *pCtrl = (DMA_CNTRs *) &tmp;
	
	TX_DISABLE;
	DMA_2_CNTR = 0;
	
	DMA_2_SOURCE = (U32)src;
	DMA_2_DEST = (U32)dest;
	
	DMA_2_COUNT = byte_count;
	
	pCtrl->size = DMA_TRANSMIT_SIZE_WORD;   //Transfer size
	pCtrl->burst_size = DMA_BURST_FOUR;     //DMA_BURST_EIGHT;		//burst size select
	pCtrl->saddr_inc = DMA_SRC_ADDR_FIXED;  //Source address inc select
	pCtrl->daddr_inc = DMA_DEST_ADDR_INC;   //Destination address inc select
	pCtrl->source = dma_source;             //Dma source select
	pCtrl->start = 0;                       //not software dma start
	pCtrl->channel_enb = 1;                 //Channel enable
	pCtrl->int_enb = 1;                     //interrupt enable
	
	DMA_2_CNTR = tmp;
	
	TX_RESTORE;	
}

void DMA_Channel2_Disable(void)
{
	TX_INTERRUPT_SAVE_AREA;

	TX_DISABLE;
	DMA_2_CNTR = 0;
	DMA_2_COUNT = 0;
	TX_RESTORE;
}


#if 1//def KALAOK_EN
//dma 3 for adc or iis1 in
void DMA_Channel3_Init(U32 *dest, U32 *src, U32 byte_count, U8 dma_source)
{
	TX_INTERRUPT_SAVE_AREA;
	volatile U32 tmp = 0;
	DMA_CNTRs *pCtrl = (DMA_CNTRs *) &tmp;
	
	TX_DISABLE;
	DMA_3_CNTR = 0;
	
	DMA_3_SOURCE = (U32)src;
	DMA_3_DEST = (U32)dest;
	
	DMA_3_COUNT = byte_count;
	
	pCtrl->size = DMA_TRANSMIT_SIZE_WORD;   //Transfer size
	pCtrl->burst_size = DMA_BURST_FOUR;     //DMA_BURST_EIGHT;		//burst size select
	pCtrl->saddr_inc = DMA_SRC_ADDR_FIXED;  //Source address inc select
	pCtrl->daddr_inc = DMA_DEST_ADDR_INC;   //Destination address inc select
	pCtrl->source = dma_source;             //Dma source select
	pCtrl->start = 0;                       //not software dma start
	pCtrl->channel_enb = 1;                 //Channel enable
	pCtrl->int_enb = 1;                     //interrupt enable
	
	DMA_3_CNTR = tmp;
	
	TX_RESTORE;	
}

void DMA_Channel3_Disable(void)
{
	TX_INTERRUPT_SAVE_AREA;

	TX_DISABLE;
	DMA_3_CNTR = 0;
	DMA_3_COUNT = 0;
	TX_RESTORE;
}
#endif



#ifdef REMOTE_IR_ENABLE

//DMA used for IR
void DMA_Channel6_Init(U32 *dest, U32 *src, U32 byte_count, U8 dma_source)
{
	volatile U32 tmp = 0;
	DMA_CNTRs *pCtrl = (DMA_CNTRs *) &tmp;
	
	DMA_6_CNTR = 0;
	
	DMA_6_SOURCE = (U32)src;
	DMA_6_DEST = (U32)dest;
	
	DMA_6_COUNT = byte_count;
	
	pCtrl->size = DMA_TRANSMIT_SIZE_WORD;   //Transfer size
	pCtrl->burst_size = DMA_BURST_SINGLE;   // size
//	pCtrl->burst_size = DMA_BURST_4;        //burst size select
	pCtrl->saddr_inc = DMA_SRC_ADDR_FIXED;  //Source address inc select
	pCtrl->daddr_inc = DMA_DEST_ADDR_INC;   //Destination address inc select
	pCtrl->source = dma_source;             //Dma source select
	pCtrl->start = 0;                       //not software dma start
	pCtrl->channel_enb = 1;                 //Channel enable
	pCtrl->int_enb = 1;                     //interrupt enable
	
	DMA_6_CNTR = tmp;
}

void DMA_Channel6_Disable(void)
{
#if 1
//	DMA_6_CNTR = 0;
	DMA_6_COUNT = 0;
#else
	//dma transfer disable, clear dma flag
	DMA_GLOBAL_CNTR = (~0x00001000 | DMA_6_CHANNEL);
#endif
}

void DMA_Channel6_Enable(U32 byte_count)
{
#if 1
	DMA_6_COUNT = byte_count;
#else
	//dma transfer enable, clear dma flag
	DMA_GLOBAL_CNTR = (0x00001000 | DMA_6_CHANNEL);
#endif
}

#endif //REMOTE_IR_ENABLE


void DMA_Channel7_Init(U32 *dest, U32 *src, U32 byte_count)
{
	volatile U32 *pDmaSrc = &DMA_7_SOURCE;
	volatile U32 *pDmaDest = &DMA_7_DEST;
	U32 tmp = 0;
	DMA_CNTRs *pCtrl = (DMA_CNTRs *) &tmp;

//	pDmaSrc = src;
//	pDmaDest = dest;
	DMA_7_CNTR = 0;

	DMA_7_SOURCE = (U32)src;
	DMA_7_DEST = (U32)dest;

	DMA_7_COUNT = byte_count;

//	pCtrl->size = DMA_TRANSMIT_SIZE_BYTE;   //Transfer size
	pCtrl->size = DMA_TRANSMIT_SIZE_WORD;   //Transfer size
//	pCtrl->burst_size = DMA_BURST_SINGLE;   //burst size select
	pCtrl->burst_size = DMA_BURST_4;        //burst size select
	//pCtrl->saddr_inc =	DMA_SRC_ADDR_FIXED; //Source address inc select
	pCtrl->saddr_inc =	DMA_SRC_ADDR_INC; //Source address inc select
	pCtrl->daddr_inc = 	DMA_DEST_ADDR_INC;  //Destination address inc select
	pCtrl->source = SOURCE_DMA_COPYDATA;           //Dma source select
	pCtrl->start = 1;                       //software dma start
	pCtrl->channel_enb = 1;                 //Channel enable
	pCtrl->int_enb = 1;                     //interrupt Enable

	//tmp(=0x0000619a)
	DMA_7_CNTR = tmp;

//	pCtrl->start = 1;						//channel start	
}
#endif