#include "os_config.h"

#include "c_def.h"
#include "debug.h"
#include "oem.h"

#include "regmap.h"

#include "hw_pll.h"
#include "hw_uart.h"
#include "hw_da_pp.h"
#include "hw_dma.h"
#include "hw_codec.h"

#include "App_main.h"

enum 
{
	APWM_OUT_MUTE_OFF = 0,
	APWM_OUT_MUTE_ON = 1,
	I2S_BLCK_OUT = 1,
	I2S_LRCK_OUT = 1
};


void dda_pp_init(void)
{
	volatile U32 tmp1;
	volatile U32 tmp;
	volatile U16 dma_tx_start = 0;
	U32 temp;


#if 1//def CLASSD_OUT_TEST
	//32'b 0_1_00_0_001110_0_1_11_0_0_1_01_0111_00_00_10_1_1;				//8x //24bit, 2 chans, 8x, quan 7+1, 48k

	CLASSD_CONFIG_AHB *classd_config_ahb;

	CLASSD_CONFIG_AHB_2 *classd_config_ahb_2;
	CLASSD_CONFIG_AHB_3 *classd_config_ahb_3;

	U32 value = 0;
	value = DA_PP_CLASSD_CONFIG;
	classd_config_ahb = (CLASSD_CONFIG_AHB *) &value;


#ifdef AUDIO_24_BIT_OUTPUT
	classd_config_ahb->classd_data_24_bit = 1;
#else
	classd_config_ahb->classd_data_24_bit = 0;
#endif

	classd_config_ahb->classd_6db = 0;//default: 0-> 0dB;1-> 6dB

#ifdef PWM_768_2048
	classd_config_ahb->pp_clk_config = 1;
#elif defined PWM_2304x
	classd_config_ahb->pp_clk_config = 0;
#else  //PWM_384
	classd_config_ahb->pp_clk_config = 2;
#endif
	
#ifdef PWM_768_4096
	classd_config_ahb->osr_config = 2;
#elif defined PWM_768_2048
	classd_config_ahb->osr_config = 2;
#elif defined PWM_2304x
	classd_config_ahb->osr_config = 3;
#else
	classd_config_ahb->osr_config = 0;
#endif

	//classd_config_ahb->stream_type = 0; //0 is ok, 1/2/3 is NG
	classd_config_ahb->stream_type = 0;

#ifdef PWM_2304x
	classd_config_ahb->sigma_delta_quan = 5;
#elif defined PWM_768_2048
	classd_config_ahb->sigma_delta_quan = 6;
#else
	classd_config_ahb->sigma_delta_quan = 7;
#endif


#if (SHARE_LINK_MODE == SL_SUBWOOFER)
	if (app_main_data.share_link_role == SL_ROLE_SLAVE)
	{
		classd_config_ahb->pp_clk_config = 2;
		classd_config_ahb->osr_config = 0;
		classd_config_ahb->sigma_delta_quan = 7;
	}
#endif

	classd_config_ahb->sigma_delta_order = 1;
#if 0//def PWM_HALF_BRIDGE
	classd_config_ahb->sd_reset_en = 0;
#else
	classd_config_ahb->sd_reset_en = 1;
#endif
	classd_config_ahb->pwm_inv = 0;
	classd_config_ahb->mi2s_da_pp_n = 0;      //1:original data.

	classd_config_ahb->mi2s_chs = MI2S_OUTPUT_CHANNEL_DEFAULT;// 3

	classd_config_ahb->classd_clk_err_en = 0;
	//classd_config_ahb->reserved = 0;
	classd_config_ahb->pwm_delay = 0xE;   //6bits
	classd_config_ahb->pwm_i2s_lrck_swap = 0;
	classd_config_ahb->pwm_i2s_sel = 0;  //0: mi2s_out_bclk=192k; 1: mi2s_out_bck=96k; 3: mi2s_out_bck=48k.
	classd_config_ahb->pwm_i2s_en = 1;   //1:enable bck of pwm and mi2s_out;
#if 1//def PWM_HALF_BRIDGE
	classd_config_ahb->pwm_reset_en = 0;  
#else
	classd_config_ahb->pwm_reset_en = 1;
#endif
	DA_PP_CLASSD_CONFIG = value;


	value = DA_PP_CLASSD_CONFIG_AHB_2;
	classd_config_ahb_2 = (CLASSD_CONFIG_AHB_2 *) &value;  
	
	classd_config_ahb_2->pwm_adjust_t = 0;
	//classd_config_ahb_2->pwm_adjust_t = 0xF;


#ifdef AUDIO_PWM_MOSFET_OUT
	//A06604
	classd_config_ahb_2->pwm_drv_pre_deadt = 14; //6*14: 84ns  
	classd_config_ahb_2->pwm_drv_post_deadt = 14; //6*14: 84ns	
	classd_config_ahb_2->pwm_min_t = 31; //its value is above two numbers conbined, and its is never great than 31.
#else
	//Headphone
	classd_config_ahb_2->pwm_drv_pre_deadt = 2;
	classd_config_ahb_2->pwm_drv_post_deadt = 1;
	classd_config_ahb_2->pwm_min_t= 4;
#endif

    /*********disable ch7/8 pwm out ****************/
	classd_config_ahb_2->i2s_ch7_ch8_pwm_disable = 1;
    
	#if 0// i2s_ch6/7_pwm_p/n_mux_en = 0 is pwm out.
    	classd_config_ahb_2->i2s_ch7_pwm_p_mux_en = 1;
    	classd_config_ahb_2->i2s_ch7_pwm_n_mux_en = 1;
        classd_config_ahb_2->i2s_ch6_pwm_p_mux_en = 1;
    	classd_config_ahb_2->i2s_ch6_pwm_n_mux_en = 1;

        classd_config_ahb_2->i2s_ch7_pwm_p_sel = 0;
    	classd_config_ahb_2->i2s_ch7_pwm_n_sel = 1;
        classd_config_ahb_2->i2s_ch6_pwm_p_sel = 2;
    	classd_config_ahb_2->i2s_ch6_pwm_n_sel = 3;
	#else
    	classd_config_ahb_2->i2s_ch7_pwm_p_mux_en = 0;
    	classd_config_ahb_2->i2s_ch7_pwm_n_mux_en = 0;
        classd_config_ahb_2->i2s_ch6_pwm_p_mux_en = 0;
    	classd_config_ahb_2->i2s_ch6_pwm_n_mux_en = 0;
	#endif
    
	

   
/****************************MI2S_Multi_OUT_BCLK/LRCK/DATA[0:3]***************************/
/****************************maintained by leelin, updated: may 30 2020************************************/
#ifdef MI2S_OUT_ENABLE
    U32 classd_config_ahb_strc = 0;
    classd_config_ahb_strc = DA_PP_CLASSD_CONFIG;

    //CLASSD_CONFIG_AHB *classd_config_ahb;
    classd_config_ahb = (CLASSD_CONFIG_AHB *) &classd_config_ahb_strc;
    

    classd_config_ahb->sd_reset_en = 1;    //when dc input, reset sigma delta
    classd_config_ahb->pwm_reset_en = 0;   //when dc input, reset pwm
    classd_config_ahb->mi2s_chs = MI2S_OUTPUT_CHANNEL_DEFAULT; // how many channels to use
    classd_config_ahb->pwm_i2s_lrck_swap = 0;
    classd_config_ahb->pwm_i2s_sel = 2;  //0:mi2s_out_bclk 192k; 1:mi2s_out_bck 96k; 2: mi2s_out_bck 48k.
	classd_config_ahb->pwm_i2s_en = 1;   //1:enable bck of pwm and mi2s_out;

    DA_PP_CLASSD_CONFIG = classd_config_ahb_strc;

    U32 mi2s_config_strc = 0;
    mi2s_config_strc = MI2S_CONFIG;

    MI2S_CONFIG_AHB *mi2s_config_ahb;
    mi2s_config_ahb = (MI2S_CONFIG_AHB *) &mi2s_config_strc; 

    mi2s_config_ahb->mi2s_tx_enable= 1;
#ifdef AUDIO_24_BIT_OUTPUT	
    mi2s_config_ahb->mi2s_tx_24_bit = 1;
#else
    mi2s_config_ahb->mi2s_tx_24_bit = 0;
#endif
    mi2s_config_ahb->mi2s_tx_fmt = 0;
    mi2s_config_ahb->mi2s_lrck_tx_swap = 0;
    mi2s_config_ahb->mi2s_bck_div = 1;
    mi2s_config_ahb->mi2s_lrck_div = 1;


    #ifdef PWM_CH8_AS_LRCK_BCK_OF_MI2S_OUT //8P as mi2s_lrck_out; 8N as mi2s_bck_out
        
        classd_config_ahb_2->i2s_ch7_pwm_n_mux_en = 1;  // for i2s_pwm_mux_en = 1;
        GPIO_MUXFUNCTION_SELECT(AUDIO_PWM_8N, MUX_SEL_FUNCTION2); //8N: bck 0f mi2s_out
        GPIO_MUXFUNCTION_SELECT(AUDIO_PWM_8P, MUX_SEL_FUNCTION2); //8P: lrck of mi2s_out

        /*---------------- mi2s_out's data[0:3] config------------------------------  */
        #ifdef PWM_CH7_AS_MI2S_OUT_ANYONE_DATA
            classd_config_ahb_2->i2s_ch7_pwm_n_mux_en = 1; // pwm_7n as conditon of Mi2s_Dout
            classd_config_ahb_2->i2s_ch7_pwm_n_sel = 0;    // defination channel of output data; 0 = mi2s_Dout[0]; 1= mi2s_Dout[1]; 2=mi2s_Dout[2];3=mi2s_Dout[3].
            GPIO_MUXFUNCTION_SELECT(AUDIO_PWM_7N, MUX_SEL_FUNCTION2);
            #ifdef PWM_CH7P_AS_MI2S_OUT_ANYONE_DATA  //for 3-4 channels
            classd_config_ahb_2->i2s_ch7_pwm_p_mux_en = 1; // pwm_7p as conditon of Mi2s_Dout
            classd_config_ahb_2->i2s_ch7_pwm_p_sel = 1;
            GPIO_MUXFUNCTION_SELECT(AUDIO_PWM_7P, MUX_SEL_FUNCTION2);
            #endif 
          //classd_config_ahb_2->i2s_ch7_pwm_p_sel = 1;    // Dout[1] for 2.1 channels or 4.0 channels.  
            #ifdef PWM_CH6N_AS_MI2S_OUT_ANYONE_DATA  

            classd_config_ahb_2->i2s_ch7_ch8_pwm_disable = 0;
            classd_config_ahb_2->i2s_ch6_pwm_p_mux_en = 1; 
            classd_config_ahb_2->i2s_ch6_pwm_p_sel = 2;   //for 5-6 channels
            GPIO_MUXFUNCTION_SELECT(AUDIO_PWM_6P, MUX_SEL_FUNCTION2);
            #endif
          //app_gpio_MUXfunction_select(GPIO2_18_INDEX, MUX_SEL_FUNCTION2);
            #ifdef PWM_CH6P_AS_MI2S_OUT_ANYONE_DATA
            classd_config_ahb_2->i2s_ch7_ch8_pwm_disable = 0;
            classd_config_ahb_2->i2s_ch6_pwm_n_mux_en = 1;
            classd_config_ahb_2->i2s_ch6_pwm_n_sel = 3;   //for 7-8 channels
            GPIO_MUXFUNCTION_SELECT(AUDIO_PWM_6N, MUX_SEL_FUNCTION2);
            #endif
        #endif

        #ifdef PWM_CH4N_AS_MI2S_OUT_ANYONE_DATA
            classd_config_ahb_2->i2s_ch6_pwm_n_mux_en = 1;    //condition
            classd_config_ahb_2->i2s_ch7_ch8_pwm_disable = 1; //condition
            classd_config_ahb_2->i2s_ch6_pwm_n_sel = 2;       // Dout[2] for 5.1 channel 
            GPIO_MUXFUNCTION_SELECT(GPIO2_07_INDEX, MUX_SEL_FUNCTION1);
        #endif
        #ifdef PWM_CH4P_AS_MI2S_OUT_ANYONE_DATA
            classd_config_ahb_2->i2s_ch6_pwm_p_mux_en = 1;    //condition
            classd_config_ahb_2->i2s_ch7_ch8_pwm_disable = 1; //condition
            classd_config_ahb_2->i2s_ch6_pwm_p_sel = 3;       //Dout[3] for 7.1 channel
            GPIO_MUXFUNCTION_SELECT(GPIO2_06_INDEX, MUX_SEL_FUNCTION1);
        #endif

    #else /*pwm6chs as lrck and bck of mi2s_out*/ // only Dolby board v1.2 or OTK5285.
        classd_config_ahb_2->i2s_ch7_ch8_pwm_disable = 1;
        classd_config_ahb_2->i2s_ch6_pwm_p_mux_en = 1;   
        classd_config_ahb_2->i2s_ch6_pwm_n_mux_en = 1;   
        
        GPIO_MUXFUNCTION_SELECT(GPIO2_10_INDEX, MUX_SEL_FUNCTION1); //CH 6P as mi2s LRCK out
        GPIO_MUXFUNCTION_SELECT(GPIO2_11_INDEX, MUX_SEL_FUNCTION1); //CH 6N as mi2s BCLK out

        /*----------------------------------------------------------------------------*/
        /*---------------- mi2s_out's data[0:3] config only for Dolby board---------  */
        #ifdef PWM_CH7_AS_MI2S_OUT_ANYONE_DATA
            classd_config_ahb_2->i2s_ch7_pwm_p_mux_en = 1;
	        classd_config_ahb_2->i2s_ch7_pwm_n_mux_en = 1;

            classd_config_ahb_2->i2s_ch7_pwm_p_sel = 0; //Dout[0] or anyone of the Dout[0:3] 
            GPIO_MUXFUNCTION_SELECT(GPIO2_17_INDEX, MUX_SEL_FUNCTION2);

            classd_config_ahb_2->i2s_ch7_pwm_n_sel = 1; //Dout[1] or Dout[0:3]
            GPIO_MUXFUNCTION_SELECT(GPIO2_18_INDEX, MUX_SEL_FUNCTION2);
            

        #elif defined PWM_CH5_AS_MI2S_OUT_ANYONE_DATA

         /***** PWM5chs as Dout of Mi2s condition:  *****/
         //i2s_ch7_ch8_pwm_disable ==1  && i2s_ch7_pwm_p_mux_en ==1), //select CH 5P and 5N as mi2s_Dout.
		

            classd_config_ahb_2->i2s_ch7_pwm_p_mux_en = 1; 
            classd_config_ahb_2->i2s_ch7_pwm_n_mux_en = 1;

            classd_config_ahb_2->i2s_ch7_pwm_p_sel = 0; //Dout[0] or Dout[0:3]
            GPIO_MUXFUNCTION_SELECT(GPIO2_08_INDEX, MUX_SEL_FUNCTION1);

            classd_config_ahb_2->i2s_ch7_pwm_n_sel = 0; //Dout[1] or Dout[0:3]
            GPIO_MUXFUNCTION_SELECT(GPIO2_09_INDEX, MUX_SEL_FUNCTION1);

        #endif

        #ifdef PWM_CH4P_AS_MI2S_OUT_ANYONE_DATA
            classd_config_ahb_2->i2s_ch6_pwm_p_sel = 0; //Dout[2] or Dout[0:3]
            GPIO_MUXFUNCTION_SELECT(GPIO2_06_INDEX, MUX_SEL_FUNCTION1);
        #endif

        #ifdef PWM_CH4N_AS_MI2S_OUT_ANYONE_DATA
            classd_config_ahb_2->i2s_ch6_pwm_n_sel = 0; //Dout[1] or Dout[0:3]
            GPIO_MUXFUNCTION_SELECT(GPIO2_07_INDEX, MUX_SEL_FUNCTION1);
        #endif
   #endif

   MI2S_CONFIG = mi2s_config_strc;
#endif  


/*********************End of BCLK/LRCK/DATA[0:3] of the MI2S_Multi Dout***********/    
/************************************************************************************/

	DA_PP_CLASSD_CONFIG_AHB_2 = value;

	value = DA_PP_CLASSD_CONFIG_AHB_3;
	classd_config_ahb_3 = (CLASSD_CONFIG_AHB_3 *) &value;

    #ifndef OTK5286_B_D
	//only current of the PWM 1/2/3/4 can be adjusted, it is driving strength at 4.0ma-16ma range in 4.0mA/step.
    //classd_config_ahb_3->pwm_out_current = 0xFFFF;    //it can be selected from 4,8,12 and 16mA@3.3V
	//classd_config_ahb_3->pwm_out_current = 0xAAAA;	//and only channle 1/2/3/4 can be adjusted.
	//classd_config_ahb_3->pwm_out_current = 0x5555;    //min for headphone voice
    classd_config_ahb_3->pwm_out_current = 0x0000;    //min 4 mA /* each channel has 2bit parameters*/

    #elif (defined OTK5283P)
    classd_config_ahb_3->pwm_out_current = 0xFF00;    //min 4 mA /* each channel has 2bit parameters*/
    #else
    classd_config_ahb_3->pwm_out_current = 0x00FF;    //min 4 mA /* each channel has 2bit parameters*/
    #endif

    classd_config_ahb_3->pwm_out_mode = 0; //audio pwm out enable

	classd_config_ahb_3->pwm_mute = 0;

#ifdef AUDIO_PWM_MOSFET_OUT
	classd_config_ahb_3->pwm_dt_sel = 1;
#else
	classd_config_ahb_3->pwm_dt_sel = 0;
#endif

	DA_PP_CLASSD_CONFIG_AHB_3 = value;
#endif


#if 0
	DMIC_CONFIG_AHB *p_dmic_config;
    U16 tmp_u16;

	tmp_u16 = 0;
    p_dmic_config = (DMIC_CONFIG_AHB *) &tmp_u16;

    p_dmic_config->dmic_enable = 1;
    p_dmic_config->dmic_chan = 0;
    //p_dmic_config->dmic_bck_div = 1;// (CLK / 4 )
    p_dmic_config->dmic_bck_div = 3;// (CLK / 8 )
    p_dmic_config->dmci_minus_enable = 1;
    p_dmic_config->dmic_down_sample = 7;               //(11.2896/4)/9 = 176.4k
    //p_dmic_config->dmic_down_sample = 6;                //bypass

    DMIC_CONFIG = (U32) tmp_u16;  //0x79; //above structure can't work!
    //CLASSD_CONFIG_AHB_3 = 15;           //debug
    
	gpio0_SetFunction(GPIO3_MASK, FALSE);// DMIC data pin
	
#endif


#if 0//def DMIC_TEST

	//inial dma 3 
	DMA_3_SOURCE  = DA_DMIC_FIFO_ADDR;				//from map file

#ifdef DMA_BUF_INTERNAL
	DMA_3_DEST   = dma_buf;
	DMA_3_COUNT = dma_size;	
#else
	DMA_3_DEST   = 0x70000000;
	DMA_3_COUNT = (0x800000/4);					//from map file
#endif

	DMA_3_CNTR   = 0x2E2a | 0x80;		//dest inc, beat 8


	DMIC_CONFIG_AHB *p_dmic_config;
    U16 tmp_u16;

	tmp_u16 = 0;
    p_dmic_config = (DMIC_CONFIG_AHB *) &tmp_u16;

    p_dmic_config->dmic_enable = 1;
    p_dmic_config->dmic_chan = 0;
    p_dmic_config->dmic_bck_div = 1;
    p_dmic_config->dmci_minus_enable = 1;
    p_dmic_config->dmic_down_sample = 7;               //(11.2896/4)/9 = 176.4k
    //p_dmic_config->dmic_down_sample = 0;                //bypass

    DMIC_CONFIG = (U32) tmp_u16;  //0x79; //above structure can't work!

    //CLASSD_CONFIG_AHB_3 = 15;           //debug


			tmp = DMA_3_COUNT;
			if (tmp == 0) {

				DMA_3_SOURCE  = DA_DMIC_FIFO_ADDR;				//from map file

#ifdef DMA_BUF_INTERNAL
				DMA_3_DEST   = dma_buf;
				DMA_3_COUNT = dma_size;					//from map file

#else
				DMA_3_DEST   = 0x70000000;
				DMA_3_COUNT = (0x800000/4);					//from map file
#endif	//DMA_BUF_INTERNAL		
			}			 
#endif //I2S_STEREO_IN_ENABLE


	DMA_GLOBAL_CNTR = (0x00001000 | DMA_0_CHANNEL | DMA_1_CHANNEL |
		                   DMA_2_CHANNEL | DMA_4_CHANNEL | DMA_5_CHANNEL);

	DA_PP_MUTE_EN = 0;

	DA_PP_CLASSD_EN = 0x01; //classd enale
}


void da_pp_channel_setting(U8 channel)
{
	CLASSD_CONFIG_AHB *classd_config_ahb;
	volatile U32 temp;

	temp = DA_PP_CLASSD_CONFIG;

	classd_config_ahb = (CLASSD_CONFIG_AHB *)&temp;
	classd_config_ahb->mi2s_chs = channel;

	DA_PP_CLASSD_CONFIG = temp;
}


void i2sCd_i2s1_mi2sIn_config(void)
{
    U32 mi2s_config_strc = 0;
    U32 i2_cdconfig_strc = 0;
    U32 misc_audio_codec_controls_tmp = 0;
       
    mi2s_config_strc = MI2S_CONFIG;
    i2_cdconfig_strc  = CD_I2S_CONFIG;
    misc_audio_codec_controls_tmp = REG_MISC_AUDIO_CODEC;

    MI2S_CONFIG_AHB *mi2s_config_ahb;
    mi2s_config_ahb = (MI2S_CONFIG_AHB *) &mi2s_config_strc; 
       

    I2_CD_CONFIG_AHB *i2_cd_config_ahb;
    i2_cd_config_ahb = (I2_CD_CONFIG_AHB *) &i2_cdconfig_strc;


    MISC_AUDIO_CODEC_CONTROLs *misc_audio_codec_controls;
    misc_audio_codec_controls = (MISC_AUDIO_CODEC_CONTROLs *)&misc_audio_codec_controls_tmp;

#ifndef I2S1_MI2SIN_B_GROUP
     /***************only i2s_cd_enable = 0 for [B] group ***********/
     i2_cd_config_ahb->i2s_cd_enable = 1; /*always enalbe for reset of i2scd_i2s1_mi2sin*/

     #ifdef I2S1_MI2SIN_BCK_LRCK_OUT 
         i2_cd_config_ahb->i2s_cd_lrck_div = 0x1f;       
         i2_cd_config_ahb->i2s_cd_bck_div  = 0x01;
         i2_cd_config_ahb->i2s_cd_mode=1;  // output of bck/lrck; master mode for A group
     #else
         i2_cd_config_ahb->i2s_cd_mode=0;  // intput of bck and lrck; salve mode for A group
         i2_cd_config_ahb->i2s_cd_lrck_div = 0x0;       
         i2_cd_config_ahb->i2s_cd_bck_div  = 0x0; 
     #endif

     GPIO_MUXFUNCTION_SELECT(GPIO0_07_INDEX, MUX_SEL_FUNCTION1); //i2s_bck for i2s1,cd_i2s,mi2s Din.
     GPIO_MUXFUNCTION_SELECT(GPIO0_08_INDEX, MUX_SEL_FUNCTION1); //i2s_lrck for i2s1,cd_i2s,mi2s Din.


     #ifdef I2S1_SETEREO_ENABLE
            misc_audio_codec_controls->i2s_st_pin_sel = 1;  // 1 = A group, 0 = [B] group

           #ifdef I2S1_DATA_IN
    	       mi2s_config_ahb->mi2s_rx_enable = 1;

             
              #ifdef AUDIO_ADC_24BIT
                mi2s_config_ahb->mi2s_rx_24_bit = 1;  // 24 bit is selected
               #else
                mi2s_config_ahb->mi2s_rx_24_bit = 0;  // 16 bit is selected
               #endif

               GPIO_MUXFUNCTION_SELECT(GPIO0_05_INDEX, MUX_SEL_FUNCTION1); //stereo din
           #endif

           #ifdef I2S1_DATA_OUT
    	       mi2s_config_ahb->mi2s_tx_enable = 1;
               mi2s_config_ahb->mi2s_tx_24_bit = 1; 
	       	   GPIO_MUXFUNCTION_SELECT(GPIO0_06_INDEX, MUX_SEL_FUNCTION1); //stereo dout
		   #endif
     

     
      #elif defined I2S_CD_DATA_IN_ENABLE //CD_FUNCTION_ENABLE
           #ifndef I2S1_MI2SIN_BCK_LRCK_OUT
           //i2_cd_config_ahb->cd_mi2s_sel = 0;  // 0 for cd din; 1 for mi2s_din; fifo push_data.
           i2_cd_config_ahb->i2s_cd_24_bit = 0;  // when cd should be equal 0 for 16bit
           i2_cd_config_ahb->i2s_cd_fmt = 0;              
           i2_cd_config_ahb->i2s_cd_swap = 0;
           i2_cd_config_ahb->cdrom_en = 0; 
           i2_cd_config_ahb->cdrom_discramble= 0;
           i2_cd_config_ahb->cdrom_mode= 0;
           i2_cd_config_ahb->i2s_cd_bck_div = 0;
           i2_cd_config_ahb->i2s_cd_lrck_div = 0;
           mi2s_config_ahb->mi2s_rx_enable = 1;

           GPIO_MUXFUNCTION_SELECT(GPIO0_03_INDEX, MUX_SEL_FUNCTION1); //i2s_cd_din
           GPIO_MUXFUNCTION_SELECT(GPIO0_04_INDEX, MUX_SEL_FUNCTION1); //i2s_cd_ef       
           #endif
      #else  // for mi2s muliti-Din up to 4 data in
           
           #ifdef MI2SIN_MULTY_DATA_IN    // total support 4_data.
             i2_cd_config_ahb->cd_mi2s_sel = 1;  //0 for cd din; 1 for mi2s_din; fifo push_data.

             misc_audio_codec_controls->mi2sin_pin_sel = 0 ; // only for mi2sin_[B] group whe =1;
             mi2s_config_ahb->mi2s_rx_mode  = 0;             // =1 or 0 unmeaning
             mi2s_config_ahb->mi2s_bck_div  = 0;
             mi2s_config_ahb->mi2s_lrck_div = 0;

             i2_cd_config_ahb->mi2s_rcv_chan = 0;   // 0= stereo; 1= 4channels; 2=6channels; 3=8channels

             mi2s_config_ahb->mi2s_rx_enable = 1;
             mi2s_config_ahb->mi2s_rx_24_bit = 0;   // 0 =16 bit, 1 = 24 bit.

             GPIO_MUXFUNCTION_SELECT(GPIO0_03_INDEX, MUX_SEL_FUNCTION1);   //mi2s_data_in_a[0] 
             //app_gpio_MUXfunction_select(GPIO0_04_INDEX, MUX_SEL_FUNCTION1); //mi2s_data_in_a[1] 
             //app_gpio_MUXfunction_select(GPIO0_05_INDEX, MUX_SEL_FUNCTION1); //mi2s_data_in_a[2]
             //app_gpio_MUXfunction_select(GPIO0_06_INDEX, MUX_SEL_FUNCTION1); //mi2s_data_in_a[3]
           #endif
           
      #endif
      
#else // only for otk5283p/82p/82 i2s1_setero [B] group
      /***************only i2s_cd_enable = 0 for [B] group ***********/
      i2_cd_config_ahb->i2s_cd_enable = 0;              // =0  only for [B] group .
      //misc_audio_codec_controls->mi2sin_pin_sel = 1;  //=1 mi2sIn for [B]
      misc_audio_codec_controls->i2s_st_pin_sel = 0;    // 0= for i2s_[B] group

      #ifdef I2S1_MI2SIN_BCK_LRCK_OUT
 	      mi2s_config_ahb->mi2s_rx_mode  = 1;             // i2s1_[B] for master
  	      mi2s_config_ahb->mi2s_lrck_div = 0x1f;
  	      mi2s_config_ahb->mi2s_bck_div  = 0x01;
      #else
 	      mi2s_config_ahb->mi2s_rx_mode  = 0;             // i2s1_[B] for slave
 	      mi2s_config_ahb->mi2s_lrck_div = 0x0;
 	      mi2s_config_ahb->mi2s_bck_div  = 0x0;
      #endif
	  
 	      GPIO_MUXFUNCTION_SELECT(GPIO1_08_INDEX, MUX_SEL_FUNCTION1); //i2s_bck[B] 
 	      GPIO_MUXFUNCTION_SELECT(GPIO1_09_INDEX, MUX_SEL_FUNCTION1); //i2s lrck[B]

      #ifdef I2S1_DATA_IN
          mi2s_config_ahb->mi2s_rx_enable = 1;
          mi2s_config_ahb->mi2s_rx_24_bit = 0; 
          GPIO_MUXFUNCTION_SELECT(GPIO1_10_INDEX, MUX_SEL_FUNCTION1); //i2s1[B] Din
      #endif

      #ifdef I2S1_DATA_OUT
          //mi2s_config_ahb->mi2s_tx_fmt = 0; 
          //mi2s_config_ahb->mi2s_lrck_tx_swap = 0; 
	   	  mi2s_config_ahb->mi2s_tx_enable = 1;
		  
#ifdef AUDIO_24_BIT_OUTPUT
          mi2s_config_ahb->mi2s_tx_24_bit = 1; 
#else
          mi2s_config_ahb->mi2s_tx_24_bit = 0; 
#endif

		  
		  
          GPIO_MUXFUNCTION_SELECT(GPIO1_11_INDEX, MUX_SEL_FUNCTION1); //stereo dout
      #endif
#endif
    

    CD_I2S_CONFIG = i2_cdconfig_strc;
    REG_MISC_AUDIO_CODEC = misc_audio_codec_controls_tmp;
    MI2S_CONFIG = mi2s_config_strc;
}


/**The function of PWM pins disable is only close PWM out if all pins or portion of the audio_pwm_out */
/**is unused, that purpose is to reduce electromagnetic interference prepared by Leelin **/
//#define AUDIO_PWM_DESABLE_GPIO_OUT
void audio_pwm_out_pins_disable(U8 start_pin, U8 end_pin )
{
    
     U8 i,y,z;
     U32 mask1 = 0;
     U32 mask  = 0;
     
     if(start_pin >= AUDIO_PWM_1P && end_pin <= AUDIO_PWM_6N ) 
     {
          z = end_pin - start_pin + 1 ;

          if (z % 2 == 0 ) //to avoid the MOSFET is burned that use pwm direct driver MOSFET amplifier.
          {                //if full in is wrong by user.
               y = start_pin -= 64;
               
               for(i= 0; i< z; i++)
               {

                    mask1  = 1 << y++;   
                    mask  +=    mask1;
               }

               REG_GPIO2_FUNC &= ~mask;             //gpioFunc2 = 0, priority 1(if)
    	       REG_GPIO3_FUNC &= ~(mask<<16);       //gpioFunc3 = 0, priority 2(else if); gpio is else.

               #ifdef AUDIO_PWM_DESABLE_GPIO_OUT    //gpio2 output gpio_low
                       
                   REG_GPIO2_IE   &= ~mask;          //gpio2_input_Enable =0,
			       REG_GPIO2_DOE  |=  mask;          //gpio2_output =1,

                   REG_GPIO2_DOUT &= ~mask;          // Output Low.

               #else   //gpio input
                   
			       REG_GPIO2_DOE  &= ~mask;
		           REG_GPIO2_IE   |=  mask;
               #endif
               //DBG_Printf("audio_pwm_out_pins_disable has been run \n\r");
          }
			  
          else
          {
               DBG_Printf("failure of audio_pwm_out_pins_disable \n\r");
          }
     }

     else
     {  
        return 0;
     }
}

void da_pp_classd_config_ahb3(U16 pwm_out_current,U16 pwm_out_select,U8 pwm_out_mode)
{
    #if 1

    CLASSD_CONFIG_AHB_3 *classd_config_ahb_3;
    U32 value = DA_PP_CLASSD_CONFIG_AHB_3;
	classd_config_ahb_3 = (CLASSD_CONFIG_AHB_3 *) &value;
    U16 temp;
    U16 tmp1;
    U8  tmp2;

    #ifdef OTK5286_B_D
       temp = 0x00;
    #else
       temp = pwm_out_current;
    #endif

    tmp1 = pwm_out_select;
    tmp2 = pwm_out_mode;
    
    classd_config_ahb_3->pwm_out_current = temp & tmp1;
    classd_config_ahb_3->pwm_out_mode = tmp2;

    classd_config_ahb_3->pwm_mute = 0x0;

    #ifdef AUDIO_PWM_MOSFET_OUT
	classd_config_ahb_3->pwm_dt_sel = 1;
    #else
	classd_config_ahb_3->pwm_dt_sel = 0;
    #endif

	DA_PP_CLASSD_CONFIG_AHB_3 = value;

    #endif

}

void audio_pwm_out_standby(U8 enable)
{

    CLASSD_CONFIG_AHB_3 *classd_config_ahb_3;
    U32 value = DA_PP_CLASSD_CONFIG_AHB_3;
	classd_config_ahb_3 = (CLASSD_CONFIG_AHB_3 *) &value;

   if(enable == 1)
   {
     classd_config_ahb_3->pwm_mute = 0xF;

   }
   else
   {

     classd_config_ahb_3->pwm_mute = 0x0;

   }

    DA_PP_CLASSD_CONFIG_AHB_3 = value;

}