hw_dma.h
7.61 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
#ifndef _HW_DMA_H
#define _HW_DMA_H
#define DMA_CONFIG_BASE_ADDR 0x12000000
#define DMA0_BASE_ADDR (DMA_CONFIG_BASE_ADDR)
#define DMA1_BASE_ADDR (DMA_CONFIG_BASE_ADDR + 32 * 1)
#define DMA2_BASE_ADDR (DMA_CONFIG_BASE_ADDR + 32 * 2)
#define DMA3_BASE_ADDR (DMA_CONFIG_BASE_ADDR + 32 * 3)
#define DMA4_BASE_ADDR (DMA_CONFIG_BASE_ADDR + 32 * 4)
#define DMA5_BASE_ADDR (DMA_CONFIG_BASE_ADDR + 32 * 5)
#define DMA6_BASE_ADDR (DMA_CONFIG_BASE_ADDR + 32 * 6)
#define DMA7_BASE_ADDR (DMA_CONFIG_BASE_ADDR + 32 * 7)
#define DMA8_BASE_ADDR (DMA_CONFIG_BASE_ADDR + 32 * 8)
#define DMA9_BASE_ADDR (DMA_CONFIG_BASE_ADDR + 32 * 9)
#define DMA_0_SOURCE REG(DMA_CONFIG_BASE_ADDR)
#define DMA_0_DEST REG(DMA_CONFIG_BASE_ADDR + 8)
#define DMA_0_COUNT REG(DMA_CONFIG_BASE_ADDR + 16)
#define DMA_0_CNTR REG(DMA_CONFIG_BASE_ADDR+24)
#define DMA_1_SOURCE REG( DMA_CONFIG_BASE_ADDR + 32 * 1)
#define DMA_1_DEST REG(DMA_CONFIG_BASE_ADDR + 32 * 1 + 8)
#define DMA_1_COUNT REG(DMA_CONFIG_BASE_ADDR + 32 * 1 + 16)
#define DMA_1_CNTR REG(DMA_CONFIG_BASE_ADDR+ 32 * 1 + 24)
#define DMA_2_SOURCE REG(DMA_CONFIG_BASE_ADDR + 32 * 2)
#define DMA_2_DEST REG(DMA_CONFIG_BASE_ADDR + 32 * 2 + 8)
#define DMA_2_COUNT REG(DMA_CONFIG_BASE_ADDR + 32 * 2 + 16)
#define DMA_2_CNTR REG(DMA_CONFIG_BASE_ADDR+ 32 * 2 + 24)
#define DMA_3_SOURCE REG(DMA_CONFIG_BASE_ADDR + 32 * 3)
#define DMA_3_DEST REG(DMA_CONFIG_BASE_ADDR + 32 * 3 + 8)
#define DMA_3_COUNT REG(DMA_CONFIG_BASE_ADDR + 32 * 3 + 16)
#define DMA_3_CNTR REG(DMA_CONFIG_BASE_ADDR+ 32 * 3 + 24)
#define DMA_4_SOURCE REG(DMA_CONFIG_BASE_ADDR + 32 * 4)
#define DMA_4_DEST REG(DMA_CONFIG_BASE_ADDR + 32 * 4 + 8)
#define DMA_4_COUNT REG(DMA_CONFIG_BASE_ADDR + 32 * 4 + 16)
#define DMA_4_CNTR REG(DMA_CONFIG_BASE_ADDR+ 32 * 4 + 24)
#define DMA_5_SOURCE REG(DMA_CONFIG_BASE_ADDR + 32 * 5)
#define DMA_5_DEST REG(DMA_CONFIG_BASE_ADDR + 32 * 5 + 8)
#define DMA_5_COUNT REG(DMA_CONFIG_BASE_ADDR + 32 * 5 + 16)
#define DMA_5_CNTR REG(DMA_CONFIG_BASE_ADDR+ 32 * 5 + 24)
#define DMA_6_SOURCE REG(DMA_CONFIG_BASE_ADDR + 32 * 6)
#define DMA_6_DEST REG(DMA_CONFIG_BASE_ADDR + 32 * 6 + 8)
#define DMA_6_COUNT REG(DMA_CONFIG_BASE_ADDR + 32 * 6 + 16)
#define DMA_6_CNTR REG(DMA_CONFIG_BASE_ADDR+ 32 * 6 + 24)
#define DMA_7_SOURCE REG(DMA_CONFIG_BASE_ADDR + 32 * 7)
#define DMA_7_DEST REG(DMA_CONFIG_BASE_ADDR + 32 * 7 + 8)
#define DMA_7_COUNT REG(DMA_CONFIG_BASE_ADDR + 32 * 7 + 16)
#define DMA_7_CNTR REG(DMA_CONFIG_BASE_ADDR+ 32 * 7 + 24)
#define DMA_8_SOURCE REG(DMA_CONFIG_BASE_ADDR + 32 * 8)
#define DMA_8_DEST REG(DMA_CONFIG_BASE_ADDR + 32 * 8 + 8)
#define DMA_8_COUNT REG(DMA_CONFIG_BASE_ADDR + 32 * 8 + 16)
#define DMA_8_CNTR REG(DMA_CONFIG_BASE_ADDR+ 32 * 8 + 24)
#define DMA_9_SOURCE REG(DMA_CONFIG_BASE_ADDR + 32 * 9)
#define DMA_9_DEST REG(DMA_CONFIG_BASE_ADDR + 32 * 9 + 8)
#define DMA_9_COUNT REG(DMA_CONFIG_BASE_ADDR + 32 * 9 + 16)
#define DMA_9_CNTR REG(DMA_CONFIG_BASE_ADDR+ 32 * 9 + 24)
#define DMA_GCNTR REG(DMA_CONFIG_BASE_ADDR+ 32 * 12)
typedef volatile struct {
u32 size :3;
u32 burst_size :3;
u32 saddr_inc :1;
u32 daddr_inc :1;
u32 source :4;
u32 start :1;
u32 channel_enb :1;
u32 int_enb :1;
}DMA_CNTRs;
#define DMA_TRANS_8BITS 0
#define DMA_TRANS_16BITS 1
#define DMA_TRANS_32BITS 2
#define DMA_TRANSMIT_SIZE_BYTE 0
#define DMA_TRANSMIT_SIZE_HALFWORD 1
#define DMA_TRANSMIT_SIZE_WORD 2
#define DMA_BURST_SINGLE 0
#define DMA_BURST_FOUR 3
#define DMA_BURST_EIGHT 5
#define DMA_BURST_SIXTEEN 7
#define DMA_SRC_ADDR_FIXED 0
#define DMA_SRC_ADDR_INC 1
#define DMA_DEST_ADDR_FIXED 0
#define DMA_DEST_ADDR_INC 1
//#define DMA_BURST_SINGLE 0
#define DMA_BURST_4 (3<<3)
#define DMA_BURST_8 (5<<3)
#define DMA_BURST_16 (7<<3)
#define DMA_SOURCE_FIXED 0
#define DMA_SOURCE_INC (1<<6)
#define DMA_DEST_FIXED 0
#define DMA_DEST_INC (1<<7)
#define DMA_SOURCE(A) (A<<8)
#define DMA_NO_SOFT_START 0
#define DMA_SOFTWARE_START (1<<12)
#define DMA_CHANNEL_DISABLE 0
#define DMA_CHANNEL_ENABLE (1<<13)
#define DMA_CHANNEL_INT_DISABLE 0
#define DMA_CHANNEL_INT_ENABLE (1<<14)
#define DMA_CHANNEL0_ENABLE (DMA_0_CNTR|= bit13)
#define DMA_CHANNEL0_DISENABLE (DMA_0_CNTR &= ~bit13)
#define DMA_CHANNEL1_ENABLE (DMA_1_CNTR|= bit13)
#define DMA_CHANNEL1_DISENABLE (DMA_1_CNTR &= ~bit13)
#define BURST_SINGLE 0
#define BURST_FOUR 3
#define BURST_EIGHT 5
#define BURST_SIXTEEN 7
#define ADDR_FIXED 0
#define ADDR_INC 1
//I2S
#define SOURCE_DMA0 0
#define SOURCE_DMA1 1
#define SOURCE_DMA2 2
#define SOURCE_DMA3 3
//LCD
#define SOURCE_DMA4 4
//USB
#define SOURCE_DMA5 5
#define SOURCE_DMA6 6
//SD
#define SOURCE_DMA7 7
#define SOURCE_DMA8 8
//jpeg
#define SOURCE_DMA9 9
#define SOURCE_DMA10 10
#define SOURCE_DMA11 11
#define SOURCE_DMA12 12
#define SOURCE_DMA13 13
#define SOURCE_DMA14 14
#define SOURCE_DMA15 15
//OTK526x DMA hardware connection
#define SOURCE_DMA_IIS0_IN 1
#define SOURCE_DMA_ADC 2
#define SOURCE_DMA_IIS1_IN 3
#define SOURCE_DMA_DA_PP 4
#define SOURCE_DMA_SPDIF_IN 5
#define SOURCE_DMA_IIS1_OUT 6
#define SOURCE_DMA_SD_WR 7
#define SOURCE_DMA_SD_RD 8
#define SOURCE_DMA_UART_0_TX 9
#define SOURCE_DMA_UART_0_RX 10
#define SOURCE_DMA_SPI_TX 11
#define SOURCE_DMA_SPI_RX 12
#define SOURCE_DMA_SPDIF_DAC_OUT 13
#define SOURCE_DMA_DIGIT_MIC_IN 14
#define DMA_STOP 0
#define DMA_START 1
#define CHANNEL_DISENB 0
#define CHANNEL_ENB 1
//----------------------------------------------------------------------------------
#define DMA_GLOBAL_CNTR REG(DMA_CONFIG_BASE_ADDR + 32*12)
#define DMA_0_CHANNEL 0x0001
#define DMA_1_CHANNEL 0x0002
#define DMA_2_CHANNEL 0x0004
#define DMA_3_CHANNEL 0x0008
#define DMA_4_CHANNEL 0x0010
#define DMA_5_CHANNEL 0x0020
#define DMA_6_CHANNEL 0x0040
#define DMA_7_CHANNEL 0x0080
#define DMA_8_CHANNEL 0x0100
#define DMA_9_CHANNEL 0x0200
void Dma_Init(void);
//void DMA_Channel1_Init(U32 *dest, U32 *src, U32 byte_count);
//void DMA_Channel2_Init(U32 *dest, U32 *src, U32 byte_count);
//OTK526x
//dma 0 for da_pp or iis1 tx
void DMA_Channel0_Init(U32 *dest, U32 *src, U32 byte_count, U8 dma_source);
void DMA_Channel0_Disable(void);
//dma 1 for iis0, iis1 in or spdif in
void DMA_Channel1_Init(U32 *dest, U32 *src, U32 byte_count, U8 dma_source);
void DMA_Channel1_Disable(void);
//dma 2 for adc or iis1 in
void DMA_Channel2_Init(U32 *dest, U32 *src, U32 byte_count, U8 dma_source);
void DMA_Channel2_Disable(void);
#ifdef OPTEK_DSP_MX1
//dma 0 for da_pp or iis1 tx
void DMA_Channel3_Init(U32 *dest, U32 *src, U32 byte_count, U8 dma_source);
void DMA_Channel3_Disable(void);
#endif
void DMA_Channel4_Init(U32 *dest, U32 *src, U32 byte_count, U8 dma_source);
void DMA_Channel4_Disable(void);
void DMA_Channel5_Init(U32 *dest, U32 *src, U32 byte_count, U8 dma_source);
void DMA_Channel5_Disable(void);
void DMA_Channel6_Init(U32 *dest, U32 *src, U32 byte_count, U8 dma_source);
void DMA_Channel6_Disable(void);
void dma_transf_init(u32 *reg, u32 *sou, u32 *dest, u32 len);
void dma_transf_contrl_set(u32 *p,u8 b_sizes, BOOL sInc, BOOL dInc, u8 trig);
void DMA_Channel9_Init(U32 *dest, U32 *src, U32 byte_count, U8 dma_source);
void DMA_Channel9_Disable(void);
#endif //_HW_DMA_H