hw_da_pp.h
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#ifndef DA_PP_H
#define DA_PP_H
#include "flash_boot.h"
#if 1
#define AUDIO_PWM_OUTPUT /*close it that is audio code HP output, vice veasa audio pwm output*/
#endif
#ifdef AUDIO_PWM_OUTPUT
//#define AUDIO_PWM_MOSFET_OUT //for audio PWM P/N channel MOSFET output, it must be defined
#endif
#define PWM_HALF_BRIDGE
#ifdef AUDIO_PWM_OUTPUT
#undef AUDIO_HEADPHONE_OUTPUT
#else
#define AUDIO_HEADPHONE_OUTPUT
#endif
/************************Here is only for i2s section including mi2s_out, mi2s_in and i2s1*************/
#define MI2S_OUTPUT_CHANNEL_DEFAULT 0//0: 2 channels; 1: 4 channels; 2: 6 chans; 3: 8 channels
#define IIS_MCLK1_OUT_ENABLE
/************************Here is Mi2s out **********************************/
//#define MI2S_OUT_ENABLE
#ifdef MI2S_OUT_ENABLE
/*** pwm8_chs and pwm7_chs are combined with SDRAM pins***/
// #define PWM_CH8_AS_LRCK_BCK_OF_MI2S_OUT
// #define PWM_CH7_AS_MI2S_OUT_ANYONE_DATA
/********************************************************/
#define PWM_CH5_AS_MI2S_OUT_ANYONE_DATA
//#define PWM_CH4P_AS_MI2S_OUT_ANYONE_DATA
//#define PWM_CH4N_AS_MI2S_OUT_ANYONE_DATA
#endif
/************************End of Mi2s out ***********************************/
/***********************Here is Mi2s_in and i2s1 ***************************/
//#define I2SCD_I2S1_MI2SIN_ENABLE
#ifdef I2SCD_I2S1_MI2SIN_ENABLE
//#define I2S1_MI2SIN_B_GROUP /* only for OTK5282/83/P */
#define I2S1_MI2SIN_BCK_LRCK_OUT //Outdead: #define I2S1_BCK_LRCK_OUT
#define I2S1_DATA_OUT
#define I2S1_DATA_IN
#define I2S1_SETEREO_ENABLE
//#define I2S_CD_DATA_IN_ENABLE
//#define MI2SIN_MULTY_DATA_IN
#endif
#if 1 //Here is not changed.
#ifdef I2S1_SETEREO_ENABLE
#undef I2S_CD_DATA_IN_ENABLE
#undef MI2SIN_MULTY_DATA_IN
#undef DMA_AUDIO_FROM_CD_OR_MI2SIN
#endif
#ifdef MI2SIN_MULTY_DATA_IN
#define DMA_AUDIO_FROM_CD_OR_MI2SIN
#undef I2S1_SETEREO_ENABLE
#undef I2S1_DATA_OUT
#undef I2S1_DATA_IN
#undef I2S_CD_DATA_IN_ENABLE
#endif
#ifdef I2S_CD_DATA_IN_ENABLE
#define DMA_AUDIO_FROM_CD_OR_MI2SIN
#undef I2S1_SETEREO_ENABLE
#undef MI2SIN_MULTY_DATA_IN
#undef I2S1_MI2SIN_BCK_LRCK_OUT
#undef I2S1_DATA_OUT
#endif
#ifndef I2SCD_I2S1_MI2SIN_ENABLE
#ifndef MI2S_OUT_ENABLE
#undef IIS_MCLK1_OUT_ENABLE
#endif
#endif
#endif
/***************************End of Mi2s in and i2s1 ***************************/
//digital audio post processing
//need more study with rtl
#define DA_PP_BASE_ADDR 0x13000000
#define DA_PP_CLASSD_FIFO_ADDR 0x13000400
#define DA_SPDIF_IN_FIFO_ADDR 0x13000800
#define DA_SPDIF_OUT_FIFO_ADDR 0x13000800 //DMA 13 same with spdif in, onr read, one write
#define DA_ADC_IN_FIFO_ADDR 0x13000C00
#define DA_I2S_IN_FIFO_ADDR 0x13001400
#define DA_I2S_OUT_FIFO_ADDR 0x13001800
#define DA_CD_IN_FIFO_ADDR 0x13001000
#define DA_DMIC_FIFO_ADDR 0x13001C00 //DMA 14
/*
`define CLASSD_FIFO_ADDR 13'b0_0100_0000_0000 //12'h400
`define SPDIF_FIFO_ADDR 13'b0_1000_0000_0000
`define ADC_I2S_ADDR 13'b0_1100_0000_0000
`define CD_I2S_ADDR 13'b1_0000_0000_0000
`define I2S_RX_ADDR 13'b1_0100_0000_0000
`define I2S_TX_ADDR 13'b1_1000_0000_0000
`define DMIC_ADDR 13'b1_1100_0000_0000
*/
/*
#define DA_PP_CLASSD_EN *( (volatile U32 *) (void *) (DA_PP_BASE_ADDR + 4*72))
#define DA_PP_MUTE_EN *( (volatile U32 *) (void *) (DA_PP_BASE_ADDR + 4*73))
#define DA_PP_CLASSD_CONFIG *( (volatile U32 *) (void *) (DA_PP_BASE_ADDR + 4*74))
#define DA_PP_PWM_CONFIG *( (volatile U32 *) (void *) (DA_PP_BASE_ADDR + 4*75))
#define DA_PP_CH1_CH2_DRC_ATTACK2RELEASE_T *( (volatile U32 *) (void *) (DA_PP_BASE_ADDR + 4*76))
#define DA_PP_CH1_CH2_DRC_RELEASE_T *( (volatile U32 *) (void *) (DA_PP_BASE_ADDR + 4*77))
#define DA_PP_CH3_CH4_DRC_ATTACK2RELEASE_T *( (volatile U32 *) (void *) (DA_PP_BASE_ADDR + 4*78))
#define DA_PP_CH3_CH4_DRC_RELEASE_T *( (volatile U32 *) (void *) (DA_PP_BASE_ADDR + 4*79))
#define DA_PP_EQ_PARS_VALID *( (volatile U32 *) (void *) (DA_PP_BASE_ADDR + 4*80))
*/
#define DA_PP_CLASSD_EN *( (volatile U32 *) (void *) (DA_PP_BASE_ADDR + 4*0))
#define DA_PP_MUTE_EN *( (volatile U32 *) (void *) (DA_PP_BASE_ADDR + 4*1))
#define DA_PP_CLASSD_CONFIG *( (volatile U32 *) (void *) (DA_PP_BASE_ADDR + 4*2))
#define DA_PP_CLASSD_CONFIG_AHB_2 *( (volatile U32 *) (void *) (DA_PP_BASE_ADDR + 4*3))
#define SPDIF_CONFIG *( (volatile U32 *) (void *) (DA_PP_BASE_ADDR + 4*4))
#define SPDIF_ENC_STATUS_L *( (volatile U32 *) (void *) (DA_PP_BASE_ADDR + 4*5))
#define SPDIF_ENC_STATUS_H *( (volatile U32 *) (void *) (DA_PP_BASE_ADDR + 4*6))
#define SPDIF_DEC_SAMPLE_RATE_DETECT *( (volatile U32 *) (void *) (DA_PP_BASE_ADDR + 4*7))
#define MI2S_CONFIG *( (volatile U32 *) (void *) (DA_PP_BASE_ADDR + 4*8))
#define CD_I2S_CONFIG *( (volatile U32 *) (void *) (DA_PP_BASE_ADDR + 4*9))
#define DMIC_CONFIG *( (volatile U32 *) (void *) (DA_PP_BASE_ADDR + 4*13))
#define DA_PP_CLASSD_CONFIG_AHB_3 *( (volatile U32 *) (void *) (DA_PP_BASE_ADDR + 4*15))
typedef volatile struct{
U32 mi2s_tx_enable : 1; //mi2s_config_ahb [0];
U32 mi2s_rx_enable : 1; //mi2s_config_ahb [1];
U32 mi2s_tx_24_bit : 1; //mi2s_config_ahb [2];
U32 mi2s_rx_24_bit : 1; //mi2s_config_ahb [3];
U32 mi2s_tx_fmt : 1; //mi2s_config_ahb [4];
U32 mi2s_rx_fmt : 1; //mi2s_config_ahb [5];
U32 mi2s_lrck_tx_swap : 1; //mi2s_config_ahb [6];
U32 mi2s_lrck_rx_swap : 1; //mi2s_config_ahb [7];
U32 mi2s_bck_div : 4; //mi2s_config_ahb [11:8];
U32 mi2s_lrck_div : 6; //mi2s_config_ahb [17:12];
//U32 mi2s_tx_bits : ; //mi2s_config_ahb [19:18];
//U32 mi2s_tx_mode : ; //mi2s_config_ahb [20];
U32 reserved : 3;
U32 mi2s_rx_mode : 1; //mi2s_config_ahb [21]; /*1'b1 mater mode, 1'b0 slave mode*/
//U32 i2s_stereo_data_in_sel : 3; //mi2s_config_ahb [24:22];
//U32 mi2s_tx_sel : 1; //mi2s_config_ahb [25];
} MI2S_CONFIG_AHB;
//i2_cd_config_ahb
typedef volatile struct{
U32 i2s_cd_enable : 1; //i2_cd_config_ahb[0];
U32 i2s_cd_mode : 1; //i2_cd_config_ahb[1]; // slave:0; master:1;
U32 i2s_cd_24_bit : 1; //i2_cd_config_ahb[2];
U32 i2s_cd_fmt : 1; //i2_cd_config_ahb[3];
U32 i2s_cd_swap : 1; //i2_cd_config_ahb[4]; //for cd right justify, high is left, for i2s, low is left
U32 cdrom_en : 1; //i2_cd_config_ahb[5];
U32 cdrom_discramble : 1; //i2_cd_config_ahb[6];
U32 cdrom_mode : 2; //i2_cd_config_ahb[8:7];
U32 i2s_cd_bck_div : 4; //i2_cd_config_ahb[12:9];
U32 i2s_cd_lrck_div : 6; //i2_cd_config_ahb[18:13];
U32 mi2s_rcv_chan : 2; //i2_cd_config_ahb[20:19]; //2'b00:2,2b01:4,2'b10:6,2'b11:8
U32 cd_mi2s_sel : 1; //i2_cd_config_ahb[21]; 0 cd in, 1 mi2s in
} I2_CD_CONFIG_AHB;
typedef volatile struct {
U32 classd_data_24_bit : 1;// classd_config_ahb[0];
U32 classd_6db : 1;// classd_config_ahb[1];
U32 pp_clk_config : 2;// classd_config_ahb [3:2];
U32 osr_config : 2;// classd_config_ahb [5:4];
U32 stream_type : 2;// classd_config_ahb [7:6];
U32 sigma_delta_quan : 4;// classd_config_ahb [11:8];
U32 sigma_delta_order : 2;// classd_config_ahb [13:12]; //no user now
U32 sd_reset_en : 1;// classd_config_ahb [14];
U32 pwm_inv : 1;// classd_config_ahb [15];
U32 mi2s_da_pp_n : 1;// classd_config_ahb [16];
U32 mi2s_chs : 2;// classd_config_ahb [18:17]; //2'b00:2,2b01:4,2'b10:6,2'b11:8
U32 classd_clk_err_en : 1;// classd_config_ahb [19];
U32 reserved : 1;
U32 pwm_delay : 6;// classd_config_ahb [26:21];
U32 pwm_i2s_lrck_swap : 1;// classd_config_ahb [27];
U32 pwm_i2s_sel : 2;// classd_config_ahb [29:28];
U32 pwm_i2s_en : 1;// classd_config_ahb [30];
U32 pwm_reset_en : 1;// classd_config_ahb [31];
} CLASSD_CONFIG_AHB;
/*
assign i2s_ch7_ch8_pwm_disable = classd_config_ahb_2[19];
assign i2s_ch7_pwm_p_mux_en = classd_config_ahb_2[20];
assign i2s_ch7_pwm_n_mux_en = classd_config_ahb_2[21];
assign i2s_ch6_pwm_p_mux_en = classd_config_ahb_2[22];
assign i2s_ch6_pwm_n_mux_en = classd_config_ahb_2[23];
assign i2s_ch7_pwm_p_sel = classd_config_ahb_2[25:24];
assign i2s_ch7_pwm_n_sel = classd_config_ahb_2[27:26];
assign i2s_ch6_pwm_p_sel = classd_config_ahb_2[29:28];
assign i2s_ch6_pwm_n_sel = classd_config_ahb_2[31:30];
*/
//pwm config
typedef volatile struct {
U32 pwm_adjust_t : 4;// classd_config_ahb_2[`DRV_ADJUST_BITS-1:0];
U32 pwm_drv_pre_deadt : 4;// classd_config_ahb_2[(`DRV_ADJUST_BITS+`DRV_DEAD_BITS-1):`DRV_ADJUST_BITS];
U32 pwm_drv_post_deadt : 4;// classd_config_ahb_2[(`DRV_ADJUST_BITS+`DRV_DEAD_BITS+`DRV_DEAD_BITS-1):(`DRV_ADJUST_BITS+`DRV_DEAD_BITS)];
U32 pwm_min_t : 5;// classd_config_ahb_2[(`DRV_ADJUST_BITS+`DRV_DEAD_BITS+`DRV_DEAD_BITS+`DRV_ADJUST_BITS-1):(`DRV_ADJUST_BITS+`DRV_DEAD_BITS+`DRV_DEAD_BITS)];
U32 resv : 2;
U32 i2s_ch7_ch8_pwm_disable : 1;
U32 i2s_ch7_pwm_p_mux_en : 1;
U32 i2s_ch7_pwm_n_mux_en : 1;
U32 i2s_ch6_pwm_p_mux_en : 1;
U32 i2s_ch6_pwm_n_mux_en : 1;
U32 i2s_ch7_pwm_p_sel : 2;
U32 i2s_ch7_pwm_n_sel : 2;
U32 i2s_ch6_pwm_p_sel : 2; //0:MI2S_D0; 1:MI2S_D1, 2:MI2S_D2; 3:MI2S_D3
U32 i2s_ch6_pwm_n_sel : 2;
} CLASSD_CONFIG_AHB_2;
typedef volatile struct {
U32 pwm_out_current : 16; //classd_config_ahb_3[15:0];
U32 pwm_out_mode : 4; //classd_config_ahb_3[19:16];
U32 pwm_mute : 4; //classd_config_ahb_3 [23:20];
U32 pwm_dt_sel : 1; //classd_config_ahb_3 [24];
} CLASSD_CONFIG_AHB_3;
// only for audio pwm_out 1P-4N
#define PWM_OUT_CURRENT_04mA 0x0000
#define PWM_OUT_CURRENT_08mA 0x5555
#define PWM_OUT_CURRENT_12mA 0xAAAA
#define PWM_OUT_CURRENT_16mA 0xFFFF
#define PWM_OUT_SELECT_1P1N 0x0F<<0
#define PWM_OUT_SELECT_2P2N 0x0F<<1
#define PWM_OUT_SELECT_3P3N 0x0F<<2
#define PWM_OUT_SELECT_4P4N 0x0F<<3
#define PWM_OUT_SELECT_1P2N 0xFF<<0
#define PWM_OUT_SELECT_3P4N 0xFF<<1
#define PWM_OUT_SELECT_ELSE 0
//*** [19:16] for OUT_MODE ***//
#define PWM_OUT_MODE_ON_ALL 0x0
#define PWM_OUT_MODE_ONLY_1P2N 0xE
#define PWM_OUT_MODE_ONLY_3P4N 0xD
#define PWM_OUT_MODE_ONLY_5P6N 0xB
#define PWM_OUT_MODE_ONLY_7P8N 0x7
#define PWM_OUT_MODE_OFF_ALL 0xF
#define PWM_OUT_MUTE_1P2N 1
#define PWM_OUT_MUTE_3P4N 2
#define PWM_OUT_MUTE_5P6N 4
#define PWM_OUT_MUTE_7P8N 8
/*
assign spdif_enc_enable = spdif_config_ahb [0];
assign spdif_dec_enable = spdif_config_ahb [1];
assign spdif_data_sel = spdif_config_ahb [3:2];
assign spdif_enc_inv = spdif_config_ahb [5];
assign spdif_dec_inv = spdif_config_ahb [6];
assign spdif_dec_sr_detect_start = spdif_config_ahb [8];
assign spdif_dec_aux_mask = spdif_config_ahb [9];
assign sync_err_auto_recover = spdif_config_ahb [10];
assign spdif_enc_data_24b = spdif_config_ahb [11];
assign dac_lrck_swap = spdif_config_ahb [12];
assign spdif_enc_stream = spdif_config_ahb [14:13];//adjust dac out phase with pwm output
assign spdif_enc_sample_delay = spdif_config_ahb[20:15];
assign dac_enable = spdif_config_ahb [21];
assign adc_enable = spdif_config_ahb [22];
assign adc_bck_div = spdif_config_ahb [26:23];
assign adc_i2s_24bit = spdif_config_ahb [27];
assign adc_lrck_swap = spdif_config_ahb [28];
assign sample_tx_sel = spdif_config_ahb [29];
assign sample_rx_sel = spdif_config_ahb [30];
assign spdif_dec_data_16b = spdif_config_ahb[31];
*/
typedef volatile struct {
U32 spdif_enc_enable : 1;// classd_config_ahb[0]
U32 spdif_dec_enable : 1;// classd_config_ahb[1]
U32 spdif_data_sel : 2;// classd_config_ahb [3:2]
U32 rsv_1 : 1;
U32 spdif_enc_inv : 1;
U32 spdif_dec_inv : 1;
U32 adc_slave : 1; //soc is adc slave
U32 spdif_dec_sr_detect_start : 1;// classd_config_ahb [8]
U32 spdif_dec_aux_mask : 1;// classd_config_ahb [9]
U32 sync_err_auto_recover : 1;// classd_config_ahb [10]
U32 spdif_enc_data_24b : 1;// classd_config_ahb [11]
U32 dac_lrck_swap : 1;// classd_config_ahb [12]
U32 spdif_enc_stream : 2;// classd_config_ahb [14:13], 2'b00:2,2b01:4,2'b10:6,2'b11:8
U32 spdif_enc_sample_delay : 6;//spdif_config_ahb[20:15]
U32 dac_enable : 1;// classd_config_ahb [21]
U32 adc_enable : 1; //spdif_config_ahb[22]
U32 adc_bck_div : 4; //spdif_config_ahb [26:23]
U32 adc_i2s_24bit : 1;// classd_config_ahb [27]
U32 adc_lrck_swap : 1;// classd_config_ahb [28]
U32 sample_tx_sel : 1;// classd_config_ahb [29]
U32 sample_rx_sel : 1; // classd_config_ahb [30]
U32 spdif_dec_data_16b : 1; // classd_config_ahb [31]
} SPDIF_CONFIG_AHB;
/*
assign dmic_enable = dmic_config[0];
assign dmic_chan = dmic_config[2:1];
assign dmci_minus_enable = dmic_config[3];
assign dmic_bck_div = dmic_config[7:4];
assign dmic_down_sample = dmic_config [13:8];
assign dmic_clk_sel = dmic_config [14];
*/
typedef volatile struct {
U16 dmic_enable :1;
U16 dmic_chan :2;//0,2 mics; 1, 4 mics; 2, 6 mics, 3, 8mics
U16 dmci_minus_enable :1;
U16 dmic_bck_div :4;
U16 dmic_down_sample :6;
U16 dmic_clk_sel :1;//0 mclk, 1 ahb clk
} DMIC_CONFIG_AHB;
void i2sCd_i2s1_mi2sIn_config(void);
void da_pp_channel_setting( U8 );
void audio_pwm_out_pins_disable(U8 start_pin, U8 end_pin );
void da_pp_classd_config_ahb3(U16 pwm_out_current,U16 pwm_out_select,U8 pwm_out_mode);
void audio_pwm_out_standby(U8 enable);
#define AUDIO_PWM_1P GPIO2_00_INDEX
#define AUDIO_PWM_1N GPIO2_01_INDEX
#define AUDIO_PWM_2P GPIO2_02_INDEX
#define AUDIO_PWM_2N GPIO2_03_INDEX
#define AUDIO_PWM_3P GPIO2_04_INDEX
#define AUDIO_PWM_3N GPIO2_05_INDEX
#define AUDIO_PWM_4P GPIO2_06_INDEX
#define AUDIO_PWM_4N GPIO2_07_INDEX
#define AUDIO_PWM_5P GPIO2_08_INDEX
#define AUDIO_PWM_5N GPIO2_09_INDEX
#define AUDIO_PWM_6P GPIO2_10_INDEX
#define AUDIO_PWM_6N GPIO2_11_INDEX
#define AUDIO_PWM_7P GPIO2_18_INDEX
#define AUDIO_PWM_7N GPIO2_17_INDEX
#define AUDIO_PWM_8P GPIO2_16_INDEX
#define AUDIO_PWM_8N GPIO2_15_INDEX
#define AUDIO_PWM_OUT_PINS_DISABLE(START_PIN,END_PIN) audio_pwm_out_pins_disable(START_PIN,END_PIN)
#define PWM_OUT_CURRENT_AND_PIN_SEL(pwm_out_current,pwm_out_select,pwm_out_mode) da_pp_classd_config_ahb3(pwm_out_current,pwm_out_select,pwm_out_mode);
#endif