/*
** Copyright (C) 2001 Optek. All rights reserved.
**
** The information and source code contained herein is the exclusive
** property of Mediamatics and may  not be disclosed, examined or
** reproduced in whole or in part without explicit written authorization
** from the company.
*/

/*
** Author:
**
** Date: 2/03/2001
**
** Description: Audio Codec Interface.
** 
*/

#include "os_config.h"

#include "c_def.h"
#include "debug.h"
#include "oem.h"


#if 1//def MP3CD

#include "regmap.h"

#include "hw_dma.h"
#include "hw_iis.h"
#include "hw_spdif.h"
#include "hw_da_pp.h"
//#include "audio_pll.h"
#include "hw_codec.h"
#include "interrupt.h"
#include "hw_pll.h"

#include "mem_reloc.h"
#include "message.h"
#include "app_sdram.h"
#include "app_main.h"
#include "app_timer.h"
#include "audio_dec.h"
#include "app_dac.h"
#include "app_cmd.h"
#include "fifo.h"
#include "tools.h"
#include "codec.h"
#include "hw_dma.h"
#include <string.h>
#include "flash_boot.h"

#ifndef FREE_RTOS_DEBUG
/* FreeRTOS includes. */
#include "FreeRTOS.h"
#include "task.h"
#include "timers.h"
#include "event_groups.h"
#endif

#if	(defined USB_SPEAKER || defined USB_DEV_ENABLE)
#include "denumAudio.h"
#include "daudio.h"
#endif
#include "hw_timer.h"

#include "optek_link.h"

void SoftInt0Isr(void)              __INTERNAL_RAM_TEXT;
void SoftInt1Isr(void)              __INTERNAL_RAM_TEXT;
void SoftInt2Isr(void)              __INTERNAL_RAM_TEXT;
void SoftInt3Isr(void)              __INTERNAL_RAM_TEXT;
void SoftInt4Isr(void)              __INTERNAL_RAM_TEXT;

void Dma_0_TransmitIsr(void)         __INTERNAL_RAM_TEXT;
void Dma_8_TransmitIsr(void)         __INTERNAL_RAM_TEXT;
void Dma_2_RcvIsr(void)              __INTERNAL_RAM_TEXT;
void Dma_3_RcvIsr (void)			 __INTERNAL_RAM_TEXT;
void Dma_1_PCM_ReceiveIsr(void)      __INTERNAL_RAM_TEXT;
void Dma_3_PCM_ReceiveIsr(void)      __INTERNAL_RAM_TEXT;
void Dma_2_TransmitIsr(void)         __INTERNAL_RAM_TEXT;
void taskStream_Rcv(void *pvParameters) __INTERNAL_RAM_TEXT;
//void app_dac_init_for_latency (U32 samples) __INTERNAL_RAM_TEXT;

#if 1//def DOLBY_AC3_DEC
#define Zero_Buf_Size    240//(128*3) //about 1.45ms
#else
#define Zero_Buf_Size    (128*1) //about 1.45ms
#endif


U8 uiDoubleBufferIndex;

#ifdef SYSTEM_CRASH_CHECK_ENABLE
volatile U8 dma2_tx_int_check;
#endif

/*II2S*/


BOOL uiDacMute;
BOOL uiAdcMute;
BOOL uiCdservoMute;
U8 audio_iso_mute;

U8 audio_out_mode;

FIFO AdcInFifo;


#ifdef USB_HOST_AUDIO_ENABLE
FIFO MicInFifo;//JJ+ for USB MIC
U8 micFifo_buf[MIC_FIFO_BUF_SIZE];
#endif


AWOUTSTORE awOutStore __attribute__(( aligned (16) ));
AWOUT_CONTRLS awOut_contrls;//make sure that when buffer pointer pwBuf not ready wSize must equal to 0

AWINSTORE awInStore __attribute__(( aligned (64) ));//__attribute__ ((section (".stream_memory_bss")));//__attribute__(( aligned (16) ));

/*
#ifdef PCM_RECEIVE_ENABLE
#define PCM_TRANSMIT_DEMO
U32 pcmRcvSample[2][CD_DA_SECTOR_SIZE / 4]	__attribute__ ((section (".sdram_bss")));
U8 pcmRcvIndex;
#endif*/


#define DAC_OUT_FRAME_SZIE (240*2*4)


U8 pcmRcvIndex;

void app_dac_init (void)
{
	memset((void*)awOutStore.awOutSampleStore[0],0,sizeof(awOutStore.awOutSampleStore[0]));

#ifdef OPTEK_DSP_MX1
	mix1_init();
#endif

#ifdef I2S1_DATA_OUT
	DMA_Channel0_Init((U32 *)DA_I2S_OUT_FIFO_ADDR,   (U32 *)awOutStore.awOutSampleStore[0], DAC_OUT_FRAME_SZIE/4, SOURCE_DMA_IIS1_OUT);
	#ifndef OPL_MODE_WIRELESS_MIC
	if (app_main_data.share_link_role == SL_ROLE_SLAVE)
		DMA_Channel8_Init((U32 *)DA_SPDIF_OUT_FIFO_ADDR, (U32 *)awOutStore.awOutSampleStore[0], DAC_OUT_FRAME_SZIE/4, SOURCE_DMA_SPDIF_DAC_OUT);
	#endif
#else
#ifdef AUDIO_PWM_OUTPUT
	DMA_Channel0_Init((U32 *)DA_PP_CLASSD_FIFO_ADDR, (U32 *)awOutStore.awOutSampleStore[0], DAC_OUT_FRAME_SZIE/4, SOURCE_DMA_DA_PP);
	#ifndef OPL_MODE_WIRELESS_MIC
	if (app_main_data.share_link_role == SL_ROLE_SLAVE)
		DMA_Channel8_Init((U32 *)DA_SPDIF_OUT_FIFO_ADDR, (U32 *)awOutStore.awOutSampleStore[0], DAC_OUT_FRAME_SZIE/4, SOURCE_DMA_SPDIF_DAC_OUT);
	#endif
#else
	DMA_Channel0_Init((U32 *)DA_SPDIF_OUT_FIFO_ADDR, (U32 *)awOutStore.awOutSampleStore[0], DAC_OUT_FRAME_SZIE/4, SOURCE_DMA_SPDIF_DAC_OUT);
	#ifndef OPL_MODE_WIRELESS_MIC
	if (app_main_data.share_link_role == SL_ROLE_SLAVE)
		DMA_Channel8_Init((U32 *)DA_PP_CLASSD_FIFO_ADDR, (U32 *)awOutStore.awOutSampleStore[0], DAC_OUT_FRAME_SZIE/4, SOURCE_DMA_DA_PP);
	#endif
#endif //AUDIO_PWM_OUTPUT
#endif //I2S1_DATA_OUT

	awOut_contrls.awIndex = 1;
	awOut_contrls.awSize = 0;

	audio_out_mode = AUDIO_OUT_L_R;

#ifdef SPDIF_ENABLE
	SOFT2_INT_ENABLE; //DMA 1
#endif

	//dma transfer enable, clear dma flag
#ifdef OPTEK_DSP_MX1
	DMA_GLOBAL_CNTR = (0x00001000 | DMA_0_CHANNEL | DMA_2_CHANNEL | DMA_3_CHANNEL);
#else
	DMA_GLOBAL_CNTR = (0x00001000 | DMA_0_CHANNEL | DMA_2_CHANNEL);
#endif

	if (app_main_data.share_link_role == SL_ROLE_SLAVE)	
		DMA_GLOBAL_CNTR |= (DMA_9_CHANNEL | DMA_8_CHANNEL);
}


void IIS_1_reset(void);

void app_output_reset (void)
{
#ifdef AUDIO_OUT_FROM_I2S1
    IIS_1_reset();
#endif

//	da_pp_close();
//	da_pp_open ();
//	da_pp_eq_init();
}

void app_dac_open (void)
{
}

void app_dac_close (void)
{
}

void app_dac_fini (void)
{
}

void app_dac_outbuf_init (void)
{
	return;

#if 0
	int i;

	/*only be called in dac mute state*/
	//DBG_Assert (uiDacMute == TRUE);

	memset((void *)awOutStore.awOutSampleStore[0], 0, sizeof(awOutStore));

	memset((void *)sDacOutIsrBuf, 0, sizeof(sDacOutIsrBuf));
		
	/*Please note the in/out sequence is 1,0,1,0*/
	//wDacInIndex = 1;
	//DACOUTISRBUF_from_DEC = 0;
#endif
}

void app_dac_mute_enable (void)
{
	uiDacMute = TRUE;

}

void app_dac_mute_disable (void)
{
#if 1//def MP3CD
	//memset((void *) awOutStore.awOutSampleStore[0], 0, sizeof(awOutStore));

	if (!app_main_data.Mute)
	{
		//AMPLIFIER_MUTE_OFF;

#if defined AUDIO_CODEC_USED_VOL
		//AUDIOdevice.Set_Volume(app_main_data.volume);
#elif defined AUDIO_AMP_USED_VOL
		//audioAmp_Dev.Set_Volume(app_main_data.volume);
#endif
	}

	uiDacMute = FALSE;

#ifdef ADC_RECORD
#ifdef CD_KARAOKE_REC_ENABLE
	uiAdcMute = FALSE;
#endif
#endif

#endif
}

void app_adc_mute_enable (void)
{
	uiAdcMute = TRUE;
}

void app_adc_mute_disable (void)
{
	U16 i, j;

	//memset((void *)awInSampleStore, 0, sizeof(awInSampleStore));
	//memset((void *) awOutStore.awOutSampleStore[0], 0, sizeof(awOutStore));

	/*Please note the in/out sequence is 1,0,1,0*/
	//wDacInIndex = 1;
	//DACOUTISRBUF_from_DEC = 0;

	//memset((void *)sDacOutIsrBuf, 0, sizeof(sDacOutIsrBuf));

	//uiDoubleBufferIndex = 0;

#ifdef ADC_RECORD
#ifdef CD_KARAOKE_REC_ENABLE
	uiDoubleBufferIndex_1 = 0;
#endif
#endif

	uiAdcMute = FALSE;
}

void app_audio_iso_rcv_enable (void)
{
	audio_iso_mute = FALSE;
}

void app_audio_iso_rcv_disable (void)
{
	audio_iso_mute = TRUE;
}


void app_adc_receive_disable (void)
{
#ifdef PCM_RECEIVE_ENABLE

#if 1
	//IIS1_Rx_Disable();
	//DMA_Channel3_Disable();
	DMA_Channel2_Disable();
#else
/*
#ifdef IIS0_RX_ENABLE
	IIS0_Rx_Disable();
	DMA_Channel1_Disable();
#else
	IIS1_Rx_Disable();
	DMA_Channel3_Disable();
#endif
*/
#endif

#endif
}

void app_adc_receive_enable (void)
{
#if 0
#ifdef PCM_RECEIVE_ENABLE

#ifdef IIS0_RX_ENABLE
	U32 *pDmaSrc = (U32 *)&I2S0_RX_DATA_REG;
#else
	U32 *pDmaSrc = (U32 *)&I2S1_RX_DATA_REG;
#endif

	uiDoubleBufferIndex = 0;

#ifdef ADC_RECORD
#ifdef CD_KARAOKE_REC_ENABLE
	uiDoubleBufferIndex_1 = 0;
#endif
#endif

#ifdef IIS0_RX_ENABLE
	IIS0_Rx_Enable ();
	//DMA_Channel1_Init((U32 *)awOutStore.awOutSampleStore[uiDoubleBufferIndex], pDmaSrc, MP3_DEC_FRAME_SIZE/2);
#else
	IIS1_Rx_Enable ();
	//DMA_Channel3_Init((U32 *)awOutStore.awOutSampleStore[uiDoubleBufferIndex], pDmaSrc, MP3_DEC_FRAME_SIZE/2);
#endif
#endif //PCM_RECEIVE_ENABLE
#endif
}

void app_dac_adc_fifo_init(void)
{
	fifo_init (&AdcInFifo, awInStore.awInSampleStore1[0], ADC_IN_FIFO_SIZE,TRUE);
}

void app_dac_receive_pcm_enable(U8 con)
{
	//TX_INTERRUPT_SAVE_AREA;
	U32 *pDmaSrc;
	U32 *pDmaDest;
	U32 DmaSel;

	if (con)
	{
		clear_decode_data_rev_event();
		fifo_init (&AdcInFifo, awInStore.awInSampleStore1[0], ADC_IN_FIFO_SIZE,TRUE);			
		memset((void *)awInStore.awInSampleStore1[0], 0, ADC_IN_FIFO_SIZE);
		pDmaDest = (U32 *)awInStore.awInSampleStore1[0];
				
		#ifdef OPL_SLAVE_ENBALE	
		if (app_main_data.share_link_role == SL_ROLE_SLAVE)
		{
		#ifdef DMA_AUDIO_FROM_CD_OR_MI2SIN 
			pDmaSrc = (U32 *)DA_CD_IN_FIFO_ADDR;
			DmaSel = SOURCE_DMA_IIS0_IN;
		#elif defined I2S1_DATA_IN//AUDIO_IN_FROM_I2S1
			pDmaSrc = (U32 *)DA_I2S_IN_FIFO_ADDR;
			DmaSel = SOURCE_DMA_IIS1_IN;
		#else
			pDmaSrc = (U32 *)DA_ADC_IN_FIFO_ADDR;
			DmaSel = SOURCE_DMA_ADC;
		#endif

			if (optek_link_mode == GAME_HEADPHONE_PT7P5MS_T7R3E || optek_link_mode == BC_SF48K_PT7P5MS)
				DMA_Channel2_Init(pDmaDest, pDmaSrc,48*5+48, DmaSel);
			else		
				DMA_Channel2_Init(pDmaDest, pDmaSrc,48*3+48, DmaSel);
		}
		else
		#endif
		{
		#ifdef DMA_AUDIO_FROM_CD_OR_MI2SIN 
			pDmaSrc = (U32 *)DA_CD_IN_FIFO_ADDR;
			DmaSel = SOURCE_DMA_IIS0_IN;
		#elif defined I2S1_DATA_IN//AUDIO_IN_FROM_I2S1
			pDmaSrc = (U32 *)DA_I2S_IN_FIFO_ADDR;
			DmaSel = SOURCE_DMA_IIS1_IN;
		#else
			pDmaSrc = (U32 *)DA_ADC_IN_FIFO_ADDR;
			DmaSel = SOURCE_DMA_ADC;
		#endif
			#ifdef OPL_MODE_SWF
				DMA_Channel2_Init(pDmaDest, pDmaSrc, 16*5+48, DmaSel);
			#else	
			if (optek_link_mode == GAME_HEADPHONE_PT7P5MS_T7R3E || optek_link_mode == BC_SF48K_PT7P5MS)
		    	DMA_Channel2_Init(pDmaDest, pDmaSrc, 16*11+48, DmaSel);
		    else		
				DMA_Channel2_Init(pDmaDest, pDmaSrc, 16*5+48, DmaSel);
			#endif	
		}
	}
	else
	{
		DMA_Channel2_Disable();
	}
}

void app_dac_receive_pcm_enable_1(U8 con)
{
#ifdef PCM_RECEIVE_ENABLE
	if (con)
	{
		pcmRcvFlag = TRUE;
	}
	else
	{
		pcmRcvFlag = FALSE;
	}
#endif
}

U8 tran_path;
//DMA channle 0 is fixed for tx
void Dma_0_TransmitIsr(void)
{
	U16 len;
	int *pBuf,i;

	#ifndef OPL_MODE_WIRELESS_MIC
	if (app_main_data.share_link_role == SL_ROLE_SLAVE)
	{
		DMA_8_COUNT = 0;
		DMA_8_COUNT = 0;
		DMA_8_COUNT = 0;
		DMA_8_COUNT = 0;							
		DMA_8_SOURCE = (int *) &awOutStore.awOutSampleStore[0][0]; //Source address
		DMA_8_COUNT = DMA_UNDERFLOW_DELAY_COUNT;	
	}
	else
	#endif
	{
		//if (decode_type == DECODE_PCM || app_main_data.share_link_role != SL_ROLE_BT)
		//	return;

		if (awOut_contrls.awSize)
		{
			len = awOut_contrls.awSize; //int size

			DMA_0_SOURCE = (int *) &awOutStore.awOutSampleStore[awOut_contrls.awIndex][0]; //Source address
			DMA_0_COUNT = len;

			/*Clear the previous out data*/
			awOut_contrls.awIndex = 1-awOut_contrls.awIndex;
			awOut_contrls.awSize = 0;
		}
		else
		{	
			//no dec/dapp data
			pBuf = (int *) &awOutStore.awOutSampleStore[1-awOut_contrls.awIndex][0];
			for (i=0;i<Zero_Buf_Size*2/4;i++) {
				*pBuf++ = 0;
				*pBuf++ = 0;
				*pBuf++ = 0;
				*pBuf++ = 0;
			}

			DMA_0_SOURCE = (int *) &awOutStore.awOutSampleStore[1-awOut_contrls.awIndex][0]; //Source address
			DMA_0_COUNT = Zero_Buf_Size*2;
		}
		
		SOFT3_INT_SET;
	}
}

static int dma8src[4] = {0,0,0,0};
void Dma_8_TransmitIsr (void)
{
	U16 len;
	int *pBuf,i;


	if (DMA_0_COUNT == 0)
	{
		if (awOut_contrls.awSize)
		{
			len = awOut_contrls.awSize; //int size

			DMA_0_SOURCE = (int *) &awOutStore.awOutSampleStore[awOut_contrls.awIndex][0]; //Source address
			DMA_0_COUNT = len;

			DMA_8_SOURCE = dma8src;//(int *) &awOutStore.awOutSampleStore[0][0];
			DMA_8_COUNT = len - TRANS_PART2_COUNT;

			/*Clear the previous out data*/
			awOut_contrls.awIndex = 1-awOut_contrls.awIndex;
			awOut_contrls.awSize = 0;
		}
		else
		{	
			//no dec/dapp data
			pBuf = (int *) &awOutStore.awOutSampleStore[1-awOut_contrls.awIndex][0];
			for (i=0;i<Zero_Buf_Size*2/4;i++) {
				*pBuf++ = 0;
				*pBuf++ = 0;
				*pBuf++ = 0;
				*pBuf++ = 0;
			}

			DMA_0_SOURCE = (int *) &awOutStore.awOutSampleStore[1-awOut_contrls.awIndex][0]; //Source address
			DMA_0_COUNT = Zero_Buf_Size*2;

			DMA_8_SOURCE = dma8src;//(int *) &awOutStore.awOutSampleStore[0][0];
			DMA_8_COUNT = Zero_Buf_Size*2 - TRANS_PART2_COUNT;			
		}		
	}
	else
	{		
		SOFT3_INT_SET;

		DMA_8_SOURCE = dma8src;//(int *) &awOutStore.awOutSampleStore[0][0];
		DMA_8_COUNT = (TRANS_PART1_COUNT + TRANS_PART2_COUNT)*2;
	}
}

extern volatile U32 devfirst_ccount,hcountms,devcur_ccount;
extern U32 frame_count;
extern int decode_type;
void Dma_2_RcvIsr (void)
{
	U16 index;
	TX_INTERRUPT_SAVE_AREA;

#ifdef SPDIF_ENABLE

	devcur_ccount = read_ccount();
	hcountms += 5;

	if (devfirst_ccount == 0)
	{
		devfirst_ccount = devcur_ccount;
		hcountms = 0;
	}

	if ( (decode_type == DECODE_SPDIF) ||
		(decode_type == DECODE_DD_AC3) || 
		(decode_type == DECODE_PCM) || 
		(decode_type == DECODE_LC3))
	{

		{

			uiDoubleBufferIndex = ( 1 - uiDoubleBufferIndex );
			
			//DMA_2_SOURCE = (U32*)DA_SPDIF_IN_FIFO_ADDR;						//Source address
			DMA_2_DEST = (U32)awInStore.awInSampleStore1[uiDoubleBufferIndex];		//Dest address
			
			if ((decode_type == DECODE_SPDIF) ||
				(decode_type == DECODE_DD_AC3))
			{
				DMA_2_COUNT = SPDIF_FRAME_SIZE/4;				
			}
			else
			{
				DMA_2_COUNT = dec_frame_size/4;
			}
			
			//TX_DISABLE;
			SOFT2_INT_SET;
			//TX_RESTORE;

		}
	}
	else
#endif
	{
		DMA_2_DEST = (U32 *)awInStore.awInSampleStore1[0];
		DMA_2_COUNT = ADC_IN_FIFO_SIZE/4;
	}
}

/*******************************************************************************
 *
 *   FUNCTION NAME - SoftInt2Isr
 *
 *   ARGUMENTS     - None
 *
 *   RETURN VALUE  - None
 *
 *******************************************************************************
 *
 *   DESCRIPTION
 *       This function handles the Software Interrupt 2, which is triggered by
 *       either of the PDIR1Full or PDIR2Full ISRs when they collect one
 *       complete sector. It clears the interrupt source and then posts a
 *       message to the waiting task to say that a sector has been collected
 *       for processing. This ISR also handles the error case when no CDROM
 *       sector sync has been found for a period of time. 
 *
 ******************************************************************************/

void SoftInt2Isr (void)
{
	int ret;

	SOFT2_INT_CLR;

	if (decode_type == DECODE_PCM || decode_type == DECODE_LC3)
	{
		ret = xEventGroupSetBitsFromISR(event_grop, AUDIO_DECODE_EVENT2, NULL);
		if( ret == pdTRUE )
		{
			portYIELD_FROM_ISR();
		}			
	}
	else
	{
	#ifdef SPDIF_ENABLE
		uiStreamSend(STREAM_SOURCE_SPDIF, (void *)(awInStore.awInSampleStore1[1 - uiDoubleBufferIndex]),
					SPDIF_FRAME_SIZE);
	#endif
	}
}

U8* wait_decode_data(void)
{

	//xEventGroupWaitBits(event_grop, AUDIO_DECODE_EVENT2, pdTRUE, pdFALSE, portMAX_DELAY);

	if ((xEventGroupWaitBits(event_grop, AUDIO_DECODE_EVENT2, pdTRUE, pdFALSE, 10) & AUDIO_DECODE_EVENT2) == AUDIO_DECODE_EVENT2)
	{
		return (U8*)awInStore.awInSampleStore1[1 - uiDoubleBufferIndex];
	}
	else
	{
		return NULL;
	}
}

void clear_decode_data_rev_event(void)
{
	xEventGroupWaitBits(event_grop, AUDIO_DECODE_EVENT2, pdTRUE, pdTRUE, 0);
}

#ifdef UART0_TX_DMA
void SoftInt0Isr (void)
{
	SOFT0_INT_CLR;

	UART0_TX_EVENT_iSET; //uart0 tx ready
}
#endif //UART0_TX_DMA

#ifdef UART0_RX_DMA
extern FIFO *pHcipUartRcvFifo;
void bt_hci_h4_sync_check (void);

void SoftInt1Isr (void)
{
	U32 *pUart0Dest;
	
	SOFT1_INT_CLR;

#if 1
	pUart0Dest = DMA_4_DEST; //current fifo write address
	fifo_put_data_by_dma (pHcipUartRcvFifo, pUart0Dest);
#endif

	bt_hci_h4_sync_check ();

	UART0_RX_EVENT_iSET; //uart0 rx polling
}
#endif //UART0_RX_DMA


#ifdef SPDIF_ENABLE

void Spdif_rcv_enable(void)
{
	U32 *pDmaSrc;

	spdif_dec_disable (); //reset fifo
	delayms (10);

	app_adc_mute_disable();

	pDmaSrc = (U32)DA_SPDIF_IN_FIFO_ADDR;
	DMA_Channel2_Init((U32 *)awInStore.awInSampleStore1[uiDoubleBufferIndex], pDmaSrc, SPDIF_FRAME_SIZE/4, SOURCE_DMA_SPDIF_IN);

	spdif_dec_enable ();

#ifdef USB_HOST_AUDIO_ENABLE
	if (usbd_get_usbhost_audio_device_status())
	{
		usbhost_audio_device_src_setting();
	}
#endif
}

void Spdif_rcv_disable(void)
{
	DMA_Channel2_Disable();
}

void taskStream_Rcv(void *pvParameters)
{
	U32 data[WIDTH_OF_STREAM_RCV_QUEUE];
	STREAM_MSG *msg = (STREAM_MSG *)data;

	while(1)
	{
		QUEUE_STREAM_RCV_RECEIVE;
		
		if (msg->source == STREAM_SOURCE_SPDIF)
		{
			spdif_rx( (U8 *) msg->buffer, msg->length);
		}
	}
}
#endif
/*******************************************************************************
 *
 *   FUNCTION NAME - SoftInt3Isr
 *
 *   ARGUMENTS     - None
 *
 *   RETURN VALUE  - None
 *
 *******************************************************************************
 *
 *   DESCRIPTION
 *       This function handles the Software Interrupt 3, which is triggered
 *       when one full frame has been transmitted.
 *       It clears the interrupt source and then sets a kernel event for
 *       the waiting decoder task, so that task can wake up and process the
 *       next frame.
 *
 ******************************************************************************/

void SoftInt3Isr (void)
{
	SOFT3_INT_CLR;
}


#ifdef OPTEK_DSP_MX1
#include "../dsp/echo_reverb/optek_mic_processing_collection.h"

#include "../dsp/echo_reverb/optek_hifi2_echo_reverb.h"
#include "peak_level_meter.h"

peak_level_det mic_peak_44p1K;

U32 *pMicInSampleStore;
U32 MicInSampleStoreSize;

U32 micRecStore[1152*3 / 4];//for mic in

FIFO MicInFifo;
U8 mic_opened = FALSE;

void mix1_init(void)
{
	if (app_main_data.share_link_role == SL_ROLE_SLAVE)
	{
		mic_opened = FALSE;		
		return;
	}
	if (1)//(app_main_data.media== MEDIA_AUX)
	{
		//pMicInSampleStore = awInStore.awInSampleStore2[0];
		//MicInSampleStoreSize = sizeof(awInStore.awInSampleStore2);
		pMicInSampleStore = micRecStore;
		MicInSampleStoreSize = sizeof(micRecStore);		
	}
	else
	{
		pMicInSampleStore = &awInStore;
		MicInSampleStoreSize = sizeof(awInStore);
	}

	app_dac_receive_mic_enable(true);

#ifdef MIC_REVERB
	optek_hifi2_reverb_init();
#endif

#ifdef MIC_DODGE_ENABLE
	optek_mic_dodge_init();
	optek_mic_dodge_open();
#endif

	peak_level_meter_16bit_open(&mic_peak_44p1K,PEAK_UPDATA_SAMPLES_44P1k);
	
	mic_opened = TRUE;
}

void mix1_init_reuse_audio_in_buf(void)
{
	pMicInSampleStore = awInStore.awInSampleStore1[0];
	MicInSampleStoreSize = sizeof(awInStore);
	app_dac_receive_mic_enable(true);

#ifdef MIC_REVERB
	optek_hifi2_reverb_init();
#endif

#ifdef MIC_DODGE_ENABLE
	optek_mic_dodge_init();
	optek_mic_dodge_open();
#endif

	peak_level_meter_16bit_open(&mic_peak_44p1K,PEAK_UPDATA_SAMPLES_44P1k);
	
	mic_opened = TRUE;
}

void app_dac_receive_mic_enable(U8 con)
{
	U32 *pDmaDest;
	U32 *pDmaSrc;
	
	if (con)
	{
		fifo_init (&MicInFifo, pMicInSampleStore, MicInSampleStoreSize, TRUE);

#ifdef MIC_ECHO
		optek_hifi2_echo_init();
#endif		

		pDmaDest = (U32 *)pMicInSampleStore;

#ifndef I2S1_DATA_IN
		pDmaSrc = (U32 *)DA_I2S_IN_FIFO_ADDR;
		DMA_Channel3_Init(pDmaDest, pDmaSrc, MicInSampleStoreSize/4, SOURCE_DMA_IIS1_IN);
#else
		pDmaSrc = (U32 *)DA_ADC_IN_FIFO_ADDR;
		DMA_Channel3_Init(pDmaDest, pDmaSrc, MicInSampleStoreSize/4, SOURCE_DMA_ADC);	
#endif
	}
	else
	{
#if 0
		app_dac_mute_enable ();
		pcmRcvFlag = FALSE;
#endif

		DMA_Channel3_Disable();
	}
}
//DMA 3 for MIC rx 
void Dma_3_RcvIsr (void)
{
	DMA_3_DEST = (U32 *)pMicInSampleStore;
	DMA_3_COUNT = MicInSampleStoreSize/4;
}
#else
void Dma_3_RcvIsr (void)
{
}
#endif //OPTEK_DSP_MX1

#endif