hw_iis.h
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#ifndef IIS_H
#define IIS_H
enum {
IIS_MCLK1,
IIS_MCLK2,
};
enum {
IIS_MCLK_OUT,
IIS_MCLK_INPUT,
};
#define IIS_MCLK1_PIN GPIO0_00_INDEX
#define IIS_MCLK2_PIN GPIO2_06_INDEX
#define IIS_LRCK_PIN GPIO2_10_INDEX
#define IIS_BCLK_PIN GPIO2_11_INDEX
#define I2S_DATA_IN_PIN GPIO3_MASK
#define CD_EF_PIN GPIO24_MASK
#define I2S0_BCK_PIN GPIO20_MASK
#define I2S0_LRCK_PIN GPIO21_MASK
#define I2S0_DATA_IN_PIN GPIO22_MASK
#define I2S0_DATA_OUT_PIN GPIO23_MASK
#define I2S1_BCK_PIN GPIO26_MASK
#define I2S1_LRCK_PIN GPIO27_MASK
#define I2S1_DATA_IN_PIN GPIO25_MASK
#define I2S1_DATA_OUT_PIN GPIO25_MASK
#define I2S2_BCK_PIN GPIO30_MASK
#define I2S2_LRCK_PIN GPIO31_MASK
#define I2S2_DATA_IN_PIN GPIO22_MASK
#define I2S2_DATA_OUT_PIN GPIO22_MASK
//IIS
#define I2S_DATA0_IN_PIN GPIO22_MASK
#define I2S_DATA0_OUT_PIN GPIO22_MASK //for IIS2 output
//IIS 0
#define I2S_DATA1_IN_PIN GPIO23_MASK
#define I2S_DATA1_OUT_PIN GPIO23_MASK
//IIS 1
#define I2S_DATA2_IN_PIN GPIO28_MASK
#define I2S_DATA2_OUT_PIN GPIO28_MASK //for IIS2 output(subwof)
#define I2S_DATA3_IN_PIN GPIO29_MASK
#define I2S_DATA3_OUT_PIN GPIO29_MASK
#define I2S_DATA4_IN_PIN GPIO25_MASK
#define I2S_DATA4_OUT_PIN GPIO25_MASK //for IIS1 output
//144 pins
#define I2S_DATA5_IN_PIN GPIO3_MASK
//#define I2S_DATA5_OUT_PIN
#define AUDIO_CH1_PWM_P_PIN GPIO84_MASK //GROUP 2[20]
#define AUDIO_CH1_PWM_N_PIN GPIO85_MASK //GROUP 2[21]
#define AUDIO_CH2_PWM_P_PIN GPIO86_MASK //GROUP 2[22]
#define AUDIO_CH2_PWM_N_PIN GPIO87_MASK //GROUP 2[23]
#define AUDIO_CH3_PWM_P_PIN GPIO88_MASK //GROUP 2[24]
#define AUDIO_CH3_PWM_N_PIN GPIO89_MASK //GROUP 2[25]
#define AUDIO_CH4_PWM_P_PIN GPIO90_MASK //GROUP 2[26]
#define AUDIO_CH4_PWM_N_PIN GPIO91_MASK //GROUP 2[27]
#define AUDIO_CH5_PWM_P_PIN GPIO92_MASK //GROUP 2[28]
#define AUDIO_CH5_PWM_N_PIN GPIO93_MASK //GROUP 2[29]
enum {
enIIS_OUT_16BIT,
enIIS_OUT_24BIT,
};
enum {
MCLK_MASTER,
MCLK_SLAVE,
};
enum {
MCLK_1_OUT,
MCLK_2_OUT,
};
enum {
MCLK1_IN,
MCLK2_IN,
};
enum {
MCLK_INPUT,
MCLK_OUTPUT,
MCLK_UNKNOWN
};
enum {
IIS_0_CH,
IIS_1_CH,
IIS_2_CH,
IIS_3_CH,
IIS_4_CH,
IIS_LAST_CH
};
enum {
IIS_DATA_0,
IIS_DATA_1,
IIS_DATA_2,
IIS_DATA_3,
IIS_DATA_4,
IIS_DATA_5,
IIS_DATA_LAST
};
enum {
IIS_DIR_IN,
IIS_DIR_OUT
};
typedef volatile struct {
U32 i2s_enable :1; //@i2s cd enable
U32 i2s_mode :1; //@0:slave;1:master
U32 i2s_24_bit :1;
U32 i2s_fmt :1; //@0:i2s;1:DSP MODE A
U32 i2s_swap :1; //@for i2s, it is always 1
U32 cdrom_en :1;
U32 cdrom_discramble :1;
U32 cdrom_mode :2; //@2b01:Mode 1;2b10:Mode 2
U32 i2s_bck_div :4;
U32 i2s_lrck_div :6;
U32 i2s_din_sel :3; //3b000:D0;....3b101:D5
} IIS0_CONFIGs;
typedef volatile struct {
U32 i2s_tx_enable :1;
U32 i2s_rx_enable :1;
U32 i2s_tx_24_bit :1;
U32 i2s_rx_24_bit :1;
U32 i2s_tx_fmt :1; //@0:i2s;1:DSP MODE A
U32 i2s_rx_fmt :1; //@0:i2s;1:DSP MODE A
U32 i2s_lrck_tx_swap :1; //@for i2s, it is always 1
U32 i2s_lrck_rx_swap :1; //@for i2s, it is always 1
U32 i2s_bck_div :4;
U32 i2s_lrck_div :6;
U32 reseved_bits :3;
U32 i2s_mode :1; //@0:slave;1:master
U32 i2s_din_sel :3; //3b000:D0;....3b101:D5
} IIS1_CONFIGs;
typedef volatile struct {
//@please check DA_PP_CONFIGs
} IIS2_CONFIGs;
//I2S Rcv Stream Type
enum {
RECEIVE_PCM,
RECEIVE_CDDA,
RECEIVE_CDROM
};
//CDROM Stream Type
enum {
RECEIVE_CDROM_MODE_0, //no crc check
RECEIVE_CDROM_MODE_1,
RECEIVE_CDROM_MODE_2
};
void IIS_Mclk_Master_Set(con);
void IIS_Mclk_Set(U8 master, U8 mclk_numer);
void IIS_0_init (U8 dir, U8 data_number);
void IIS_0_open (void);
void IIS_0_fini (void);
void IIS_0_close(void);
void IIS_0_enable (void);
void IIS_0_disable (void);
void IIS_1_init (U8 dir, U8 data_number);
void IIS_1_open (void);
void IIS_1_fini (void);
void IIS_1_close(void);
void IIS_1_tx_enable (void);
void IIS_1_rx_enable (void);
void IIS_1__rx_disable (void);
void IIS_1__tx_disable (void);
void IIS_2_init (void);
void IIS_2_open (void);
void IIS_2_fini (void);
void IIS_2_close(void);
void IIS_2_enable (void);
void IIS_2_disable (void);
void vSetCdromMode (U8 Mode);
#endif