#include "c_def.h"
#include "debug.h"

#include "regmap.h"

#include "hw_misc.h"
#include "hw_pwm.h"
#include "hw_gpio.h"

#include "app_gpio.h"


#define PWM_OUT   	
//#define PWM1_OUT   
//#define PWM2_OUT   
//#define PWM4_OUT   


#define PWM_OUT_PIN    	GPIO0_00_INDEX
#define PWM1_OUT_PIN    GPIO0_01_INDEX
#define PWM2_OUT_PIN    0//GPIO0_09_INDEX
//#define PWM3_OUT_PIN    GPIO2_04_INDEX
#define PWM4_OUT_PIN    GPIO2_04_INDEX


void pwm_init(void)
{
	hw_pwm_init();

#ifdef PWM_OUT
	hw_pwm_open();
	hw_pwm_clk_set(PWM_CLK_DIV4);
	hw_pwm_duty_set(PWM_DUTY_1,PWM_PERIOD_1);
#endif

#if defined PWM1_OUT
	//hw_pwm_init();
	hw_pwm1_open();
	hw_pwm1_clk_set(PWM_CLK_DIV4);
	hw_pwm1_duty_set(PWM_DUTY_2,PWM_PERIOD_2);
#endif

#if defined PWM2_OUT
	//hw_pwm_init();
	hw_pwm2_open();
	hw_pwm2_clk_set(PWM_CLK_DIV4);
	hw_pwm2_duty_set(PWM_DUTY_3,PWM_PERIOD_3);
#endif

#if defined PWM4_OUT 
	//hw_pwm_init();
	hw_pwm4_open();
	hw_pwm4_clk_set(PWM_CLK_DIV4);
	hw_pwm4_duty_set(PWM_DUTY_4,PWM_PERIOD_4);
#endif

	
}


void hw_pwm_init (void)
{
#if 0
	gpio0_SetFunction(PWM_OUT_PIN, TRUE);
	gpio0_SetOutputEnable(PWM_OUT_PIN);

	while (1)
	{
		gpio0_SetOutput(PWM_OUT_PIN);
		delayms(1);
		gpio0_ClrOutput(PWM_OUT_PIN);
		delayms(1);
	}
#endif





 #ifdef PWM_OUT
	app_gpio_MUXfunction_select(PWM_OUT_PIN, MUX_SEL_FUNCTION2);  
	//miscClock_gate_set(REG_CLKGATE_PWM);
#endif

#if defined PWM1_OUT
	app_gpio_MUXfunction_select(PWM1_OUT_PIN, MUX_SEL_FUNCTION2);
	//miscClock_gate_set(REG_CLKGATE_PWM);
#endif

#if defined PWM2_OUT
	app_gpio_MUXfunction_select(PWM2_OUT_PIN, MUX_SEL_FUNCTION2);
	//miscClock_gate_set(REG_CLKGATE_PWM);
#endif

#if defined PWM4_OUT 
	app_gpio_MUXfunction_select(PWM4_OUT_PIN, MUX_SEL_FUNCTION2);
#endif


	miscClock_gate_set(REG_CLKGATE_PWM);


}
#if 1//PWM

void hw_pwm_open (void)
{
//	volatile U32 tmp = REG_PWM_VERSION;

	//disable
	REG_PWM_CTL = 0x0;

	//APB CLK/div
	REG_PWM_CLK = PWM_CLK_DIV8;

	REG_PWM_DUTY = (900 << 16) | 600;
//	REG_PWM_DUTY = (900 << 16) | 0;

	//enable
	REG_PWM_CTL = 0x1;
}

void hw_pwm_clk_set(U8 div)
{
	//APB CLK/div
	REG_PWM_CLK = div;
}

void hw_pwm_close (void)
{
	REG_PWM_CTL = 0x0;			//disable
}


//
//   |<-----Period------------>|
//   ___________
//___|          |______________|
//   |<--Duty-->|

void hw_pwm_duty_set (U16 duty, U16 period)
{
#if 1
	REG_PWM_CTL = 0x0;			//disable

	REG_PWM_DUTY = (period << 16) | duty;

	REG_PWM_CTL = 0x1;			//enable  
#endif
}
#endif

#if 1//PWM 1
void hw_pwm1_open (void)
{
//	volatile U32 tmp = REG_PWM_VERSION;

	//disable
	REG_PWM1_CTL = 0x0;

	//APB CLK/div
	REG_PWM1_CLK = PWM_CLK_DIV8;

	REG_PWM1_DUTY = (900 << 16) | 600;
//	REG_PWM_DUTY = (900 << 16) | 0;

	//enable
	REG_PWM1_CTL = 0x1;
}

void hw_pwm1_clk_set(U8 div)
{
	//APB CLK/div
	REG_PWM1_CLK = div;
}

void hw_pwm1_close (void)
{
	REG_PWM1_CTL = 0x0;			//disable
}


//
//   |<-----Period------------>|
//   ___________
//___|          |______________|
//   |<--Duty-->|

void hw_pwm1_duty_set (U16 duty, U16 period)
{
#if 1
	REG_PWM1_CTL = 0x0;			//disable

	REG_PWM1_DUTY = (period << 16) | duty;

	REG_PWM1_CTL = 0x1;			//enable
#endif
}

#endif

#if 1//PWM 2
void hw_pwm2_open (void)
{
//	volatile U32 tmp = REG_PWM_VERSION;

	//disable
	REG_PWM2_CTL = 0x0;

	//APB CLK/div
	REG_PWM2_CLK = PWM_CLK_DIV8;

	REG_PWM2_DUTY = (900 << 16) | 600;
//	REG_PWM_DUTY = (900 << 16) | 0;

	//enable
	REG_PWM2_CTL = 0x1;
}

void hw_pwm2_clk_set(U8 div)
{
	//APB CLK/div
	REG_PWM2_CLK = div;
}

void hw_pwm2_close (void)
{
	REG_PWM2_CTL = 0x0;			//disable
}


//
//   |<-----Period------------>|
//   ___________
//___|          |______________|
//   |<--Duty-->|

void hw_pwm2_duty_set (U16 duty, U16 period)
{
#if 1
	REG_PWM2_CTL = 0x0;			//disable

	REG_PWM2_DUTY = (period << 16) | duty;

	REG_PWM2_CTL = 0x1;			//enable
#endif
}

#endif

#if 1//PWM 4
void hw_pwm4_open (void)
{
//	volatile U32 tmp = REG_PWM_VERSION;

	//disable
	REG_PWM3_CTL = 0x0;

	//APB CLK/div
	REG_PWM3_CLK = PWM_CLK_DIV8;

	REG_PWM3_DUTY = (900 << 16) | 600;
//	REG_PWM_DUTY = (900 << 16) | 0;

	//enable
	REG_PWM3_CTL = 0x1;
}

void hw_pwm4_clk_set(U8 div)
{
	//APB CLK/div
	REG_PWM3_CLK = div;
}

void hw_pwm4_close (void)
{
	REG_PWM3_CTL = 0x0;			//disable
}


//
//   |<-----Period------------>|
//   ___________
//___|          |______________|
//   |<--Duty-->|

void hw_pwm4_duty_set (U16 duty, U16 period)
{
#if 1
	REG_PWM3_CTL = 0x0;			//disable

	REG_PWM3_DUTY = (period << 16) | duty;

	REG_PWM3_CTL = 0x1;			//enable
#endif
}

#endif