interrupt.h
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/* interrupts.h -- Interrupt related definitions
*
* This code is taken from example code in the Xtensa Microprocessor
* Programmer's Guide.
*
* WARNING: It is highly unlikely that this code works as is on your
* particular Xtensa processor configuration. It is hardcoded
* for the specific processor configuration used for the
* examples in the Xtensa Microprocessor Programmer's Guide.
* (The example code did not use the Xtensa HAL to address this
* portability issue, for clarity's sake.) Getting it to work
* on another processor configuration requires some modifications.
*/
/*
* Copyright (c) 2003-2005 by Tensilica Inc. ALL RIGHTS RESERVED.
* These coded instructions, statements, and computer programs are the
* copyrighted works and confidential proprietary information of Tensilica Inc.
* They may not be modified, copied, reproduced, distributed, or disclosed to
* third parties in any manner, medium, or form, in whole or in part, without
* the prior written consent of Tensilica Inc.
*/
#ifndef __INTERRUPT_H__
#define __INTERRUPT_H__
//#include "prj.h"
#ifndef _XTSTR
#define _XTSTR(x) # x
#define XTSTR(x) _XTSTR(x)
#endif
#define INT_LEVEL_MASK 0
#define INT_ENABLE_MASK 4
#if 0//defined THREAD_RTOS
extern unsigned int intMasking[2];
static __inline__ unsigned int enable_ints(unsigned int mask)
{
unsigned int ret;
unsigned int new_intenable;
__asm__ __volatile__(
"rsil a15, 1 \n\t"
"l32i %0,%3,"XTSTR(INT_ENABLE_MASK)" \n\t"
"or %1, %0, %2 \n\t"
"s32i %1,%3,"XTSTR(INT_ENABLE_MASK)" \n\t"
"l32i %2,%3,"XTSTR(INT_LEVEL_MASK)" \n\t"
"and %1,%1,%2 \n\t"
"wsr %1,"XTSTR(INTENABLE)" \n\t"
"wsr a15, "XTSTR(PS)" \n\t"
"rsync \n\t"
: "=&a" (ret), "=&a" (new_intenable)
: "a" (mask), "a" (intMasking)
: "a15"
);
return ret;
}
static __inline__ unsigned int disable_ints(unsigned int mask)
{
unsigned int ret;
unsigned int new_intenable;
__asm__ __volatile__(
"rsil a15, 1 \n\t"
"l32i %0,%3,"XTSTR(INT_ENABLE_MASK)" \n\t"
"and %1, %0, %2 \n\t"
"s32i %1,%3,"XTSTR(INT_ENABLE_MASK)" \n\t"
"l32i %2,%3,"XTSTR(INT_LEVEL_MASK)" \n\t"
"and %1,%1,%2 \n\t"
"wsr %1,"XTSTR(INTENABLE)" \n\t"
"wsr a15, "XTSTR(PS)" \n\t"
"rsync \n\t"
: "=&a" (ret), "=&a" (new_intenable)
: "a" (mask), "a" (intMasking)
: "a15"
);
return ret;
}
static __inline__ unsigned int read_interrupt()
{
unsigned int interrupt;
__asm__ __volatile__ (
"rsr %0, "XTSTR(INTERRUPT)
: "=a" (interrupt)
);
return interrupt;
}
#endif
/// Format of an event callback function
typedef void (*p_callback_t)(void);
/*
* STRUCTURES DEFINTIONS
****************************************************************************************
*/
/// KE EVENT environment structure
struct ke_event_env_tag
{
/// Event field
U32 event_field;
/// Callback table
p_callback_t callback[10];
};
extern struct ke_event_env_tag ke_event_env;
/// RWIP Environment structure
struct rwip_env_tag
{
#if 1//(BLE_EMB_PRESENT || BT_EMB_PRESENT)
/// Half slot target timer (in half slots)
U32 timer_hs_target;
/// Half us target timer (in half us)
U32 timer_hus_target;
#endif // (BLE_EMB_PRESENT || BT_EMB_PRESENT)
/// 10 ms target timer (in half slots)
U32 timer_10ms_target;
#if 1//(BLE_EMB_PRESENT || BT_EMB_PRESENT)
/// Contains sleep duration accumulated timing error (32kHz: 1/2 half us | 32.768kHz: 1/256 half-us)
U32 sleep_acc_error;
/// Power_up delay (in LP clock cycle unit, depends on Low power clock frequency)
U32 lp_cycle_wakeup_delay;
/// Duration of sleep and wake-up algorithm (depends on CPU speed) expressed in half us.
U16 sleep_algo_dur;
#endif // (BLE_EMB_PRESENT || BT_EMB_PRESENT)
/// Prevent sleep bit field
U16 prevent_sleep;
#if 1//(BLE_EMB_PRESENT || BT_EMB_PRESENT)
/// External wake-up support
U8 ext_wakeup_enable;
#endif // (BLE_EMB_PRESENT || BT_EMB_PRESENT)
};
/*
* GLOBAL DEFINITIONS
****************************************************************************************
*/
/// RW SW environment
extern struct rwip_env_tag rwip_env;
#define LEVEL1_INT0_MASK (1 << 0)
#define LEVEL1_INT1_MASK (1 << 1)
#define LEVEL1_INT2_MASK (1 << 2)
#define LEVEL1_INT3_MASK (1 << 3)
#define LEVEL1_INT4_MASK (1 << 4)
#define LEVEL1_INT5_MASK (1 << 5)
#define LEVEL1_INT6_MASK (1 << 6)
#define LEVEL2_INT8_MASK (1 << 8)
#define LEVEL2_INT18_MASK (1 << 18)
#define LEVEL2_INT19_MASK (1 << 19)
#define LEVEL2_INT20_MASK (1 << 20)
#define LEVEL3_INT9_MASK (1 << 9)
#define LEVEL3_INT10_MASK (1 << 10)
#define INT_DMA LEVEL3_INT9_MASK
#define INT_USB LEVEL2_INT8_MASK
#define INT_INTCON LEVEL1_INT1_MASK
#define INT_GPIO LEVEL1_INT0_MASK
//LEVEL1_INI1
#define UART_INT_MASK (1<<0)
#define SPI_INT_MASK (1<<1)
#define I2S0_INT_MASK (1<<2)
#define I2S1_INT_MASK (1<<3)
#define I2C0_INT_MASK (1<<4)
#define LCD_INT_MASK (1<<5)
#define SD_INT_MASK (1<<6)
#define RTC_INT_MASK (1<<7)
#define UART1_INT_MASK (1<<8)
#define UART2_INT_MASK (1<<10)
#define IR_INT_MASK (1<<11)
#define ADC_INT_MASK (1<<13)
#define I2C1_INT_MASK (1<<30)
#define SPI_TEST_INT_MASK (1<<31)
#define SOFT0_INT_MASK (1<<12)
#define SOFT1_INT_MASK (1<<13)
#define SOFT2_INT_MASK (1<<14)
#define SOFT3_INT_MASK (1<<15)
#define SOFT4_INT_MASK (1<<16)
#define SOFT5_INT_MASK (1<<17)
#define SOFT6_INT_MASK (1<<18)
#define SOFT7_INT_MASK (1<<19)
#ifdef HDMI_CEC_BY_OPTEK
#define SOFT8_INT_MASK (1<<20)
#endif
#define SOFT_INT_ENABLE(x) (REG_INTCON_INT_ENA |= SOFT##x##_INT_MASK )
#define SOFT_INT_DISABLE(x) (REG_INTCON_INT_ENA &= ~SOFT##x##_INT_MASK)
#define SOFT_INT_SET(x) (REG_INTCON_INT_TEST |= SOFT##x##_INT_MASK)
#define SOFT_INT_CLR(x) (REG_INTCON_INT_TEST &= ~SOFT##x##_INT_MASK)
#define SOFT0_INT_ENABLE (REG_INTCON_INT_ENA |= SOFT0_INT_MASK )
#define SOFT0_INT_DISABLE (REG_INTCON_INT_ENA &= ~SOFT0_INT_MASK)
#if 0
#define SOFT0_INT_SET (REG_INTCON_INT_TEST |= SOFT0_INT_MASK)
#define SOFT0_INT_CLR (REG_INTCON_INT_TEST &= ~SOFT0_INT_MASK)
#else
#define SOFT0_INT_SET { \
TX_INTERRUPT_SAVE_AREA; \
TX_iDISABLE; \
REG_INTCON_INT_TEST |= SOFT0_INT_MASK; \
TX_iRESTORE; \
}
#define SOFT0_INT_CLR { \
TX_INTERRUPT_SAVE_AREA; \
TX_iDISABLE; \
REG_INTCON_INT_TEST &= ~SOFT0_INT_MASK; \
TX_iRESTORE; \
}
#endif
#define SOFT1_INT_ENABLE (REG_INTCON_INT_ENA |= SOFT1_INT_MASK )
#define SOFT1_INT_DISABLE (REG_INTCON_INT_ENA &= ~SOFT1_INT_MASK)
#if 0
#define SOFT1_INT_SET (REG_INTCON_INT_TEST |= SOFT1_INT_MASK)
#define SOFT1_INT_CLR (REG_INTCON_INT_TEST &= ~SOFT1_INT_MASK)
#else
#define SOFT1_INT_SET { \
TX_INTERRUPT_SAVE_AREA; \
TX_iDISABLE; \
REG_INTCON_INT_TEST |= SOFT1_INT_MASK; \
TX_iRESTORE; \
}
#define SOFT1_INT_CLR { \
TX_INTERRUPT_SAVE_AREA; \
TX_iDISABLE; \
REG_INTCON_INT_TEST &= ~SOFT1_INT_MASK; \
TX_iRESTORE; \
}
#endif
#define SOFT2_INT_ENABLE (REG_INTCON_INT_ENA |= SOFT2_INT_MASK )
#define SOFT2_INT_DISABLE (REG_INTCON_INT_ENA &= ~SOFT2_INT_MASK)
#if 0
#define SOFT2_INT_SET (REG_INTCON_INT_TEST |= SOFT2_INT_MASK)
#define SOFT2_INT_CLR (REG_INTCON_INT_TEST &= ~SOFT2_INT_MASK)
#else
#define SOFT2_INT_SET { \
TX_INTERRUPT_SAVE_AREA; \
TX_iDISABLE; \
REG_INTCON_INT_TEST |= SOFT2_INT_MASK; \
TX_iRESTORE; \
}
#define SOFT2_INT_CLR { \
TX_INTERRUPT_SAVE_AREA; \
TX_iDISABLE; \
REG_INTCON_INT_TEST &= ~SOFT2_INT_MASK; \
TX_iRESTORE; \
}
#endif
#define SOFT3_INT_ENABLE (REG_INTCON_INT_ENA |= SOFT3_INT_MASK)
#define SOFT3_INT_DISABLE (REG_INTCON_INT_ENA &= ~SOFT3_INT_MASK)
#if 0
#define SOFT3_INT_SET (REG_INTCON_INT_TEST |= SOFT3_INT_MASK)
#define SOFT3_INT_CLR (REG_INTCON_INT_TEST &= ~SOFT3_INT_MASK)
#else
#define SOFT3_INT_SET { \
TX_INTERRUPT_SAVE_AREA; \
TX_iDISABLE; \
REG_INTCON_INT_TEST |= SOFT3_INT_MASK; \
TX_iRESTORE; \
}
#define SOFT3_INT_CLR { \
TX_INTERRUPT_SAVE_AREA; \
TX_iDISABLE; \
REG_INTCON_INT_TEST &= ~SOFT3_INT_MASK; \
TX_iRESTORE; \
}
#endif
#define SOFT4_INT_ENABLE (REG_INTCON_INT_ENA |= SOFT4_INT_MASK)
#define SOFT4_INT_DISABLE (REG_INTCON_INT_ENA &= ~SOFT4_INT_MASK)
#define SOFT4_INT_SET { \
TX_INTERRUPT_SAVE_AREA; \
TX_iDISABLE; \
REG_INTCON_INT_TEST |= SOFT4_INT_MASK; \
TX_iRESTORE; \
}
#define SOFT4_INT_CLR { \
TX_INTERRUPT_SAVE_AREA; \
TX_iDISABLE; \
REG_INTCON_INT_TEST &= ~SOFT4_INT_MASK; \
TX_iRESTORE; \
}
#define SOFT5_INT_ENABLE (REG_INTCON_INT_ENA |= SOFT5_INT_MASK)
#define SOFT5_INT_DISABLE (REG_INTCON_INT_ENA &= ~SOFT5_INT_MASK)
#define SOFT5_INT_SET { \
TX_INTERRUPT_SAVE_AREA; \
TX_iDISABLE; \
REG_INTCON_INT_TEST |= SOFT5_INT_MASK; \
TX_iRESTORE; \
}
#define SOFT5_INT_CLR { \
TX_INTERRUPT_SAVE_AREA; \
TX_iDISABLE; \
REG_INTCON_INT_TEST &= ~SOFT5_INT_MASK; \
TX_iRESTORE; \
}
#define SOFT6_INT_ENABLE (REG_INTCON_INT_ENA |= SOFT6_INT_MASK )
#define SOFT6_INT_DISABLE (REG_INTCON_INT_ENA &= ~SOFT6_INT_MASK)
#define SOFT6_INT_SET { \
TX_INTERRUPT_SAVE_AREA; \
TX_iDISABLE; \
REG_INTCON_INT_TEST |= SOFT6_INT_MASK; \
TX_iRESTORE; \
}
#define SOFT6_INT_CLR { \
TX_INTERRUPT_SAVE_AREA; \
TX_iDISABLE; \
REG_INTCON_INT_TEST &= ~SOFT6_INT_MASK; \
TX_iRESTORE; \
}
#define SOFT7_INT_ENABLE (REG_INTCON_INT_ENA |= SOFT7_INT_MASK )
#define SOFT7_INT_DISABLE (REG_INTCON_INT_ENA &= ~SOFT7_INT_MASK)
#define SOFT7_INT_SET { \
TX_INTERRUPT_SAVE_AREA; \
TX_iDISABLE; \
REG_INTCON_INT_TEST |= SOFT7_INT_MASK; \
TX_iRESTORE; \
}
#define SOFT7_INT_CLR { \
TX_INTERRUPT_SAVE_AREA; \
TX_iDISABLE; \
REG_INTCON_INT_TEST &= ~SOFT7_INT_MASK; \
TX_iRESTORE; \
}
#ifdef HDMI_CEC_BY_OPTEK
#define SOFT8_INT_ENABLE (REG_INTCON_INT_ENA |= SOFT8_INT_MASK )
#define SOFT8_INT_DISABLE (REG_INTCON_INT_ENA &= ~SOFT8_INT_MASK)
#define SOFT8_INT_SET { \
TX_INTERRUPT_SAVE_AREA; \
TX_iDISABLE; \
REG_INTCON_INT_TEST |= SOFT8_INT_MASK; \
TX_iRESTORE; \
}
#define SOFT8_INT_CLR { \
TX_INTERRUPT_SAVE_AREA; \
TX_iDISABLE; \
REG_INTCON_INT_TEST &= ~SOFT8_INT_MASK; \
TX_iRESTORE; \
}
#endif
#define SD_DMA_SOFT_INT_MASK SOFT4_INT_MASK
#define SD_DMA_SOFT_INT_NO 4//SOFT4_INT_MASK
#define SD_DMA_SOFT_INT_ENABLE SOFT_INT_ENABLE(4)
#define SD_DMA_SOFT_INT_DISABLE SOFT_INT_DISABLE(4)
#define SD_DMA_SOFT_INT_SET SOFT_INT_SET(4)
#define SD_DMA_SOFT_INT_CLR SOFT_INT_CLR(4)
void L1_int0_extlevel(void *param);
void L1_int1_extlevel(void *param);
void L1_int5_extlevel(void *param);
void L1_int6_timer0(void *para);
void L1_int2_extlevel(void *param);
void L1_int3_extlevel(void *param);
void L1_int4_extlevel(void *param);
void L2_int8_extlevel(void *param);
void L3_int9_extlevel(void *param);
void L3_int10_timer1(void *param);
void L2_int18_extlevel(void *param);
void L2_int19_extlevel(void *param);
void L2_int20_extlevel(void *param);
void xtensa_timer0_updata(void);
void xtensa_timer1_updata(void);
void usbotg_isr( void );
void sd_isr( void );
#ifdef SD_ENABLE
void sd_dma7TxCompleteCallback( void );
void sd_dma8RxCompleteCallback( void );
#endif
#endif //__INTERRUPT_H__