#include "os_config.h"

#include "c_def.h"
#include "debug.h"
#include "oem.h"

#include "regmap.h"


#ifdef USB_HOST_ENABLE

#include "mem_reloc.h"

#include "IRP.h"
#include "interrupt.h"
#include "hw_timer.h"
#include "message.h"
#include "usbd.h"
#include "hcd.h"
#include "otg.h"

#include "usbdev.h"

//#ifndef	OTG_FORCE_FULL_SPEED
U8 usb_highspeed_flag;
//#endif


volatile USB_OTG_REGISTERS * otgRegister;
OTG_ENHANCE_CTRL otgEnhanceCtrl, *otgEnhCtrl; 

USB_HOST_REG	usbHostRegs,	*usbhostReg;
USB_DEVICE_REG	usbDevRegs,		*usbdevReg;

typedef	struct {
	U8	oldstate;
	U8	curstate;
	
	IRP	irp;
} OTG;

OTG	otg;



void otg_intProcess(void);
void hcd_intProcess(void);
void dcd_intProcess(void);

void usbotg_isr( void ) __USBHOST_TEXT;

//int8, dma is int9
void usbotg_isr( void )
{
	//do
	{
/*	volatile U32 reg32;
		reg32 = *otgEnhCtrl->ctrl;
		*otgEnhCtrl->ctrl	&=	~ENH_CTRL_INT_STAT_MASK;
		reg32 &= ENH_CTRL_INT_STAT_MASK;
		reg32 >>= ENH_CTRL_INT_STAT_SHIFT;
		
		if( reg32 & ENH_CTRL_INT_FIFO )
		{
			DBG_assert(0);
		}
		if( reg32 & ENH_CTRL_INT_WKUP )
		{
			DBG_assert(0);
		}
		
		if( reg32 & ENH_CTRL_INT_USB )
*/		
		{	
			otg.curstate = otgRegister->state;
			
			//otg 
			otg_intProcess();
			
			if( otg.curstate == 0x03 ) //host
			{
				hcd_intProcess();
			}
			
#ifdef USB_DEV_ENABLE
			if( otg.curstate == 0x09 ) //dev
			{
				dcd_intProcess();
			}
#else
			DBG_assert( otg.curstate != 0x09 ); //dev
			//dcd_int_process();			
#endif

			if( otg.curstate != otg.oldstate )
			{
				otg.oldstate = otg.curstate;
			}		
		}
	//} while( reg32 != 0 );
	}
}

int dcd_hostUnplug( void );
int dcd_isOpen( void );

void otg_intProcess(void) __USBHOST_TEXT;

#ifdef USB_DEV_ENABLE

void otg_intProcess(void)
{
	IRP	*irp = &otg.irp;
	volatile U8 reg8;
	
	reg8 = (otgRegister->irq & otgRegister->ien);
	if( reg8 )
	{
		otgRegister->irq	=	reg8;

		//DBG_iPrintf("\n---%x\n", reg8);
		if( reg8 & 0x01 )	//2.16.1: a_idle or b_idle state.
		{
			//DBG_iPrintf("\n---reg8 & 0x01\n");
			if( otgRegister->state == 0x08 )   //2.16.2: otgstate 0x08 b_idle.
			{	
				//dev
				/*
				otgRegister->ctrl &= ~0x01;
				*usbdevReg->ctrl->usbcs &= ~0x40;	//disconnect bit, 1 is discon
				*/
				otgRegister->ctrl &= ~0x01;			//2.16.3 set otgctrl bit0 to 0, end the session.
				otgRegister->ctrl |=  0x02;			//JJ+ set bit1 to forces the bus power-down.
				*usbdevReg->ctrl->usbcs |= 0x40;	//2.18.41 usbcs: discon bit, 1 is discon. JJ+

				if( (otg.curstate == 0x08) && (otg.oldstate == 0x09 ) && dcd_isOpen() )
				{
					dcd_hostUnplug();

					//DBG_iPrintf("\n_HOST_DISCON\n");
					FILL_OTG_IRP( irp, enIRPT_DEV_STACK, IRP_PARAM_HOST_DISCONNECT );
					usbmsg_isendIRP( irp );
				}
			}
			else								//2.16.1: a_idle.
			{
				//host
				otgRegister->ctrl &= ~0x02;
				otgRegister->ctrl |= 0x01;
			}
		}
				
		if( reg8 & 0x08 )	//2.16.1: vbuserrirq, free the bus, then power-down bus.
		{
			otgRegister->ctrl &= ~0x01;
			otgRegister->ctrl |= 0x02;
			//send error msg out ?
		}
		
		if( reg8 & 0x04 )	//2.16.1: a_host or b_host state entering.
		{
			//DBG_iPrintf("\n---reg8 & 0x04\n");
			//host --> take this as dev connect			
			if( otg.curstate == 0x03 )
			{
				FILL_OTG_IRP( irp, enIRPT_USBD, IRP_PARAM_DEV_CONNECT );
			}
			else
			{
				FILL_OTG_IRP( irp, enIRPT_USBD, IRP_PARAM_DEV_DISCONNECT );
				hcd_devUnplug();
			}
			
			usbmsg_isendIRP( irp );
		}
		
		if( reg8 & 0x10 )	//2.16.1: a_peri or b_peri state entering.
		{
			//DBG_iPrintf("\n---reg8 & 0x10\n");
			//dev --> take this as host connnect
			if( dcd_isOpen() )
			{
				//DBG_iPrintf("\n_HOST_CON\n");
				FILL_OTG_IRP( irp, enIRPT_DEV_STACK, IRP_PARAM_HOST_CONNECT );
				usbmsg_isendIRP( irp );
			}
		}
	}
}

#else

void otg_intProcess(void)
{
	IRP	*irp = &otg.irp;
	volatile U8 reg8;
	
	reg8 = (otgRegister->irq & otgRegister->ien);
	if( reg8 )
	{
		otgRegister->irq = reg8;
		
		if( reg8 & 0x01 )
		{
			if( otgRegister->state == 0x08 )
			{
				//dev
				DBG_assert(0);
			}
			else
			{
				//host
				*usbdevReg->ctrl->usbcs |= 0x40; //disconnect
				otgRegister->ctrl &= ~0x02;
				otgRegister->ctrl |= 0x01;
			}
		}
		
		if( reg8 & 0x08 )
		{
			otgRegister->ctrl &= ~0x01;
			otgRegister->ctrl |= 0x02;
		}
		
		if( reg8 & 0x04 )
		{
			//host	--> take this as dev connect
			
			if( otg.curstate == 0x03 )
			{
				FILL_OTG_IRP( irp, enIRPT_USBD, IRP_PARAM_DEV_CONNECT );
			}
			else
			{
				FILL_OTG_IRP( irp, enIRPT_USBD, IRP_PARAM_DEV_DISCONNECT );
				hcd_devUnplug();
			}
			
			usbmsg_isendIRP( irp );
		}
		
		if( reg8 & 0x10 )
		{
			//dev --> take this as host connnect
			DBG_assert(0);
		}
	}
}
#endif //USB_DEV_ENABLE


#if (defined USB_DEV_ENABLE || defined USB_SPEAKER)

int otg_isDevPlugin( void )
{
	//in host mode
	return ( (otgRegister->status & 0x02) && (otgRegister->state == 0x03) );
}

int otg_isHostPlugin( void )
{
	//in dev mode
	//FIXME
	return ( (otgRegister->status & 0x04) && (otgRegister->state == 0x09) );
}

#endif


#define	REG_ADDR(x)		(void*)(USB_DEVICE_BASE_ADDR + x)
//#define	REG_ADDR(x)		(USB_DEVICE_BASE_ADDR + x)


const ENDPOINT0_REGS endp0Addr = {
	REG_ADDR(0x00),	REG_ADDR(0x01),	REG_ADDR(0x02),	
	REG_ADDR(0xc0),	REG_ADDR(0xc1),	REG_ADDR(0xc3),	REG_ADDR(0x1e0),	
	REG_ADDR(0x180), REG_ADDR(0x140), REG_ADDR(0x100)
};



const ENDPOINT_REGS	endp1RxAddr	=	{
	REG_ADDR(0x08),	REG_ADDR(0x0b),	REG_ADDR(0x0a),
	REG_ADDR(0xc6),	REG_ADDR(0xc7),	
	REG_ADDR(0x1e2), REG_ADDR(0x304),
	REG_ADDR(0x84),	REG_ADDR(0x84),	REG_ADDR(0x84)
};

const ENDPOINT_REGS	endp2RxAddr	=	{
	REG_ADDR(0x10),	REG_ADDR(0x13),	REG_ADDR(0x12),
	REG_ADDR(0xca),	REG_ADDR(0xcb),	
	REG_ADDR(0x1e4),	REG_ADDR(0x308),
	REG_ADDR(0x88),	REG_ADDR(0x88),	REG_ADDR(0x88)
};

const ENDPOINT_REGS	endp3RxAddr	=	{   //ep3 Rx=Host OUT byte counter, cs, con,...
	//REG_ADDR(0x18),	REG_ADDR(0x13),	REG_ADDR(0x1b), //JJ
	REG_ADDR(0x18),	REG_ADDR(0x1b),	REG_ADDR(0x1a),
	REG_ADDR(0xce),	REG_ADDR(0xcf),	
	REG_ADDR(0x1e6), REG_ADDR(0x30c),//2.17.20 HC INx Max, 2.18.47 outxstaddr
	REG_ADDR(0x8c),	REG_ADDR(0x8c),	REG_ADDR(0x8c)
};

const ENDPOINT_REGS	endp1TxAddr	=	{
	REG_ADDR(0x0c),	REG_ADDR(0x0f),	REG_ADDR(0x0e),
	REG_ADDR(0xc4),	REG_ADDR(0xc5),	
	REG_ADDR(0x3e2), REG_ADDR(0x344),
	REG_ADDR(0x84),	REG_ADDR(0x84),	REG_ADDR(0x84)
};

const ENDPOINT_REGS	endp2TxAddr	=	{
	REG_ADDR(0x14),	REG_ADDR(0x17),	REG_ADDR(0x16),
	REG_ADDR(0xc8),	REG_ADDR(0xc9),	
	REG_ADDR(0x3e4), REG_ADDR(0x348),
	REG_ADDR(0x88),	REG_ADDR(0x88),	REG_ADDR(0x88)
};

const ENDPOINT_REGS	endp3TxAddr	=	{   //ep3 Tx=Host IN byte counter, cs, con,... !!!
	REG_ADDR(0x1c),	REG_ADDR(0x1f),	REG_ADDR(0x1e),
	REG_ADDR(0xcc),	REG_ADDR(0xcd),	
	REG_ADDR(0x3e6), REG_ADDR(0x34c),//2.17.22 HC OUTx Max, 2.18.48 inxstaddr
	REG_ADDR(0x8c),	REG_ADDR(0x8c),	REG_ADDR(0x8c)
};




const COMMON_CTRL_REG	commCtlAddr	=	{
	REG_ADDR(0x1a2),	REG_ADDR(0x1a3),	REG_ADDR(0x1a6),	REG_ADDR(0x1a7),
	REG_ADDR(0x1a8)
};


const USB_IRQ_REGS	irqAddr	=	{
	REG_ADDR(0x1a0),	REG_ADDR(0x1a1),
	REG_ADDR(0x188),	REG_ADDR(0x194),	REG_ADDR(0x18a),	REG_ADDR(0x196),
	REG_ADDR(0x18c),	REG_ADDR(0x198),
	REG_ADDR(0x18e),	REG_ADDR(0x19a),
	REG_ADDR(0x190),	REG_ADDR(0x19c),	REG_ADDR(0x192),	REG_ADDR(0x19e),
	REG_ADDR(0x1b4),	REG_ADDR(0x1b8),	REG_ADDR(0x1b6),	REG_ADDR(0x1ba)
};

void loopdelay( U32 t )
{
	while( t -- );
}


void otg_phy_set(BOOL bHost_Dev)
{
	//for the 3rd Generation Chip
    volatile U32 tmp,val;

	MISC_USBPHY_CONTROLs *usbphy_config;
	tmp = REG_MISC_USBPHY;
	usbphy_config = (MISC_USBPHY_CONTROLs *) &tmp;

	usbphy_config->usbphy_cfg_rstn = 1;
	REG_MISC_USBPHY = tmp;
	loopdelay(10);
	
	usbphy_config->usbphy_cfg_addr = 0x23;
	usbphy_config->usbphy_cfg_wdata = 0x3c;
	REG_MISC_USBPHY = tmp;
	usbphy_config->usbphy_cfg_wren = 1;
	usbphy_config->usbphy_cfg_rden = 0;
	REG_MISC_USBPHY = tmp;
	usbphy_config->usbphy_cfg_wren = 0;
	REG_MISC_USBPHY = tmp;
	
	usbphy_config->usbphy_cfg_addr = 0x37;
	usbphy_config->usbphy_cfg_wdata = 0xEA;
	REG_MISC_USBPHY = tmp;
	usbphy_config->usbphy_cfg_wren = 1;
	REG_MISC_USBPHY = tmp;
	usbphy_config->usbphy_cfg_wren = 0;
	REG_MISC_USBPHY = tmp;


	usbphy_config->usbphy_cfg_addr = 0x23;
	REG_MISC_USBPHY = tmp;
	usbphy_config->usbphy_cfg_rden = 1;
	REG_MISC_USBPHY = tmp;
	val = (U32)usbphy_config->usbphy_cfg_rdata;
	usbphy_config->usbphy_cfg_rden = 0;
	REG_MISC_USBPHY = tmp;


	usbphy_config->usbphy_cfg_addr = 0x37;
	REG_MISC_USBPHY = tmp;
	usbphy_config->usbphy_cfg_rden = 1;
	REG_MISC_USBPHY = tmp;
	val = (U32)usbphy_config->usbphy_cfg_rdata;
	usbphy_config->usbphy_cfg_rden = 0;
	REG_MISC_USBPHY = tmp;

	if (bHost_Dev) //Host
	{
		//usbphy_config->utmi_iddig_src = 0;
		usbphy_config->utmi_iddig_src = 1;
		REG_MISC_USBPHY = tmp;
		//usbphy_config->utmi_iddig_sw = 1;
		usbphy_config->utmi_iddig_sw = 0;
	    REG_MISC_USBPHY = tmp;
	}
	else //Device
	{
		usbphy_config->utmi_iddig_src = 0;
		REG_MISC_USBPHY = tmp;
		usbphy_config->utmi_iddig_sw = 1;
	    REG_MISC_USBPHY = tmp;
	}

	//usbphy_config->utmi_vbus_src = 0;
	usbphy_config->utmi_vbus_src = 1;
	REG_MISC_USBPHY = tmp;

}

int otg_init( void )
{
	int ret;
	
	DBG_Printf("%s\n\r", __func__);

	otg_phy_set(TRUE);	//Host

	otgRegister	=	(USB_OTG_REGISTERS *)USB_OTG_BASE_ADDR;
	DBG_assert( USB_ORG_REGFILE_SIZE == sizeof(USB_OTG_REGISTERS) );
	
	otgEnhCtrl	=	&otgEnhanceCtrl;

	otgEnhCtrl->ctrl	=	(U32*)OTG_CTL_REG_ADDR;
	otgEnhCtrl->dmaEndp1Addr	=	OTG_DMA_ENDP1_ADDR;
	otgEnhCtrl->dmaEndp2Addr	=	OTG_DMA_ENDP2_ADDR;
	otgEnhCtrl->dmaEndp3Addr	=	OTG_DMA_ENDP3_ADDR;
	
	usbhostReg	=	&usbHostRegs;
	usbdevReg	=	&usbDevRegs;

	usbhostReg->endp0		=	(ENDPOINT0_REGS*)&endp0Addr;
	usbhostReg->endp1In		=	(ENDPOINT_REGS*)&endp1RxAddr;
	usbhostReg->endp1Out	=	(ENDPOINT_REGS*)&endp1TxAddr;
	usbhostReg->endp2In		=	(ENDPOINT_REGS*)&endp2RxAddr;
	usbhostReg->endp2Out	=	(ENDPOINT_REGS*)&endp2TxAddr;

	usbhostReg->endp3In		=	(ENDPOINT_REGS*)&endp3RxAddr;	//HID
	usbhostReg->endp3Out	=	(ENDPOINT_REGS*)&endp3TxAddr;

	usbhostReg->ctrl		=	(COMMON_CTRL_REG*)&commCtlAddr;
	usbhostReg->irq			=	(USB_IRQ_REGS*)&irqAddr;

	usbhostReg->portctrl	=	(U8*)REG_ADDR(0x1ab);   //0x1ab [des] 2.17.6 hcportctrl 
	usbhostReg->framenum	=	(U16*)REG_ADDR(0x1ac);  //0x1ac [des] 2.17.7 hcfrmnrl 
	usbhostReg->frameRemain	=	(U16*)REG_ADDR(0x1ae);  //0x1ae [des] 2.17.8 hcfrmnrh

	usbdevReg->endp0		=	(ENDPOINT0_REGS*)&endp0Addr;    //rxbc, txbc, cs, ... setupdat, rxdata, txdata
	usbdevReg->endp1In		=	(ENDPOINT_REGS*)&endp1TxAddr;   //useless !
	usbdevReg->endp1Out		=	(ENDPOINT_REGS*)&endp1RxAddr;   //ep1 0x01, Spk,*endp1Out,Out for Device in dcd_open()
	usbdevReg->endp2In		=	(ENDPOINT_REGS*)&endp2TxAddr;   //ep2 0x82, Mic,*endp2In, IN in dcd_open()
	usbdevReg->endp2Out		=	(ENDPOINT_REGS*)&endp2RxAddr;   //useless !

	usbdevReg->endp3In		=	(ENDPOINT_REGS*)&endp3TxAddr;   //ep3 0x83, HID,*endp3In, IN in dcd_open()
	usbdevReg->endp3Out		=	(ENDPOINT_REGS*)&endp3RxAddr;   //useless !

	usbdevReg->ctrl			=	(COMMON_CTRL_REG*)&commCtlAddr;
	usbdevReg->irq			=	(USB_IRQ_REGS*)&irqAddr;
	
	usbdevReg->framecnt		=	(U16*)REG_ADDR(0x1a4);


	//ret = hcd_init();
	//DBG_assert( ret );


	return TRUE;
}

int otg_init_for_dev( void )
{
	int ret;
	DBG_Printf("+++++++++++++++ %s\n\r", __func__);

	otg_phy_set(FALSE);	//Dev

	otgRegister	=	(USB_OTG_REGISTERS *)USB_OTG_BASE_ADDR;
	DBG_assert( USB_ORG_REGFILE_SIZE == sizeof(USB_OTG_REGISTERS) );
	
	otgEnhCtrl	=	&otgEnhanceCtrl;

	otgEnhCtrl->ctrl	=	(U32*)OTG_CTL_REG_ADDR;
	otgEnhCtrl->dmaEndp1Addr	=	OTG_DMA_ENDP1_ADDR;
	otgEnhCtrl->dmaEndp2Addr	=	OTG_DMA_ENDP2_ADDR;
	otgEnhCtrl->dmaEndp3Addr	=	OTG_DMA_ENDP3_ADDR;
	
	usbhostReg	=	&usbHostRegs;
	usbdevReg	=	&usbDevRegs;


	usbdevReg->endp0		=	(ENDPOINT0_REGS*)&endp0Addr;    //rxbc, txbc, cs, ... setupdat, rxdata, txdata

	usbdevReg->endp1In		=	(ENDPOINT_REGS*)&endp1TxAddr;   //useless !

	usbdevReg->endp1Out		=	(ENDPOINT_REGS*)&endp1RxAddr;   //ep1 0x01, Spk,*endp1Out,Out for Device in dcd_open()
	usbdevReg->endp2In		=	(ENDPOINT_REGS*)&endp2TxAddr;   //ep2 0x82, Mic,*endp2In, IN in dcd_open()

	usbdevReg->endp2Out		=	(ENDPOINT_REGS*)&endp2RxAddr;   //useless !

	usbdevReg->endp3In		=	(ENDPOINT_REGS*)&endp3TxAddr;   //ep3 0x83, HID,*endp3In, IN in dcd_open()
	usbdevReg->endp3Out		=	(ENDPOINT_REGS*)&endp3RxAddr;   //useless !

	usbdevReg->ctrl			=	(COMMON_CTRL_REG*)&commCtlAddr;
	usbdevReg->irq			=	(USB_IRQ_REGS*)&irqAddr;
	
	usbdevReg->framecnt		=	(U16*)REG_ADDR(0x1a4);


	//ret = hcd_init();
	//DBG_assert( ret );


	return TRUE;
}


void otg_phy_standby(void)  __attribute__ ((section (".flash_boot_text")));

void otg_phy_standby (void)
{
	U32 *pReg;
	
	pReg = (U32 *) OTG_CTL_REG_ADDR;

	*pReg = 0x0; //phy standby
}


int otg_open( void )
{
	volatile U32 reg32;
	int i;
	DBG_Printf("%s\n\r", __func__);

	memset( &otg, 0, sizeof(otg) );
	otg.curstate = otg.oldstate = 0xFF; //invalid state

#if 1//def OPTEK_SOC2_VERSION
	for( i = 0; i < 1; i ++ )
	{
#ifdef OTG_FORCE_FULL_SPEED
		reg32 = ENH_CTRL_PHY_CLK_ENA|ENH_CTRL_PHY_REG_ENA|ENH_CTRL_PHY_PLL_ENA|ENH_CTRL_DIS_HSPEED | ENH_CTRL_PHY_NO_SUSPEND;
		*otgEnhCtrl->ctrl = reg32;
		timer_delayms(10);
		reg32 |= ENH_CTRL_RESET;
		*otgEnhCtrl->ctrl = reg32;

		timer_delayms(10);
		reg32 = ENH_CTRL_PHY_CLK_ENA|ENH_CTRL_PHY_REG_ENA|ENH_CTRL_PHY_PLL_ENA|ENH_CTRL_DIS_HSPEED | ENH_CTRL_PHY_NO_SUSPEND;
#else

#ifndef OTG_FORCE_FULL_SPEED
		if (usb_highspeed_flag)
#endif
		{
			DBG_Puts("USB high speed\n\n\r");

			//high speed
			reg32 = ENH_CTRL_PHY_CLK_ENA|ENH_CTRL_PHY_REG_ENA|ENH_CTRL_PHY_PLL_ENA|ENH_CTRL_PHY_NO_SUSPEND;
			*otgEnhCtrl->ctrl = reg32;
			timer_delayms(10);
			reg32 |= ENH_CTRL_RESET;
			*otgEnhCtrl->ctrl = reg32;

			timer_delayms(10);
			reg32 = ENH_CTRL_PHY_CLK_ENA|ENH_CTRL_PHY_REG_ENA|ENH_CTRL_PHY_PLL_ENA| ENH_CTRL_PHY_NO_SUSPEND;
		}
#ifndef OTG_FORCE_FULL_SPEED
		else
		{
			DBG_Puts("USB full speed\n\r");

			reg32 = ENH_CTRL_PHY_CLK_ENA|ENH_CTRL_PHY_REG_ENA|ENH_CTRL_PHY_PLL_ENA|ENH_CTRL_DIS_HSPEED | ENH_CTRL_PHY_NO_SUSPEND;
			*otgEnhCtrl->ctrl = reg32;
			timer_delayms(10);
			reg32 |= ENH_CTRL_RESET;
			*otgEnhCtrl->ctrl = reg32;

			timer_delayms(10);
			reg32 = ENH_CTRL_PHY_CLK_ENA|ENH_CTRL_PHY_REG_ENA|ENH_CTRL_PHY_PLL_ENA|ENH_CTRL_DIS_HSPEED | ENH_CTRL_PHY_NO_SUSPEND;
		}
#endif

#endif

		reg32 |= (ENH_CTRL_INT_USB<<ENH_CTRL_INT_ENA_SHIFT) ;
		*otgEnhCtrl->ctrl = reg32;
		timer_delayms(10);

		otgRegister->taaidlbdis = 0x80;
		otgRegister->tawaitbcon = 0x80;
		otgRegister->ien		= 0x1d;
	}

#else

	for( i = 0; i < 2; i ++ )
	{
#ifdef	OTG_FORCE_FULL_SPEED
		//full speed
		*otgEnhCtrl->ctrl = ENH_CTRL_DIS_HSPEED;
		*otgEnhCtrl->ctrl = ENH_CTRL_RESET | ENH_CTRL_RESET_PHY|ENH_CTRL_DIS_HSPEED;
		timer_delayms(50);
		reg32	= (ENH_CTRL_ENA_CONTROLLER | ENH_CTRL_ENA_PHY | (ENH_CTRL_INT_USB<<ENH_CTRL_INT_ENA_SHIFT) );
		reg32 |= ENH_CTRL_DIS_HSPEED;
#else
		//high speed
		*otgEnhCtrl->ctrl = ENH_CTRL_RESET | ENH_CTRL_RESET_PHY;
		timer_delayms(50);
		reg32 = (ENH_CTRL_ENA_CONTROLLER | ENH_CTRL_ENA_PHY | (ENH_CTRL_INT_USB<<ENH_CTRL_INT_ENA_SHIFT) );
#endif
		*otgEnhCtrl->ctrl = reg32;
		timer_delayms(10);
		
		otgRegister->taaidlbdis	= 0x80;
		otgRegister->tawaitbcon	= 0x80;
		otgRegister->ien		= 0x1d;
	}
#endif

#ifdef USB_DEV_ENABLE
	//patch for device mode
	otgRegister->ctrl = 0x00;
#endif

	#if 0//it is moved to the dstack.c of library of optek_lib_usb_device.a
	USB_INT_ENABLE;
	#endif

	//patch for ID tied low
	if(!( otgRegister->status & 0x40) )
	{
		otgRegister->ctrl = 0x01;
	}

	return TRUE;
}

int otg_close( void )
{
	DBG_Printf("----------------- %s\n\r", __func__);

	USB_INT_DISABLE;
	otgRegister->ien = 0x00;

	*otgEnhCtrl->ctrl &= ~ENH_CTRL_INT_ENA_MASK;
#if 1//def OPTEK_SOC2_VERSION
	*otgEnhCtrl->ctrl &= ~(ENH_CTRL_PHY_CLK_ENA | ENH_CTRL_PHY_PLL_ENA | ENH_CTRL_PHY_REG_ENA | ENH_CTRL_PHY_NO_SUSPEND);
#else
	*otgEnhCtrl->ctrl &= ~(ENH_CTRL_ENA_CONTROLLER | ENH_CTRL_ENA_PHY);
#endif

	return TRUE;
}

int otg_power_down(void)
{
	DBG_Printf("%s\n\r", __func__);

	USB_INT_DISABLE;
	*otgEnhCtrl->ctrl = 0;
}

#endif //USB_HOST_ENABLE