#ifndef	__SD_HCD_H__
#define	__SD_HCD_H__


#define	RESP_WORDS	4

typedef	struct {
	U32	reset;
	U32	cmd;
	U32	argument;
	U32	blk;
	U32	resp[RESP_WORDS];

	U32	control;
	U32	status;
	U32	intEna;
	U32	intStat;
	U32	version;
}	SD_REGISTERS;

#define	SD_REGISTER_SIZE	(13*4)



//	reset

#define	RST_RESET		(1 << 0)

#define	RST_MODE_MS		(1 << 1)
#define	RST_MODE_SDn	(1 << 1)

#define	RST_RUN			(1 << 2)


//	cmd

#define	CMD_INDX_MASK		0x3F

#define	CMD_DATA_PRESENT	(1 << 6)
#define	CMD_DATA_TX			(1 << 7)
#define	CMD_MULTI_BLK		(1 << 8)

#define	CMD_RESP_TYPE_MASK		(3 << 10)
#define	CMD_RESP_TYPE_NO_RESP	(0 << 10)
#define	CMD_RESP_TYPE_136		(1 << 10)
#define	CMD_RESP_TYPE_48		(2 << 10)
#define	CMD_RESP_TYPE_48B		(3 << 10)

#define	CMD_RESP_CHK_INDX		(1 << 12)
#define	CMD_RESP_CHK_CRC		(1 << 13)


//	blk

#define	BLK_CNT_SHIFT			(12)


//	control

#define	CTL_4BIT				(1 << 0)

#define	CTL_CLK_SHIFT			1
#define	CTL_CLK_MASK			( 0x7FF << 1 )

#define	CTL_TOUT_READ_SHIFT		12			
#define	CTL_TOUT_WRITE_SHIFT	16
#define	CTL_TOUT_RESP_BUSY_SHIFT		20			

#define	CTL_FIFO_RESET			(1 << 24)
#define	CTL_ENDIAN_SWITCH		(1 << 25)


//	status

#define	STAT_WP_PIN				(1 << 5)
#define	STAT_CARD_INSERT		(1 << 8)

//	intEna/intStat

#define	INT_CARD_INSERT			(1 << 0)
#define	INT_CARD_REMOVE			(1 << 1)

#define	INT_CMD_COMPLETE		(1 << 3)
#define	INT_TRANS_COMPLETE		(1 << 4)

#define	INT_ERR_CMD_INDX		(1 << 5)
#define	INT_ERR_CMD_CRC			(1 << 6)
#define	INT_ERR_CMD_ENDB		(1 << 7)
#define	INT_ERR_CMD_TOUT		(1 << 8)

#define	INT_ERR_DATA_CRC		(1 << 9)
#define	INT_ERR_DATA_ENDB		(1 << 10)
#define	INT_ERR_DATA_TOUT		(1 << 11)

#define	INT_FIFO_EMPTY			(1 << 12)
#define	INT_FIFO_HALF_EMPTY		(1 << 13)
#define	INT_FIFO_UNDERRUN		(1 << 14)
#define	INT_FIFO_FULL			(1 << 15)
#define	INT_FIFO_HALF_FULL		(1 << 16)
#define	INT_FIFO_OVERRUN		(1 << 17)


#define	INT_CMD_ERROR			(0x0F << 5)
#define	INT_DATA_ERROR			(0x07 << 9)
#define	INT_FIFO_ERROR			(INT_FIFO_UNDERRUN | INT_FIFO_OVERRUN )

#define	INT_ERROR				( INT_CMD_ERROR | INT_DATA_ERROR | INT_FIFO_ERROR )

#define	INT_CMD_ENABLE_MASK		( INT_CARD_INSERT | INT_CARD_REMOVE | INT_CMD_COMPLETE | INT_TRANS_COMPLETE		\
			| INT_CMD_ERROR )

#define	INT_TXD_ENABLE_MASK		( INT_CARD_INSERT | INT_CARD_REMOVE | INT_CMD_COMPLETE | INT_TRANS_COMPLETE		\
			| INT_DATA_ERROR | INT_FIFO_HALF_EMPTY )

#define	INT_RXD_ENABLE_MASK		( INT_CARD_INSERT | INT_CARD_REMOVE | INT_CMD_COMPLETE | INT_TRANS_COMPLETE		\
			| INT_DATA_ERROR | INT_FIFO_HALF_FULL )


#define	INT_FIFO_HALF_STAT		( INT_FIFO_HALF_EMPTY | INT_FIFO_HALF_FULL )


//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@

#define	SD_BLOCK_SIZE	512

#define	HC_FIFO_SIZE		64
#define	HC_HALF_FIFO_SIZE	(HC_FIFO_SIZE/2)

#define	HC_HALF_FIFO_WORDS	(HC_HALF_FIFO_SIZE/4)


int sdhcd_preinit( void );
int sdhcd_init( int pnp );
int sdhcd_open( int clk, int sysclk, int buswidth );
int sdhcd_close( void );
int sdhcd_fini( void );


void sdhcd_setPnP( int ena );
int sdhcd_isCardPresent( void );
int sdhcd_isCardMechWP( void );
int sdhcd_setCardInt( int ena );
int sdhcd_setBusWidth( int width );



#define	SD_FDO_MIN		100			//khz
#define	SD_FDO_MAX		400
#define	SD_FDO_DEFAULT	300

#define	SD_FPP_MIN		12500
#define	SD_FPP_MAX		25*1000

//#define SD_FPP_DEFAULT    (4*1000)
#define SD_FPP_DEFAULT    (8*1000)
//#define SD_FPP_DEFAULT    (10*1000)

#define	SD_FPP_TYPICAL	20*1000
#define	SD_FPP_TEST	2*1000

#define	SD_FPP_HISPEED	50*1000

int sdhcd_setClk( int khz, int sysclk );


typedef	enum {
	enTM_PIO,
	enTM_PIO_DMA
}	enTRANS_MODE;

void sdhcd_setTransMode( U8 mode );




typedef	enum {
	enTRANS_OK,
	enTRANS_TIMEOUT,
	enTRANS_FAIL,
	enTRANS_CARD_REMOVED,

	enTRANS_RESP_ERR
}	enSDHCD_TRANS_RESULT;

int sdhcd_transferProtocol
	( 
		const CARD_CMD *pcmd, U32 argu,		//cmd
		U32 *resp,							//response
		U8 *buffer, U32 *blks,	U32 *bytes,	//data
		U32	*intstat
	);

#endif