#include "c_def.h"
#include "debug.h"
#include "oem.h"


#if 1//def FLASH_PROGRAM_ENABLE

#include "regmap.h"


#ifdef SPI_FLASH_WINBOND

#include "mem_reloc.h"

#include "SpiFlash_W25QXX.h"
#include "app_flash_program.h"


//#undef static
#define static


//#define FLASH_PROGRAM_DUMMY


#undef SDRAM_ENABLE

#if 1//ndef SDRAM_ENABLE
static U32 Endian_32_Convert(U32 addr) __INTERNAL_RAM_TEXT;
static U32 Page_Address_Get(U32 addr) __INTERNAL_RAM_TEXT;
static void W25QXX_Page_Program_Cmd(U32 page_num) __INTERNAL_RAM_TEXT;
static void W25QXX_Erase_Cmd(U32 addr, U8 erase_mode) __INTERNAL_RAM_TEXT;
void W25QXX_Sector_Erase(U32 sector_addr) __INTERNAL_RAM_TEXT;
U8 W25QXX_Sector_Write(U32 sector_addr, U32 *pBuf, U32 byte_len) __INTERNAL_RAM_TEXT;
#endif


#define CHIP_ERASE_CMD0        0xC7
#define CHIP_ERASE_CMD1        0x60

#define BLOCK_ERASE_32K_CMD    0x52
#define BLOCK_ERASE_64K_CMD    0xD8

#define BLOCK_ERASE_CMD        0xD8
#define SECTOR_ERASE_CMD       0x20

#define PAGE_PROGRAM_CMD                0x02
#define QUAD_INPUT_PAGE_PROGRAM_CMD     0x32

#define READ_CMD                        0x03
#define FAST_READ_CMD                   0x0B
#define FAST_READ_DUAL_OUTPUT_CMD       0x3B
#define FAST_READ_QUAD_OUTPUT_CMD       0x6B
#define FAST_READ_DATA_DUAL_IO_CMD      0xBB
#define FAST_READ_DATA_QUAD_IO_CMD      0xEB


#define POWER_DOWN_CMD        0xB9

#define HIGH_PERFORMANCE_CMD  0xA3

#define READ_DEVICE_ID_CMD    0x90

#define READ_UNIQUE_ID_CMD    0x4B

#define READ_JEDEC_ID_CMD     0x9F


#define QUAD_ENABLE           0x0200
#define QUAD_DISABLE          0x0000



#define SPI_FLASH_BUSY         (ADDR_SPI_STATUS & SPI_FLASH_BUSY_MASK)

#define SPI_FLASH_BASE_ADDR      FLASH_BASE_ADDR

//#define FLASH_FAST_PROGRAM

#define FLASH_PROGRAM_PAGE_CONVERT


void W25QXX_Init(void)
{
#ifdef SPI_FLASH_TEST
	U8 tmp_8;
	U16 tmp_16;
	U32 tmp_32;
	U64 tmp_64;

	tmp_32 = ADDR_SPI_JEDEC_ID;
	DBG_FlashPrintf("JEDEC_ID:0x%x\n\r", tmp_32);
	delayms(50);

	tmp_64 = ADDR_SPI_UNIQUE_ID;
	DBG_FlashPrintf("UMIQUE ID:0x%x\n\r", tmp_64);

	//write enable;
	ADDR_SPI_WR_ENABLE = 0;
	while(SPI_FLASH_BUSY);

	//Set Flash 4 Bit Mode;
	ADDR_SPI_WR_STATUS_2BYTES = QUAD_ENABLE;
	while(SPI_FLASH_BUSY);

	tmp_8 = ADDR_SPI_STATUS;
	DBG_FlashPrintf ("Status:0x%x\n\r", tmp_8);
	delayms(25);

	tmp_8 = ADDR_SPI_STATUS2;
	DBG_FlashPrintf ("Status 2:0x%x\n\r", tmp_8);
	delayms(25);

#else

#if 0
	U8 tmp;

	ADDR_SPI_WR_ENABLE = 0;
	//while(SPI_FLASH_BUSY);
	while (1)
	{
		tmp = SPI_FLASH_BUSY;
		if (!tmp)
		{
			break;
		}
	}

	ADDR_SPI_MODE_BIT_RESET = 0;

	//while(SPI_FLASH_BUSY);
	while (1)
	{
		tmp = SPI_FLASH_BUSY;
		if (!tmp)
		{
			break;
		}
	}
#endif

#endif
}

void W25QXX_Open(void)
{
}

void W25QXX_Close(void)
{
#if 0
	asm("movi   a2, 0x58ff0530");
	asm("l8ui   a2, a2, 0");
#endif
}

U8 W25QXX_Status_Get(void)
{
	U8 tmp;
	
	tmp = ADDR_SPI_STATUS;
	return tmp;
}

/*
static void Delay_ForCacheEable(U32 count)
{
	while (count--);
}
*/

static U32 Endian_32_Convert(U32 addr)
{
	U8 *pAddr;
	U8 *pSwapAddr;
	U32 tmp;

	pAddr = (U8 *)&addr;
	pSwapAddr = (U8 *)&tmp;

	*pSwapAddr++ =  *(pAddr + 3);
	*pSwapAddr++ =  *(pAddr + 2);
	*pSwapAddr++ =  *(pAddr + 1);
	*pSwapAddr =  *(pAddr + 0);

	return tmp;
}

static U32 Page_Address_Get(U32 addr)
{
	U8 *pAddr;
	U8 *pSwapAddr;
	U32 tmp;

	pAddr = (U8 *)&addr;
	pSwapAddr = (U8 *)&tmp;

	/*0x00ABCDEF->0x00EFCDAB*/
	*pSwapAddr++ =  *(pAddr + 2);
	*pSwapAddr++ =  *(pAddr + 1);
	*pSwapAddr++ =  *(pAddr + 0);
	*pSwapAddr =  *(pAddr + 3);

	return tmp;
}

static void W25QXX_Page_Program_Cmd(U32 page_num)
{
	U32 pageAddr;
	U8 tmp;

	ADDR_SPI_WR_ENABLE = 0;

#ifdef CACHE_ENABLE
	delayus(1);
	//Delay_ForCacheEable(1);
#endif

	//while(SPI_FLASH_BUSY);
	while (1)
	{
		tmp = SPI_FLASH_BUSY;
		if (!tmp)
		{
			break;
		}
	}

	pageAddr = Page_Address_Get(page_num);

#ifdef FLASH_FAST_PROGRAM
	ADDR_SPI_FAST_PAGE_PROGRAM = pageAddr;
#else
	ADDR_SPI_PAGE_PROGRAM = pageAddr;
#endif

#ifdef SDRAM_DISABLE

#endif
}

enum {
 FLASH_SECTOR_ERASE,
 FLASH_BLOCK_ERASE,
 FLASH_CHIP_ERASE,
};

static void W25QXX_Erase_Cmd(U32 addr, U8 erase_mode)
{
	U32 swapAddr;
	U8 tmp;

	//write enable;
	ADDR_SPI_WR_ENABLE = 0;

#ifdef CACHE_ENABLE
	delayus(1);
	//Delay_ForCacheEable(1);
#endif

	//while(SPI_FLASH_BUSY);
	while (1)
	{
		tmp = SPI_FLASH_BUSY;
		if (!tmp)
		{
			break;
		}
	}

	//tmp = ADDR_SPI_STATUS;
	//DBG_FlashPrintf ("Status:0x%x\n\r", tmp);
	//delayms(25);

	swapAddr = Endian_32_Convert(addr);

	if (erase_mode == FLASH_SECTOR_ERASE)
	{
		ADDR_SPI_SECTOR_ERASE = swapAddr;
	}
	else if (erase_mode == FLASH_BLOCK_ERASE)
	{
		ADDR_SPI_BLOCK_ERASE = swapAddr;
	}
	else if (erase_mode == FLASH_CHIP_ERASE)
	{
		ADDR_SPI_CHIP_ERASE = 0;
	}
	else
	{
		DBG_FlashAssert(FALSE);
	}
}

void W25QXX_Chip_Erase(void)
{
	U8 tmp;

	DBG_FlashPrintf("Chip Erase.\n\r");

	W25QXX_Erase_Cmd(0, FLASH_CHIP_ERASE);

	delayms(10);

	//while(SPI_FLASH_BUSY);
	while (1)
	{
		tmp = SPI_FLASH_BUSY;
		if (!tmp)
		{
			break;
		}
	}
}

void W25QXX_Sector_Erase(U32 sector_addr)
{
	U8 tmp;
	U32 swapAddr;

	W25QXX_Erase_Cmd(sector_addr, FLASH_SECTOR_ERASE);

#ifdef CACHE_ENABLE
	delayus(1);
	//Delay_ForCacheEable(1);
#endif


#if 1//def BT_HCI_ENABLE
	//app_timer_upgradeTimeoutTimer_set(500); //500ms
	//app_timer_upgradeTimeoutTimer_set(1000); //1s
	//@app_timer_upgradeTimeoutTimer_set(10000); //10s
#endif

	//while(SPI_FLASH_BUSY);
	while (1)
	{
		tmp = SPI_FLASH_BUSY;
		if (!tmp)
		{
			break;
		}
	}

	DBG_FlashPrintf("Erase:addr-0x%x.\n\r", sector_addr);

#ifndef SDRAM_ENABLE
	delayus(10);
#endif
}

void W25QXX_Block_Erase(U32 block_addr)
{
	U8 tmp;
	U32 swapAddr;

	W25QXX_Erase_Cmd(block_addr, FLASH_BLOCK_ERASE);

#ifdef CACHE_ENABLE
	delayus(1);
	//Delay_ForCacheEable(1);
#endif

#ifdef BT_HCI_ENABLE
	//app_timer_upgradeTimeoutTimer_set(500); //500ms
	//app_timer_upgradeTimeoutTimer_set(1000); //1s
	//@app_timer_upgradeTimeoutTimer_set(10000); //10s
#endif

	//while(SPI_FLASH_BUSY);
	while (1)
	{
		tmp = SPI_FLASH_BUSY;
		if (!tmp)
		{
			break;
		}
	}

	DBG_FlashPrintf("Erase:addr-0x%x.\n\r", block_addr);
}

void DataCache_Clean(void);

U8 W25QXX_Erase_Verify(U32 addr, U32 byte_len)
{
	U32 *pAddr;
	U32 tmp;
	U32 i;

	DBG_FlashAssert(addr >= SPI_FLASH_BASE_ADDR);

	if (byte_len == 0)
	{
		return FALSE;
	}

	pAddr = (U32 *) addr;

	DataCache_Clean();

	for (i=0; i<(byte_len/4); i++)
	{
		tmp = *pAddr++;
		if (tmp != 0xFFFFFFFF)
		{
			DBG_FlashPrintf("Erase Check Err:addr-0x%x-%d.\n\r", addr, i);
			//DBG_FlashPrintf("Block Erase Err:0x%x\n\r", block_addr);
			DBG_FlashPrintf("Val:0x%x\n\r", tmp);
			return FALSE;
		}
	}

	//DBG_FlashPrintf("Erase Ok:addr-0x%x\n\r", addr);
	return TRUE;
}

U8 W25QXX_Page_Write(U32 page_addr, U32 *pBuf, U32 byte_len)
{
#if 1
	U32 tmp;
	U32 i;
	U32 *pSrc;
	U32 *pDest;
	U8 *pSrc_Byte;
	U8 *pDest_Byte;
	U32 page_num;
#ifndef FLASH_PROGRAM_PAGE_CONVERT
	U32 swapAddr;
	U32 addr;
#endif

	DBG_FlashAssert(page_addr >= SPI_FLASH_BASE_ADDR);
	DBG_FlashAssert((byte_len <= FLASH_PAGE_SIZE));

	if (byte_len == 0)
	{
		return FALSE;
	}

	pSrc = pBuf;
	pDest = (U32 *) page_addr;

#ifndef FLASH_PROGRAM_PAGE_CONVERT
	addr = (page_addr - SPI_FLASH_BASE_ADDR);
#else
	page_num = (page_addr - SPI_FLASH_BASE_ADDR)/FLASH_PAGE_SIZE;
#endif

#if 0
#ifndef FLASH_PROGRAM_PAGE_CONVERT
	swapAddr = Endian_32_Convert(addr);
	W25QXX_Page_Program_Cmd(swapAddr);
#else
	W25QXX_Page_Program_Cmd(page_num);
#endif

	for (i=0; i<(FLASH_PAGE_SIZE/4); i++)
	{
		*pDest++ = *pSrc++;
	}

#ifdef CACHE_ENABLE
	delayus(1);
	//Delay_ForCacheEable(1);
#endif

	while(SPI_FLASH_BUSY);

#else
	tmp = byte_len;

#ifndef FLASH_PROGRAM_PAGE_CONVERT
	swapAddr = Endian_32_Convert(addr);
	W25QXX_Page_Program_Cmd(swapAddr);
#else
	W25QXX_Page_Program_Cmd(page_num);
#endif

	while (tmp >= 4)
	{
		*pDest++ = *pSrc++;
		tmp -= 4;
	}

	pSrc_Byte = (U8 *)pSrc;
	pDest_Byte = (U8 *)pDest;

	while (tmp > 1)
	{
		*pSrc_Byte++ = *pDest_Byte++;
		tmp -= 1;
	}

#ifdef CACHE_ENABLE
	delayus(1);
	//Delay_ForCacheEable(1);
#endif

	while(SPI_FLASH_BUSY);
#endif

	return TRUE;
#endif
}

U8 W25QXX_Sector_Write(U32 sector_addr, U32 *pBuf, U32 byte_len)
{
#if 1
	U32 tmp;
	U32 i;
	U32 j;
	U32 *pSrc;
	U32 *pDest;
	U8 *pSrc_Byte;
	U8 *pDest_Byte;
	U32 page_size;
	U32 page_num;
#ifndef FLASH_PROGRAM_PAGE_CONVERT
	U32 swapAddr;
	U32 addr;
#endif

	DBG_FlashAssert(sector_addr >= SPI_FLASH_BASE_ADDR);
	DBG_FlashAssert((byte_len <= FLASH_SECTOR_SIZE));

	if (byte_len == 0)
	{
		return FALSE;
	}
	
	pSrc = pBuf;
	pDest = (U32 *) sector_addr;

#ifndef FLASH_PROGRAM_PAGE_CONVERT
	addr = (sector_addr - SPI_FLASH_BASE_ADDR);
#else
	page_num = (sector_addr - SPI_FLASH_BASE_ADDR)/FLASH_PAGE_SIZE;
#endif

#if 0
	page_size = (byte_len + FLASH_PAGE_SIZE - 1) / FLASH_PAGE_SIZE;

	for (i=0; i<page_size; i++)
	{
#ifndef FLASH_PROGRAM_PAGE_CONVERT
		swapAddr = Endian_32_Convert(addr);
		W25QXX_Page_Program_Cmd(swapAddr);
#else
		W25QXX_Page_Program_Cmd(page_num);
#endif

		for (j=0; j<(FLASH_PAGE_SIZE/4); j++)
		{
			*pDest++ = *pSrc++;
		}

#ifdef CACHE_ENABLE
		delayus(1);
		//Delay_ForCacheEable(1);
#endif
		
		while(SPI_FLASH_BUSY);

#ifndef FLASH_PROGRAM_PAGE_CONVERT
		addr += FLASH_PAGE_SIZE;
#else
		page_num++;
#endif
	}

#else
	page_size = byte_len/FLASH_PAGE_SIZE;

	for (i=0; i<page_size; i++)
	{
#ifndef FLASH_PROGRAM_PAGE_CONVERT
		swapAddr = Endian_32_Convert(addr);
		W25QXX_Page_Program_Cmd(swapAddr);
#else
		W25QXX_Page_Program_Cmd(page_num);
#endif

		for (j=0; j<(FLASH_PAGE_SIZE/4); j++)
		{
#if 0//for debug
			if (pDest == (U32 *)(0x58000000+0x808) )
			{
				DBG_Printf("Addr:0x%x, w_val:0x%x\n\r", pDest, *pSrc);
			}

			if (pDest == (U32 *)(0x58003000+0x808) )
			{
				DBG_Printf("Addr:0x%x, w_val:0x%x\n\r", pDest, *pSrc);
			}

			if (pDest == (U32 *)(0x58004000+0x808) )
			{
				DBG_Printf("Addr:0x%x, w_val:0x%x\n\r", pDest, *pSrc);
			}

			if (pDest == (U32 *)(0x58005000+0x808) )
			{
				DBG_Printf("Addr:0x%x, w_val:0x%x\n\r", pDest, *pSrc);
			}

			if (pDest == (U32 *)(0x5800c000+0x808) )
			{
				DBG_Printf("Addr:0x%x, w_val:0x%x\n\r", pDest, *pSrc);
			}
#endif

			*pDest++ = *pSrc++;
		}

#ifdef CACHE_ENABLE
		delayus(1);
		//Delay_ForCacheEable(1);
#endif

		while(SPI_FLASH_BUSY);

#ifndef FLASH_PROGRAM_PAGE_CONVERT
		addr += FLASH_PAGE_SIZE;
#else
		page_num++;
#endif
	}

	//page remainder
	tmp = byte_len - page_size*FLASH_PAGE_SIZE;

	if (tmp)
	{
#ifndef FLASH_PROGRAM_PAGE_CONVERT
		swapAddr = Endian_32_Convert(addr);
		W25QXX_Page_Program_Cmd(swapAddr);
#else
		W25QXX_Page_Program_Cmd(page_num);
#endif

		while (tmp >= 4)
		{
			*pDest++ = *pSrc++;
			tmp -= 4;
		}

		pSrc_Byte = (U8 *)pSrc;
		pDest_Byte = (U8 *)pDest;

		while (tmp > 1)
		{
#if 0
			if (pDest == (U32 *)(0x5800c000+0x808) )
			{
				DBG_Printf("Addr:0x%x, w_val:0x%x\n\r", pDest, *pSrc);
			}
#endif

			*pSrc_Byte++ = *pDest_Byte++;
			tmp -= 1;
		}

#ifdef CACHE_ENABLE
		delayus(1);
		//Delay_ForCacheEable(1);
#endif

		while(SPI_FLASH_BUSY);
	}
#endif


#ifndef SDRAM_ENABLE
	delayus(10);
#endif

	return TRUE;
#endif
}


#if 1
//for saving code space
U8 W25QXX_Block_Write(U32 block_addr, U32 *pBuf, U32 byte_len)
{
	DBG_Assert(FALSE);
}

#else
#define UPGRADE_BUF_64K

U8 W25QXX_Block_Write(U32 block_addr, U32 *pBuf, U32 byte_len)
{
#ifdef UPGRADE_BUF_64K
	U32 tmp;
	U32 i;
	U32 j;
	U32 *pSrc;
	U32 *pDest;
	U8 *pSrc_Byte;
	U8 *pDest_Byte;
	U32 page_size;
	U32 page_num;
	//U32 offset;

	DBG_FlashAssert(block_addr >= SPI_FLASH_BASE_ADDR);
	DBG_FlashAssert((byte_len <= FLASH_BLOCK_SIZE));

	if (byte_len == 0)
	{
		return FALSE;
	}

	pSrc = pBuf;
	pDest = (U32 *) block_addr;
	//offset = 0;

	page_num = (block_addr - SPI_FLASH_BASE_ADDR)/FLASH_PAGE_SIZE;

#if 0
	page_size = (byte_len + FLASH_PAGE_SIZE - 1) / FLASH_PAGE_SIZE;

	for (i=0; i<page_size; i++)
	{		
		W25QXX_Page_Program_Cmd(page_num);
		
		for (j=0; j<(FLASH_PAGE_SIZE/4); j++)
		{
			*pDest++ = *pSrc++;
		}

#ifdef CACHE_ENABLE
		delayus(1);
		//Delay_ForCacheEable(1);
#endif

		while(SPI_FLASH_BUSY);
		page_num++;
	}

#else
	page_size = byte_len/FLASH_PAGE_SIZE;

	for (i=0; i<page_size; i++)
	{
		W25QXX_Page_Program_Cmd(page_num);
		
		for (j=0; j<(FLASH_PAGE_SIZE/4); j++)
		{
#if 0
			if (pDest == (U32 *)(0x58000000+0x858) )
			{
				DBG_Printf("Addr:0x%x, w_val:0x%x\n\r", pDest, *pSrc);
			}
#endif

			*pDest++ = *pSrc++;
		}

#ifdef CACHE_ENABLE
		delayus(1);
		//Delay_ForCacheEable(1);
#endif

		while(SPI_FLASH_BUSY);
		page_num++;
	}

	//page remainder
	tmp = byte_len - page_size*FLASH_PAGE_SIZE;

	if (tmp)
	{
		W25QXX_Page_Program_Cmd(page_num);

		while (tmp >= 4)
		{
#if 0
			if (pDest == (U32 *)(0x58000000+0x858) )
			{
				DBG_Printf("Addr:0x%x, w_val:0x%x\n\r", pDest, *pSrc);
			}
#endif

			*pDest++ = *pSrc++;
			tmp -= 4;
			//offset += 4;
		}

		pSrc_Byte = (U8 *)pSrc;
		pDest_Byte = (U8 *)pDest;

		while (tmp > 1)
		{
			*pSrc_Byte++ = *pDest_Byte++;
			tmp -= 1;
			offset += 1;
		}

#ifdef CACHE_ENABLE
		delayus(1);
		//Delay_ForCacheEable(1);
#endif

		while(SPI_FLASH_BUSY);
	}
#endif

#endif //UPGRADE_BUF_64K
}
#endif


U8 W25QXX_Write_Verify(U32 addr, U32 *pBuf, U32 byte_len)
{
	U32 tmp;
	U32 *pSrc;
	U32 *pDest;
	U8 *pSrc_Byte;
	U8 *pDest_Byte;
	U8 ret = TRUE;
	long offset;
	long temp_dest, temp_src;

	DBG_FlashAssert(addr >= SPI_FLASH_BASE_ADDR);
	DBG_FlashAssert( ( !(addr & 0x03) ) );

	if (byte_len == 0)
	{
		return FALSE;
	}

	pSrc = pBuf;
	pDest = (U32 *) addr;
	offset = 0;

	tmp = byte_len;

	while (tmp >= 4)
	{
#if 1//for debug
		temp_dest = *pDest++;
		temp_src = *pSrc++;
		if (temp_dest != temp_src)
#else
		if (*pDest++ != *pSrc++)
#endif
		{
			ret = FALSE;

#if 1 //for debug
			DBG_FlashPrintf("verify Err:block addr-0x%x, offset:0x%x\n\r", addr, offset);
			delayms(10);
			DBG_FlashPrintf("value in sFlash:0x%x, value in upgrade file :0x%x\n\r", temp_dest, temp_src);
			delayms(10);
#endif

			break;
		}

		tmp -= 4;
		offset += 4;
	}

	if (tmp > 1)
	{
		pSrc_Byte = (U8 *)pSrc;
		pDest_Byte = (U8 *)pDest;

		while (tmp > 1)
		{
			if (*pDest_Byte++ != *pSrc_Byte++)
			{
				ret = FALSE;				
				break;
			}

			tmp -= 1;
		}
	}

	return ret;
}

U8 W25QXX_Read_Data(U32 addr, U32 *pBuf, U32 byte_len)
{
	U32 tmp;
	U32 *pSrc;
	U32 *pDest;
	U8 *pSrc_Byte;
	U8 *pDest_Byte;
	U8 ret = TRUE;

	DBG_FlashAssert(addr >= SPI_FLASH_BASE_ADDR);
	DBG_Assert(!(addr & 0x03));

	if (byte_len == 0)
	{
		return FALSE;
	}

	pSrc = pBuf;
	pDest = (U32 *) addr;

	tmp = byte_len;

	while (tmp >= 4)
	{
		if (*pDest != *pSrc)
		{
			*pSrc = *pDest;
		}

		pSrc++;
		pDest++;
		tmp -= 4;
	}

	if (tmp > 1)
	{
		pSrc_Byte = (U8 *)pSrc;
		pDest_Byte = (U8 *)pDest;

		while (tmp > 1)
		{
			if (*pDest_Byte++ != *pSrc_Byte++)
			{
				*pSrc_Byte = *pDest_Byte;				
			}

			pDest_Byte++;
			pSrc_Byte++;
			tmp -= 1;
		}
	}

	return TRUE;
}

#endif //SPI_FLASH_WINBOND

#endif //FLASH_PROGRAM_ENABLE