l1d_data.h
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/*****************************************************************************
* Copyright Statement:
* --------------------
* This software is protected by Copyright and the information contained
* herein is confidential. The software may not be copied and the information
* contained herein may not be used or disclosed except with the written
* permission of MediaTek Inc. (C) 2005
*
* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
*
* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
*
* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
*
*****************************************************************************/
/*******************************************************************************
*
* Filename:
* ---------
* l1d_data.h
*
* Project:
* --------
* MT6208
*
* Description:
* ------------
* Definition of global data & tables used in L1D
*
* Author:
* -------
* -------
*
*------------------------------------------------------------------------------
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*******************************************************************************/
#ifndef _L1D_DATA_H_
#define _L1D_DATA_H_
/*---------------------------------------------------------------------------*/
#if IS_RF_TOOL_CUSTOMIZATION_SUPPORT || IS_RF_TOOL_CUSTOMIZATION_SUPPORT_V2
#define CONST
#else
#define CONST const
#endif
#if IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION
/*MT6229~*/ #define TQ_CTIRQ12_R23_DELAY 400
/*MT6229~*/ #if IS_CHIP_MT6251 /*GSM only*/
/*MT6229~*/ #define TQ_CTIRQ12_DELAY 0
/*MT6229~*/ #elif IS_CHIP_MT6253 /*Not support EDGE*/
/*MT6229~*/ #define TQ_CTIRQ12_DELAY 400 // 760
/*MT6229~*/ #elif IS_CHIP_MT6223 /*Not support EDGE*/
/*MT6229~*/ #if IS_GPRS
/*MT6229~*/ #define TQ_CTIRQ12_DELAY 400
/*MT6229~*/ #else /*GSM only */
/*MT6229~*/ #define TQ_CTIRQ12_DELAY 0
/*MT6229~*/ #endif
/*MT6229~*/ #elif IS_CHIP_MT6236 /*jason: for MPLL down hopping, need to gain 100 more for DSP*/
/*MT6229~*/ #define TQ_CTIRQ12_DELAY 860
/*MT6229~*/ #else /*Support EDGE*/
/*MT6229~*/ #define TQ_CTIRQ12_DELAY 760
/*MT6229~*/ #endif
#elif IS_CHIP_MT6218_AND_LATTER_VERSION /*&& !defined(L1D_TEST)*/ //For cosim and loopback, MCU will always run 104MHz
/*MT6218B~*/ #define TQ_CTIRQ12_R23_DELAY 400
/*MT6218B~*/ #define TQ_CTIRQ12_DELAY 400
#else
/*OTHERS*/ #define TQ_CTIRQ12_R23_DELAY 0
/*OTHERS*/ #define TQ_CTIRQ12_DELAY 0
#endif
#if defined(L1_SIM)
#undef TQ_CTIRQ12_DELAY
#if IS_FDD_DUAL_MODE_SUPPORT || IS_TDD_DUAL_MODE_SUPPORT
#define TQ_CTIRQ12_DELAY 760
#else
#define TQ_CTIRQ12_DELAY 400
#endif
#endif
#if IS_NEW_L1D_ARCH_SUPPORT
#if IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION
#undef TQ_CTIRQ12_DELAY
#define TQ_CTIRQ12_DELAY 0
#endif
#endif
#if IS_DSP_COSTDOWN_FB_CHIP
#define TQ_FSWIN_DTIRQ_DELATY_SLOT6 156 /*Set 100Qb before Slot0, for DSP has enough margin to deal FB data*/
#endif
#if defined(AFC_ALWAYS_CHARGE) || defined(AFC_VCXO)
//#define TQ_AFC_IDLE_LEN (5*(TQ_WRAP_COUNT/8))
/* For L1C may extend frame to 8 slot, 13>(4+8=12) */
#define TQ_AFC_IDLE_LEN (13*(TQ_WRAP_COUNT/8))
#else
//#define TQ_AFC_IDLE_LEN (13*(TQ_WRAP_COUNT/8))
/* For BT/WiFi to co-use 26MHz, keep AFC to always power on */
#define TQ_AFC_IDLE_LEN (TQ_AFC_READY+TQ_SLOT_LEN)
#endif
/*--------------------------------------------------------*/
/* define TSU event time in QB */
/*--------------------------------------------------------*/
#if IS_TDMA_CLIPPING_SUPPORT
#define TQ_MAXIMUM 16383 /*16383: 0x3FFF*/
#else
#define TQ_MAXIMUM (2*TQ_WRAP_COUNT+TQ_SLOT_LEN) /*10624: 2 frames + 1 slot*/
#endif
#define TQ_BURST_HEAD_GUARD 16
#define TQ_SLOT_LEN (156*4)
#define TQ_SLOT0_BEGIN (TQ_AFC_READY)
#define TQ_SLOT1_BEGIN (TQ_SLOT0_BEGIN+625)
#define TQ_SLOT2_BEGIN (TQ_SLOT1_BEGIN+625)
#define TQ_SLOT3_BEGIN (TQ_SLOT2_BEGIN+625)
#define TQ_SLOT4_BEGIN (TQ_SLOT3_BEGIN+625)
#define TQ_SLOT5_BEGIN (TQ_SLOT4_BEGIN+625)
#define TQ_SLOT6_BEGIN (TQ_SLOT5_BEGIN+625)
#define TQ_SLOT7_BEGIN (TQ_SLOT6_BEGIN+625)
#define TQ_TX2RX_LEN (TQ_SLOT3_BEGIN-TQ_SLOT0_BEGIN)
#define TQ_TX_SLOT0_BEGIN (TQ_SLOT0_BEGIN+TQ_TX2RX_LEN)
#define TQ_WRAP_COUNT 5000
#define TQ_VALIDATE_OFFSET 1
#define TQ_VALIDATE_COUNT (TQ_WRAP_COUNT-60-TQ_VALIDATE_OFFSET) /*4939*/
#define TQ_VALIDATE (TQ_VALIDATE_COUNT+TQ_VALIDATE_OFFSET) /*4940*/
#define TQ_CTIRQ1 (TQ_SLOT5_BEGIN+TQ_CTIRQ12_DELAY)
#if IS_NEW_L1D_ARCH_SUPPORT
#if IS_MT6276_ADCMUX_CHECK_CHIP
#define TQ_CTIRQ2 (TQ_SLOT0_BEGIN-200)
#else
#define TQ_CTIRQ2 (TQ_SLOT0_BEGIN)
#endif
#else
#define TQ_CTIRQ2 (TQ_SLOT4_BEGIN+TQ_CTIRQ12_DELAY)
#endif
#define TQ_DTIRQ 2
#define TQ_CTIRQ1_R23 (TQ_SLOT5_BEGIN+TQ_CTIRQ12_R23_DELAY)
#define TQ_CTIRQ2_R23 (TQ_SLOT4_BEGIN+TQ_CTIRQ12_R23_DELAY)
#if L1D_PM_ENHANCE
#define SHORT_PM_LEN 64
#define TQ_SHORT_PMWIN_LEN_IN_IDLE (SHORT_PM_LEN*4)
#if L1D_PM_1R7PM
#define PM_LEN_1R7PM 32
#define TQ_1R7PM_PMWIN_LEN_IN_IDLE (PM_LEN_1R7PM*4)
#endif
#endif
#define PM_LEN 64
#define TQ_SHORT_PMWIN_LEN (PM_LEN*4)
#if IS_AST_B2S_SUPPORT
#define TQ_AFC_READY 245
#define TQ_AFC_READY_RX 213
#else
#define TQ_AFC_READY 256
#define TQ_AFC_READY_RX TQ_AFC_READY
#endif
#define TQ_AFC_0_DEFAULT 0
#define TQ_AFC_1_DEFAULT TQ_SLOT4_BEGIN
#define TQ_AFC_2_DEFAULT TQ_SLOT4_BEGIN
#define TQ_AFC_CHARGE_IN_IDLE (TQ_AFC_IDLE_LEN)
#define TQ_AFC_CHARGE_IN_DEDI (13*(TQ_WRAP_COUNT/8))
#define TQ_AB_LEN (16+4*88+16)
#define TQ_AB_END_ADVANCED (TQ_SLOT_LEN-TQ_AB_LEN)
#if IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION
#define TQ_SBWIN_DSP_EXTEND1 52
#define TQ_SBWIN_DSP_EXTEND2 52
#else
#define TQ_SBWIN_DSP_EXTEND1 28
#define TQ_SBWIN_DSP_EXTEND2 28
#endif
#define TQ_SBWIN_LEN (TQ_SBWIN_DSP_EXTEND1+TQ_SLOT_LEN+TQ_SBWIN_DSP_EXTEND2)
#define TQ_FSWIN_STOP_FSYNC (TQ_VALIDATE+10)
#if IS_CHIP_MT6250 || IS_CHIP_MT6260 || IS_CHIP_MT6261
#define TQ_BSI_READ_TIME (TQ_SLOT0_BEGIN+TQ_SHORT_PMWIN_LEN-100)
#else
#define TQ_BSI_READ_TIME (TQ_SLOT0_BEGIN+TQ_SLOT_LEN-100)
#endif
// for switching FB algorithm on MT6229
#if IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION
#ifdef L1D_TEST
#define MT6229_FB_ON_MT6229 1
#define MT6229_FB_SCALING 1 //loopback and cosim should 1
#else
#define MT6229_FB_ON_MT6229 1
#define MT6229_FB_SCALING 1
#endif
#define MT6229_FB_VCXO 1
#else
#define MT6229_FB_ON_MT6229 0
#define MT6229_FB_SCALING 0
#define MT6229_FB_VCXO 0
#endif /*IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION*/
/* The 3rd stage FB algorithm of MT6229 sometime finds a FB but with bad QI. */
/* In the original design, DSP will try to decode SB automatically even if QI is bad. */
/* In order improve it, L1 will reset DSP to search FB again if FB with bad QI is detected */
#if MT6229_FB_ON_MT6229
#if IS_CHIP_MT6268T || (IS_EDGE_SAIC_CHIP_MT6268_AND_LATTER_VERSION && !IS_CHIP_MT6253T && !IS_CHIP_MT6516)
#define RESET_FB_WITH_BAD_QI 1
#else
#define RESET_FB_WITH_BAD_QI 0
#endif
#else
#define RESET_FB_WITH_BAD_QI 0
#endif
/* ------------------------------------------------------------------------- */
/* todo : remeber to change the enable flag definition in l1d_reg.h */
#if IS_FPGA_TARGET || IS_CHIP_MT6208
/*FPGA,MT6208*/ #define AFCEN(n) ((n)<<3)
/*FPGA,MT6208*/ #define AFCEN3 (0x8000)
#endif
#if IS_CHIP_MT6205_AND_LATTER_VERSION || IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION
/*MT6205~*/#define AFCEN(n) ((n)<<12)
/*MT6205~*/#define AFCEN3 (0x8000)
#endif
#if IS_CHIP_MT6205
/*MT6205*/ #define BSI_EVENT_COUNT 13
/*MT6205*/ #define BSI_DATA_COUNT 22
#elif IS_CHIP_MT6208 || IS_CHIP_MT6218 || IS_CHIP_MT6219
/*MT6218*/ #define BSI_EVENT_COUNT 16
/*MT6218*/ #define BSI_DATA_COUNT 26
#elif IS_CHIP_MT6227_AND_LATTER_VERSION
/*MT6227*/ #define BSI_EVENT_COUNT 16
/*MT6227*/ #define BSI_DATA_COUNT 27
#elif IS_CHIP_MT6268T_DMAC
/*MT6270*/ #define BSI_EVENT_COUNT 20 // DE JC Lin comment: align 68A
/*MT6270*/ #define BSI_DATA_COUNT 65
#elif IS_CHIP_MT6268H
/*MT6270*/ #define BSI_EVENT_COUNT 36
/*MT6270*/ #define BSI_DATA_COUNT 104
#elif IS_EDGE_SAIC_CHIP_MT6270A_AND_LATTER_VERSION
#if IS_CHIP_MT6270A_E1 || IS_CHIP_MT6276_S00 || IS_CHIP_MT6573
/*MT6270*/ #define BSI_EVENT_COUNT 36 // for MT6270A E1, MT6276E1, MT6573
/*MT6270*/ #define BSI_DATA_COUNT 104 // for MT6270A E1, MT6276E1, MT6573
#else
/*MT6270*/ #define BSI_EVENT_COUNT 42 // for MT6270A E2, MT6276E2
/*MT6270*/ #define BSI_DATA_COUNT 128 // for MT6270A E2, MT6276E2
#endif
#elif IS_EDGE_SAIC_CHIP_MT6256_AND_LATTER_VERSION
#if IS_CHIP_MT6256_S00 || IS_CHIP_MT6251
/*MT6256*/ #define BSI_EVENT_COUNT 36
/*MT6256*/ #define BSI_DATA_COUNT 64
#elif IS_CHIP_MT6261
/*MT6261*/ #define BSI_EVENT_COUNT 21
/*MT6261*/ #define BSI_DATA_COUNT 42
#else
/*MT6256*/ #define BSI_EVENT_COUNT 21
/*MT6256*/ #define BSI_DATA_COUNT 40
#endif
#elif IS_CHIP_MT6252
/*MT6252*/ #define BSI_EVENT_COUNT 21
/*MT6252*/ #define BSI_DATA_COUNT 32
#elif IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION
/*MT6229*/ #define BSI_EVENT_COUNT 20
/*MT6229*/ #define BSI_DATA_COUNT 44
#endif
#if IS_EDGE_SAIC_CHIP_MT6270A_AND_LATTER_VERSION || IS_CHIP_MT6268 || IS_EDGE_SAIC_CHIP_MT6256_AND_LATTER_VERSION || IS_CHIP_MT6252
/*MT6252*/ #define BSI_DATA_COUNT_SW_LIMIT BSI_DATA_COUNT
#elif IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION
/*MT6229*/ #define BSI_DATA_COUNT_SW_LIMIT 40 // the maximum control words length of BSI data 40~43 is 78 bits, which is not support by L1D
#else
/*OTHERS*/ #define BSI_DATA_COUNT_SW_LIMIT BSI_DATA_COUNT
#endif
/* ------------------------------------------------------------------------- */
#if IS_GPRS || IS_MULTISLOT_TX_SUPPORT
#if IS_5_BANK_RAMP_PROFILES_SUPPORT
#define S2_S3_APC_IDX 3
#define S3_S4_APC_IDX 4
#elif IS_6_BANK_RAMP_PROFILES_SUPPORT
#define S2_S3_APC_IDX 3
#define S3_S4_APC_IDX 5
#elif IS_7_BANK_RAMP_PROFILES_SUPPORT
#define S2_S3_APC_IDX 5
#define S3_S4_APC_IDX 6
#endif
#endif
/* ------------------------------------------------------------------------- */
#if !IS_RTX_5CWIN_SUPPORT // IS_GSM
#if IS_BPI_V2_SUPPORT
/*GSM*/ #define BPIRES1 20
/*GSM*/ #define BPIRES2 20
/*GSM*/ #define PT2M_EV(m,n) (21+3*(m)+(n))
/*GSM*/ #define PR3A_EV(n) BPIDX(n,3)
#elif IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION
/*GSM*/ #define BPIRES1 40
/*GSM*/ #define BPIRES2 41
/*GSM*/ #define PT2M_EV(m,n) (26+3*(m)+(n))
/*GSM*/ #define PR3A_EV(n) (35+(n))
#else
/*GSM*/ #define BPIRES 12
#endif
/*GSM*/
/*GSM*/ #define FS_CWIN_IDX 2
/*GSM*/ #define FS_RXWIN_IDX 2
/*GSM*/ #define FS_AFC_IDX 3
/*GSM*/ #define FS_AFC_EN AFCEN3
/*GSM*/
/*GSM*/ #define PM7_RXWIN_IDX 3
/*GSM*/
/*GSM*/ #define AGCEV0 (CWIN_BSI_EVENT_COUNT*CWIN_COUNT)
#endif
#if IS_RTX_5CWIN_SUPPORT // IS_GPRS
#if IS_BPI_V2_SUPPORT
/*GPRS*/ #define BPIRES1 20
/*GPRS*/ #define BPIRES2 20
/*GPRS*/ #define PT2M_EV(m,n) (21+3*(m)+(n))
/*GPRS*/ #define PR3A_EV(n) BPIDX(n,3)
#elif IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION
/*GPRS*/ #define BPIRES1 40
/*GPRS*/ #define BPIRES2 41
/*GPRS*/ #define PT2M_EV(m,n) (26+3*(m)+(n))
/*GPRS*/ #define PR3A_EV(n) (35+(n))
#else
/*GPRS*/ #define BPIRES 15
#endif
/*GPRS*/
/*GPRS*/ #define FS_CWIN_IDX 3
/*GPRS*/ #define FS_RXWIN_IDX 4
/*GPRS*/ #define FS_AFC_IDX 3
/*GPRS*/ #define FS_AFC_EN AFCEN3
/*GPRS*/
/*GPRS*/ #define PM7_RXWIN_IDX 5
/*GPRS*/
/*GPRS*/ #define AGCEV0 (CWIN_BSI_EVENT_COUNT*CWIN_COUNT)
#endif
/* ------------------------------------------------------------------------- */
#define AGCIDX(n) (AGCEV0+(n))
#if IS_BSI_SX0_SUPPORT
#define BSI_GROUP_COUNT 3
#define BSIDX(m,n) ((m)*BSI_GROUP_COUNT+(n)+1)
#else
#define BSI_GROUP_COUNT 2
#define BSIDX(m,n) ((m)*BSI_GROUP_COUNT+(n))
#endif
#define BSIEN(m,n) (1<<BSIDX(m,n))
#define BSIEN_X(n) (1<<AGCIDX(n))
#define BSIENALL(m) ((1<<(BSI_GROUP_COUNT*(m)))-1)
#if IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION
#define BPI_GROUP_COUNT 4
#else
#define BPI_GROUP_COUNT 3
#endif
#define BPIDX(m,n) ((m)*BPI_GROUP_COUNT+(n))
#define BPIEN(m,n) (1<<BPIDX(m,n))
#define BPIENALL(m) ((1<<(BPI_GROUP_COUNT*(m)))-1)
/* ------------------------------------------------------------------------- */
#if IS_FPGA_TARGET || IS_CHIP_MT6208
/*FPGA,MT6208*/ #define PCTRL_INITIAL 0x0001 /* the initial bus status */
/*FPGA,MT6208*/ #define PCTRL_MAIN 0x0000 /* BPI main control value : ctrl. by TSU */
/*FPGA,MT6208*/ /* ------------------------------------------------------------------------------------- */
#endif
#if IS_CHIP_MT6205_AND_LATTER_VERSION || IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION
#if IS_EDGE_SAIC_CHIP_MT6270A_AND_LATTER_VERSION || IS_CHIP_MT6268H || IS_AST_B2S_SUPPORT
/*MT6270~*/ #define PCTRL_INITIAL 0x03FE /* The output driving capability of BPI0~4 is 8mA */
/*MT6270~*/ #define PCTRL_MAIN 0x03FE /* The output driving capability of BPI0~4 is 8mA */
/*MT6270~*/ /* ----------------------------------------------------------------------------------------- */
#elif IS_CHIP_MT6260 || IS_CHIP_MT6261
/*MT6260 */ #define PCTRL_INITIAL 0x0001 /* The output driving is moved to GPIO */
/*MT6260 */ #define PCTRL_MAIN 0x0000 /* The output driving is moved to GPIO */
/*MT6268~*/ /* ----------------------------------------------------------------------------------------- */
#elif IS_CHIP_MT6268
/*MT6268~*/ #define PCTRL_INITIAL 0x003F /* The output driving capability of BPI0~4 is 8mA */
/*MT6268~*/ #define PCTRL_MAIN 0x003E /* The output driving capability of BPI0~4 is 8mA */
/*MT6268~*/ /* ----------------------------------------------------------------------------------------- */
#else
/*MT6229~*/ #define PCTRL_INITIAL 0x000F /* The output driving capability of BPI0~2 is 8mA */
/*MT6229~*/ #define PCTRL_MAIN 0x000E /* The output driving capability of BPI0~2 is 8mA */
/*MT6229~*/ /* ----------------------------------------------------------------------------------------- */
#endif
#endif
#if IS_CHIP_MT6260 || IS_CHIP_MT6261
#define L1D_SET_BPI_IMM_MODE_BEGIN() HW_WRITE( BPI_CON, PCTRL_INITIAL )
#define L1D_SET_BPI_IMM_MODE_END() HW_WRITE( BPI_CON, PCTRL_MAIN )
#else
#define L1D_SET_BPI_IMM_MODE_BEGIN() HW_WRITE( BPI_CON, PCTRL_INITIAL )
#define L1D_SET_BPI_IMM_MODE_END() HW_WRITE( BPI_CON, PCTRL_MAIN )
#endif
/* ------------------------------------------------------------------------- */
#if IS_FPGA_TARGET || IS_CHIP_MT6208
/*FPGA,MT6208*/ #define AFC_EVENT_TRIGGER 0x0000 /* AFC 10 bit *//* AFC power up by DAC_AFC_ENABLEn events */
/*FPGA,MT6208*/ #define AFC_FORCE_POWER_ON 0x0001 /* AFC 10 bit *//* AFC always power on */
#endif
#if IS_CHIP_MT6205_AND_LATTER_VERSION || IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION
#if IS_FDD_DUAL_MODE_SUPPORT || IS_TDD_DUAL_MODE_SUPPORT
#if IS_EDGE_SAIC_CHIP_MT6270A_AND_LATTER_VERSION || IS_CHIP_MT6268H || IS_AST_B2S_SUPPORT
/*MT6205~*/ #define AFC_EVENT_TRIGGER 0x0000 /* AFC power up by DAC_AFC_ENABLEn events */
/*MT6205~*/ #define AFC_FORCE_POWER_ON 0x0001 /* AFC immediate mode */
#elif IS_CHIP_MT6268A || IS_CHIP_MT6268_S00 || IS_CHIP_MT6268T
/* chuwei: 0x0020 fixed MT6268A AFC Hold mode issue(Always on) */
/*MT6205~*/ #define AFC_EVENT_TRIGGER 0x0024 /* AFC power up by DAC_AFC_ENABLEn events */
/*MT6205~*/ #define AFC_FORCE_POWER_ON 0x0025 /* AFC immediate mode + always power on */
#else
//* chuwei: 0x0020 fixed MT6268A AFC Hold mode issue(Always on), 0x0040 Auto_SRCLKEN_OFF*/
/*MT6205~*/ #define AFC_EVENT_TRIGGER 0x0064 /* AFC power up by DAC_AFC_ENABLEn events */
/*MT6205~*/ #define AFC_FORCE_POWER_ON 0x0065 /* AFC immediate mode + always power on */
#endif
#else
/*MT6205~*/ #define AFC_EVENT_TRIGGER 0x0000 /* AFC power up by DAC_AFC_ENABLEn events */
/*MT6205~*/ #define AFC_FORCE_POWER_ON 0x0005 /* AFC immediate mooe + always power on */
#endif
#endif
/* ------------------------------------------------------------------------- */
#define PWRRES_BIT RSSI_RESOLUTION_BITS
#define PWRRES RSSI_FACTOR
/* ========================================================================= */
extern const int dsp_power_constance;
extern const short TQ_Afc_ChargeInIdle;
extern CONST short TQ_FBWin_Start_Offset;
extern const short TQ_FSWin_DTIRQ_Delay;
extern CONST short TxPropagationDelay;
extern const short FrequencyBias;
extern short AFC_Dac_TRx_Offset[5];
#if IS_VCXO_LC_TRXOFFSET_COMPENSATE_SUPPORT
extern short AFC_TRx_Offset[5];
extern short AFC_Default_TRx_Offset[5];
#else
#if IS_RF_MT6162
extern short AFC_TRx_Offset[5];
extern short AFC_Default_TRx_Offset[5];
#endif
#endif
#if IS_BBTXRX_CHIP_DESIGN_VER_2
extern const unsigned char bbrx_iq_swap;
extern const unsigned char bbtx_iq_swap;
extern const unsigned char bbtx_common_mode_voltage;
extern const unsigned char bbtx_offset_i;
extern const unsigned char bbtx_offset_q;
extern const unsigned char bbtx_phseli;
extern const unsigned char bbtx_phselq;
extern const unsigned char bbtx_rpsel;
extern const unsigned char bbtx_inten;
extern const unsigned char bbtx_sw_qbcnt;
extern const unsigned char bbtx_gain_comp;
extern const unsigned char bbtx_iqgain_sel;
extern const unsigned char bbtx_epsk_dtap_sym;
#else
extern const unsigned char bbrx_iq_swap;
extern const unsigned char bbrx_gain_double;
extern const unsigned char bbtx_iq_swap;
extern const unsigned char bbtx_calrcsel;
extern const unsigned char bbtx_calbias;
extern const unsigned char bbtx_common_mode_voltage;
extern const unsigned char bbtx_gain;
extern const unsigned char bbtx_trim_i;
extern const unsigned char bbtx_trim_q;
#if IS_CHIP_MT6225_AND_LATTER_VERSION || IS_SAIC_CHIP_MT6223_AND_LATTER_VERSION
extern const unsigned char bbtx_dccoarse_i;
extern const unsigned char bbtx_dccoarse_q;
#endif
extern const unsigned char bbtx_offset_i;
extern const unsigned char bbtx_offset_q;
extern const unsigned char bbtx_phsel;
#if IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION
extern const unsigned char bbtx_calrcsel_h;
extern const unsigned char bbtx_common_mode_voltage_h;
extern const unsigned char bbtx_gain_h;
extern const unsigned char bbtx_trim_i_h;
extern const unsigned char bbtx_trim_q_h;
#if IS_SAIC_CHIP_MT6223_AND_LATTER_VERSION
extern const unsigned char bbtx_dccoarse_i_h;
extern const unsigned char bbtx_dccoarse_q_h;
#endif
extern const unsigned char bbtx_offset_i_h;
extern const unsigned char bbtx_offset_q_h;
extern const unsigned char bbtx_phsel_h;
#if !IS_CHIP_MT6223 && !IS_CHIP_MT6253 /*MT6223 and MT6253 don't support 8PSK*/
extern const unsigned char bbtx_rpsel;
extern const unsigned char bbtx_inten;
extern const unsigned char bbtx_sw_qbcnt;
#endif
#endif
#endif
#if IS_CHIP_MT6227
extern const unsigned char bbtx_iqswap_onfly;
#endif
extern const unsigned short bdlcon_data;
extern const unsigned short bulcon1_data;
extern const unsigned short bulcon2_data;
#if IS_TDMA_AD_DA_WINDOW_SUPPORT
extern const unsigned short bdlcon2_data;
extern const unsigned short bulcon3_data;
#endif
extern CONST int apc_bat_voltage_period;
extern CONST int apc_bat_voltage_count;
extern CONST int apc_bat_temperature_period;
extern CONST int apc_bat_temperature_count;
extern CONST int apc_rf_temperature_period;
extern CONST int apc_rf_temperature_count;
/*---------------------------------------------------------------------------*/
extern const APBADDR PDATA_REG_TABLE[/*4:5*/];
#if IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION
extern const APBADDR PDATA_REG_TABLE2[/*4:5*/];
#endif
#if IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION
extern CONST signed short RX_END_TQ_TABLE[5];
#else
extern CONST signed short RX_END_TQ_TABLE[4];
#endif
extern CONST signed short TX_START_TQ_TABLE[8];
extern CONST signed short TX_END_TQ_TABLE[6];
extern CONST signed short PM_START_TQ_TABLE[7];
extern const signed short FWIN_POS_TABLE[8];
#if IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION
extern CONST signed short FSWIN_STOP_DATA_TABLE[9];
extern const APBADDR FSWIN_STOP_REG_TABLE[2][8];
#else
extern CONST signed short FSWIN_STOP_DATA_TABLE[7];
extern const APBADDR FSWIN_STOP_REG_TABLE[2][6];
#endif
#if IS_RF_MT6162
extern const unsigned long FSWIN_STOP_BSI_DATA_TABLE[2];
extern const APBADDR FSWIN_STOP_BSI_REG_TABLE[4];
#else
extern const unsigned long FSWIN_STOP_BSI_DATA_TABLE[1];
extern const APBADDR FSWIN_STOP_BSI_REG_TABLE[2];
#endif
extern const short FIR_COEF[/*20:17*/];
extern CONST signed short RX_MIDDLE_TQ_TABLE[3];
extern CONST signed short TX_MIDDLE_TQ_TABLE[4];
extern const unsigned char LOWEST_TX_POWER[5];
extern const signed long bb_tx_opt_swing_dac_sqr;
extern const unsigned char CONTISLOTMASK[5];
extern const unsigned char FIRSTSLOTMASK[5];
/*---------------------------------------------------------------------------*/
#if IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION
/*MT6229~*/extern CONST signed short PDATA_TABLE[5][2][5];
/*MT6229~*/extern CONST signed short PDATA_TABLE3[5][3][3];//for PR2M1, PR2M2, PT2M1, PT2M3
/*MT6229~*/extern const APBADDR PDATA_PT2M_REG_TABLE[4];
/*MT6229~*/extern const APBADDR PDATA_PR2M_REG_TABLE[4];
/*MT6229~*/
/*MT6229~*/extern CONST signed short RTX_START_TQ_TABLE[2];
#ifdef L1D_TEST
/*MT6229~*/extern signed short RX_START_TQ_TABLE[8];
#else
/*MT6229~*/extern CONST signed short RX_START_TQ_TABLE[8];
#endif
/*MT6229~*/
/*MT6229~*/extern CONST signed short PM_TQ_TABLE[10];
/*MT6229~*/
#if L1D_PM_ENHANCE
/*MT6229~*/extern CONST signed short PM_IN_IDLE_TQ_TABLE[10];
#if L1D_PM_1R7PM
/*MT6229~*/extern CONST signed short PM_1R7PM_TQ_TABLE[10];
#endif
#endif
/*MT6229~*/
/*MT6229~*/extern const short NB_FIR_COEF[];
/*MT6229~*/extern const short NARROW_FB_FIR_COEF[];
/*MT6229~*/extern const short WIDE_FB_FIR_COEF[];
/*MT6229~*/extern const short NB_FIR_COEF_WIDER[];
/*MT6229~*/
#ifdef L1D_TEST
/*MT6229~*/extern const short VCXO_NARROW_FB_FIR_COEF[];
/*MT6229~*/extern const short VCXO_WIDE_FB_FIR_COEF[];
/*MT6229~*/extern const short TCVCXO_NARROW_FB_FIR_COEF[];
/*MT6229~*/extern const short TCVCXO_WIDE_FB_FIR_COEF[];
#endif
/*MT6229~*/
/*MT6229~*/extern CONST signed short RX_MIDDLE_TQ_TABLE2[2];
/*MT6229~*/extern CONST signed short TX_START_TQ_TABLE2[1];
/*MT6229~*/extern CONST signed short TX_START_TQ_TABLE3[1];//for TQ_ST2B
/*MT6229~*/
/*MT6229~*/extern CONST signed short TX_MIDDLE_TQ_TABLE2[2][4];
/*MT6229~*/
#else /*!IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION*/
/*MT6218~*/extern const signed short PDATA_TABLE[/*5*/][2][3];
/*MT6218~*/
#if IS_CHIP_MT6225_AND_LATTER_VERSION
#ifdef L1D_TEST
/*MT6218~*/extern signed short RX_START_TQ_TABLE[7];
#else
/*MT6218~*/extern const signed short RX_START_TQ_TABLE[7];
#endif
#else
/*MT6218~*/extern const signed short RX_START_TQ_TABLE[7];
#endif /*End of "IS_CHIP_MT6225_AND_LATTER_VERSION"*/
/*MT6218~*/
/*MT6218~*/extern const signed short PM_TQ_TABLE[8];
/*MT6218~*/
#if L1D_PM_ENHANCE
/*MT6218~*/extern const signed short PM_IN_IDLE_TQ_TABLE[8];
#if L1D_PM_1R7PM
/*MT6218~*/extern const signed short PM_1R7PM_TQ_TABLE[8];
#endif
#endif
/*MT6218~*/
#if IS_CHIP_MT6218_AND_LATTER_VERSION
/*MT6218~*//*MT6218~*/ extern const signed short PDATA_TABLE2[5][2][2];
/*MT6218~*//*MT6218~*/ extern const APBADDR PDATA_PT2B_REG_TABLE[2][3];
/*MT6218~*//*MT6218~*/ extern const APBADDR PDATA_PR2M_REG_TABLE[4];
/*MT6218~*//*MT6218~*/ extern const signed short RX_MIDDLE_TQ_TABLE2[2];
/*MT6218~*//*MT6218~*/ extern const signed short TX_START_TQ_TABLE2[1];
#endif
/*MT6218~*/
#if IS_CHIP_MT6225_AND_LATTER_VERSION
/*MT6218~*//*MT6225*/ extern const short NB_FIR_COEF[];
/*MT6218~*//*MT6225*/ extern const short NB_FIR_COEF_WIDER[];
#endif
/*MT6218~*/
#endif /* End of "IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION" */
/*---------------------------------------------------------------------------*/
#if !IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION
extern const unsigned char USE_3_SUBSTAGES_FB_STAGE1;
#endif
/*---------------------------------------------------------------------------*/
#if IS_RF_MT6140D
extern CONST unsigned long TXCW[/*2*/][2][5];
#endif
/*---------------------------------------------------------------------------*/
#if IS_MPLL_FH_SUPPORT || IS_MT6276E1_TEMP_MPLL_FH_SUPPORT || IS_MT6276_FREERUN_SUPPORT
extern unsigned char MPLL_FLT;
#endif
#if IS_SPLL_FH_SUPPORT
extern unsigned char SPLL_FLT;
#endif
/*---------------------------------------------------------------------------*/
#if IS_32K_CRYSTAL_REMOVAL_SUPPORT
extern char l1d_ext_32k_exist;
#endif
/*---------------------------------------------------------------------------*/
#define TQ_PM0_BEGIN_HF (TQ_AFC_READY+TQ_SLOT_LEN-TQ_SHORT_PMWIN_LEN_IN_IDLE)
#if L1D_PM_ENHANCE
#define TQ_PM1_BEGIN_HF (TQ_SLOT1_BEGIN+TQ_AFC_READY+8)
#define TQ_PM2_BEGIN_HF (TQ_PM1_BEGIN_HF+TQ_SHORT_PMWIN_LEN_IN_IDLE+TQ_AFC_READY+8)
#define TQ_PM3_BEGIN_HF (TQ_PM2_BEGIN_HF+TQ_SHORT_PMWIN_LEN_IN_IDLE+TQ_AFC_READY+8)
#define TQ_VALIDATE_COUNT_HF (TQ_PM3_BEGIN_HF+TQ_SHORT_PMWIN_LEN_IN_IDLE+8)
#define TQ_CTIRQ2_HF (TQ_PM1_BEGIN_HF+TQ_SHORT_PMWIN_LEN_IN_IDLE+100)
#define TQ_PM_REGBIAS_OFF_HF (((TQ_SHORT_PMWIN_LEN_IN_IDLE+TQ_AFC_READY+8)*4)+8)
#if IS_FHC_SUPPORT
#define TQ_PM_REGBIAS_OFF_FHC TQ_SLOT4_BEGIN//(TQ_SLOT4_BEGIN + TQ_AFC_READY)
#endif
#define TQ_PM2_END_2ND_HF (TQ_PM_REGBIAS_OFF_HF+TQ_PM2_BEGIN_HF+TQ_SHORT_PMWIN_LEN_IN_IDLE+20)
#if IS_NEW_L1D_ARCH_8R_SUPPORT
#define CTIRQ1_READ_SLOTS_IN_2ND_HF (1)//Read PM2 of 2nd HF in CTIRQ1
#define IS_CHECK_8PM_DSPPROC 0
#elif (TQ_PM2_END_2ND_HF < TQ_CTIRQ1)
#define CTIRQ1_READ_SLOTS_IN_2ND_HF (3)//Read PM2 of 2nd HF in CTIRQ1
#define IS_CHECK_8PM_DSPPROC 0
#else
#define CTIRQ1_READ_SLOTS_IN_2ND_HF (2)//Read PM2 of 2nd HF in the following CTIRQ1/CTIRQ2H
#define IS_CHECK_8PM_DSPPROC 1
#endif
#if IS_NEW_L1D_ARCH_8R_SUPPORT
#define CTIRQ1_READ_SLOTS (3)
#define CTIRQ2_READ_SLOTS_IN_1ST_HF (0)
#define CTIRQ1_READ_SLOTS_IN_2ND_HF_1R7PM (1)
#elif IS_NEW_L1D_ARCH_6R_SUPPORT
#define CTIRQ1_READ_SLOTS (4)
#define CTIRQ2_READ_SLOTS_IN_1ST_HF (2)
#define CTIRQ1_READ_SLOTS_IN_2ND_HF_1R7PM (9)
#else
#define CTIRQ1_READ_SLOTS (6)
#define CTIRQ2_READ_SLOTS_IN_1ST_HF (2)
#define CTIRQ1_READ_SLOTS_IN_2ND_HF_1R7PM (9)
#endif
extern const signed short SHORT_PM_START_TQ_TABLE[4];
#if IS_FDD_DUAL_MODE_SUPPORT || IS_TDD_DUAL_MODE_SUPPORT
extern const signed short SHORT_PM_END_POINT_TABLE[8];
#endif
#define TQ_CTIRQ1_HF_MIN (TQ_SLOT5_BEGIN+400) //3781
#if IS_NEW_L1D_ARCH_8R_SUPPORT
#define TQ_CTIRQ1_HF (TQ_CTIRQ1)
#elif ( TQ_CTIRQ1_HF_MIN < TQ_CTIRQ1 )
#define TQ_CTIRQ1_HF (TQ_CTIRQ1)
#else
#define TQ_CTIRQ1_HF (TQ_CTIRQ1_HF_MIN)
#endif
#if L1D_PM_1R7PM
#define TQ_PM0_BEGIN_1R7PM (TQ_SLOT1_BEGIN-TQ_1R7PM_PMWIN_LEN_IN_IDLE) // 753 (NULL)
#define TQ_PM1_BEGIN_1R7PM (TQ_SLOT1_BEGIN+TQ_AFC_READY+8) //1145
#define TQ_PM2_BEGIN_1R7PM (TQ_PM1_BEGIN_1R7PM+TQ_1R7PM_PMWIN_LEN_IN_IDLE+TQ_AFC_READY+8) //1537
#define TQ_PM3_BEGIN_1R7PM (TQ_PM2_BEGIN_1R7PM+TQ_1R7PM_PMWIN_LEN_IN_IDLE+TQ_AFC_READY+8) //1929
#define TQ_PM4_BEGIN_1R7PM (TQ_PM3_BEGIN_1R7PM+TQ_1R7PM_PMWIN_LEN_IN_IDLE+TQ_AFC_READY+8) //2321
/*
#define TQ_PM5_BEGIN_1R7PM ((TQ_PM4_BEGIN_1R7PM+TQ_1R7PM_PMWIN_LEN_IN_IDLE+TQ_AFC_READY+8)+8)//2721
#define TQ_PM6_BEGIN_1R7PM (TQ_PM5_BEGIN_1R7PM+TQ_1R7PM_PMWIN_LEN_IN_IDLE+TQ_AFC_READY+8) //3113
#define TQ_PM7_BEGIN_1R7PM (TQ_CTIRQ1-100-TQ_1R7PM_PMWIN_LEN_IN_IDLE) //3553
*/
#define TQ_VALIDATE_COUNT_1R7PM (TQ_PM4_BEGIN_1R7PM+TQ_1R7PM_PMWIN_LEN_IN_IDLE+8) //2457
#define TQ_CTIRQ2_1R7PM (TQ_PM1_BEGIN_1R7PM+TQ_1R7PM_PMWIN_LEN_IN_IDLE+250) //1523
#define TQ_PM_REGBIAS_OFF_1R7PM (((TQ_1R7PM_PMWIN_LEN_IN_IDLE+TQ_AFC_READY+8)*5)+8) //1968
extern const signed short PM_1R7PM_START_TQ_TABLE[6];
#endif
#if IS_FDD_DUAL_MODE_SUPPORT || IS_TDD_DUAL_MODE_SUPPORT
/*DM*/ #define TQ_CTIRQ2_FOR_PM_BEFORE_FB (TQ_SLOT0_BEGIN+TQ_SHORT_PMWIN_LEN+100)
/*DM*/ #define TQ_VALIDATE_COUNT_FOR_PM_BEFORE_FB (TQ_CTIRQ2_FOR_PM_BEFORE_FB+300)
/*DM*/ #define TQ_DTIRQ_FOR_PM_BEFORE_FB (TQ_VALIDATE_COUNT_FOR_PM_BEFORE_FB+30)
#endif
#if IS_NEW_L1D_ARCH_8R_SUPPORT
#undef TQ_CTIRQ2_HF
#undef TQ_CTIRQ2_1R7PM
#define TQ_CTIRQ2_HF TQ_CTIRQ2
#define TQ_CTIRQ2_1R7PM TQ_CTIRQ2
#endif
#endif
/*---------------------------------------------------------------------------*/
/* Power offset of WB/NB RX filter depens on WB/NB filter coefficients */
/* From MT6223~, the WB/NB power offset is not a constant, and the 64-symbol NB power is reported when WB is selected */
#if IS_CHIP_MT6223
#define WBNB_RX_FILTER_POWER_OFFSET 0 /* 0.75 *64 */
#elif IS_CHIP_MT6229 || IS_CHIP_MT6268T
#define WBNB_RX_FILTER_POWER_OFFSET 88 /* 1.375*64 */
#elif IS_CHIP_MT6225_AND_LATTER_VERSION
#define WBNB_RX_FILTER_POWER_OFFSET 80 /* 1.25 *64 */
#endif
/*---------------------------------------------------------------------------*/
#if IS_FHC_SUPPORT
#define FHC_PROC_NONE 0x00
#define FHC_PROC_DTS_AFC_WB 0x01
#define FHC_PROC_DTS_AFC_NB_SYNC 0x02
#define FHC_PROC_DTS_START 0x04
#define FHC_PROC_DTS_PL 0x10
#define FHC_PROC_UTS_PCL 0x20
#define FHC_PROC_UTS_DAC 0x40
#if IS_32K_CRYSTAL_REMOVAL_SUPPORT
#define FHC_PROC_DTS_DCXO_LPM 0x80
#endif
/*
#if IS_GPRS
#define FHC_PM_SLOT_FOR_PL 6
#endif
#if IS_GSM
#define FHC_PM_SLOT_FOR_PL 4
#endif
*/
#define FHC_PM_SLOT_FOR_PL 4
#define FHC_SB_FAIL_THRESHOLD 255
#define FHC_PM_SLOT_FOR_FCCH 4
#if IS_DSP_ARCHITECTURE_V4_SUPPORT
#define FHC_SB_SNR_THRESHOLD 10
#else
#define FHC_SB_SNR_THRESHOLD (-1)
#endif
#endif
/*---------------------------------------------------------------------------*/
#if IS_DLIF_CHIP
#define NB_FIR_4DC_NORMAL_IFSEL0 0x7F7F //( -1, -1)
#if (IS_CHIP_MT6256_S00 || IS_CHIP_MT6251_S00) && defined(L1D_TEST)
#define WB_FIR_4DC_NORMAL_IFSEL0 0x7C7C //( -4, -4)
#else
#define WB_FIR_4DC_NORMAL_IFSEL0 0x7F7F //( -1, -1)
#endif
/*
#define NB_FIR_4DC_NORMAL_IFSEL1 0x7F01 //( -1, 1), no-use, HW do complex-conjugate by itself
#define WB_FIR_4DC_NORMAL_IFSEL1 0x7C04 //( -4, 4), no-use, HW do complex-conjugate by itself
*/
#if IS_CHIP_MT6256_S00 || IS_CHIP_MT6251
#define NB_FIR_4DC_FB_POWRON_IFSEL0 0x6A16 //(-22, 22)
#define WB_FIR_4DC_FB_POWRON_IFSEL0 0x2929 //( 41, 41)
#define NB_FIR_4DC_FB_POWRON_IFSEL1 0x1212 //( 18, 18)
#define WB_FIR_4DC_FB_POWRON_IFSEL1 0x2957 //( 41,-41)
#endif
#if IS_CHIP_MT6256_S00
#elif IS_CHIP_MT6256 || IS_CHIP_MT6255 || IS_CHIP_MT6250 || IS_CHIP_MT6260 || IS_CHIP_MT6261
#if defined(L1D_TEST)
#if IS_BFE_RX_TYPE_NB_EN_SUPPORT
#define DCOC_QB_RX_FENA_2_FSYNC 32
// for RX_TIME_CON0
#define RX_DCOC_STR_NB (DCOC_QB_RX_FENA_2_FSYNC-26) //26: filter CIC1 group delay
#define RX_NULL_STR_NB (RX_DCOC_STR_NB-4) // 4: for cosim
// for RX_TIME_CON1
#define RX_IRCMPN_SW (DCOC_QB_RX_FENA_2_FSYNC-20) //20: filter FIR3 group delay
// for RX_TIME_CON2
#define RX_DCOC_STR (DCOC_QB_RX_FENA_2_FSYNC-30) //30: filter CIC1 group delay
#define RX_NULL_STR (RX_DCOC_STR-0) // 0: for cosim
#else
#define DCOC_QB_RX_FENA_2_FSYNC 32
// for RX_TIME_CON0
#define RX_DCOC_STR (DCOC_QB_RX_FENA_2_FSYNC-26) //26: filter CIC1 group delay
#define RX_NULL_STR (RX_DCOC_STR-4) // 4: for cosim
// for RX_TIME_CON1
#define RX_IRCMPN_SW (DCOC_QB_RX_FENA_2_FSYNC-20) //20: filter FIR3 group delay
#endif
#elif IS_BFE_RX_TYPE_NB_EN_SUPPORT
#define DCOC_QB_RX_FENA_2_FSYNC 48
// for RX_TIME_CON0
#define RX_DCOC_STR_NB (DCOC_QB_RX_FENA_2_FSYNC-26) //26: filter CIC1 group delay
#define RX_NULL_STR_NB (RX_DCOC_STR_NB-15) //15: max value for current data does NOT overlap the previous slot
// for RX_TIME_CON1
#define RX_IRCMPN_SW (DCOC_QB_RX_FENA_2_FSYNC-20) //20: filter FIR3 group delay
// for RX_TIME_CON2
#define RX_DCOC_STR (DCOC_QB_RX_FENA_2_FSYNC-38) //38: filter CIC1 group delay
#define RX_NULL_STR (RX_DCOC_STR-10) //10: max value for current data does NOT overlap the previous slot
#elif IS_RX_DCOC_ADVANCED_SUPPORT
#define DCOC_QB_RX_FENA_2_FSYNC 48
// for RX_TIME_CON0
#define RX_DCOC_STR (DCOC_QB_RX_FENA_2_FSYNC-38) //38: filter CIC1 group delay
#define RX_NULL_STR (RX_DCOC_STR-10) //10: max value for current data does NOT overlap the previous slot
// for RX_TIME_CON1
#define RX_IRCMPN_SW (DCOC_QB_RX_FENA_2_FSYNC-20) //20: filter FIR3 group delay
#else
#define DCOC_QB_RX_FENA_2_FSYNC 48
// for RX_TIME_CON0
#define RX_DCOC_STR (DCOC_QB_RX_FENA_2_FSYNC-26) //26: filter CIC1 group delay
#define RX_NULL_STR (RX_DCOC_STR-15) //15: max value for current data does NOT overlap the previous slot
// for RX_TIME_CON1
#define RX_IRCMPN_SW (DCOC_QB_RX_FENA_2_FSYNC-20) //20: filter FIR3 group delay
#endif
#endif
/*...........................................................................*/
#if (IS_CHIP_MT6256_S00 || IS_CHIP_MT6251_S00) && defined(L1D_TEST)
#define THR_ITD_DEFAULT 0x96 //150
#else
#define THR_ITD_DEFAULT 0xA0 //160
#endif
#if defined(L1D_TEST)
#define TX_CNT_TGT_DEFAULT 158
#else
#define TX_CNT_TGT_DEFAULT 36 //140
#endif
#define PM_DLY_DEFAULT 0
#define P2X_SCALE_DEFAULT 0x3A //58
#if IS_CHIP_MT6256_S00 || IS_CHIP_MT6251
#define TX_CNT_TGT_SW_DEFAULT 0
#else
#define TX_CNT_TGT_SW_DEFAULT TX_CNT_TGT_DEFAULT //For normal mode, TX_CNT_TGT_SW_DEFAULT should be equal to TX_CNT_TGT_DEFAULT
#endif //For loopback mode, we set TX_CNT_TGT_SW_DEFAULT=146 in L1DTest_Init2()
#define TX_CON0_DEFAULT 0
#define TX_CON1_DEFAULT ( ((PM_DLY_DEFAULT&0xF)<<8)|TX_CNT_TGT_DEFAULT )
#if IS_CHIP_MT6256_S00 || IS_CHIP_MT6251
#define RX_CON3_DEFAULT ( THR_ITD_DEFAULT<<8 )
#define TX_PWR_DEFAULT ( (TX_CNT_TGT_SW_DEFAULT&0xFF)<<8 )
#else
#define TX_CON2_DEFAULT ( (TX_CNT_TGT_SW_DEFAULT&0xFF)<<8 )
#endif
#endif
/*---------------------------------------------------------------------------*/
#if IS_TX_POWER_CONTROL_SUPPORT
#if IS_TXPC_CL_AUXADC_SUPPORT
extern short scan_qb;
extern CONST short TQ_TxSampleOffsetGMSK;
#if IS_EPSK_TX_SUPPORT
extern CONST short TQ_TxSampleOffsetEPSK;
#endif
#endif
#if IS_TXPC_OL_BSI_SUPPORT || IS_TXPC_OL_AUXADC_SUPPORT
extern CONST short txpc_epsk_tp_slope_lb;
extern CONST short txpc_epsk_tp_slope_hb;
#endif
extern const char temp_adc_cal_type;
#endif
/*---------------------------------------------------------------------------*/
/* RX LNA calbiration */
#if IS_MULTI_LNA_MODE_CALIBRATION_SUPPORT
extern const char is_lna_calibration;
#endif
/*---------------------------------------------------------------------------*/
#if IS_DYNAMIC_G_E_TXWIN_POSITION_SUPPORT || IS_DYNAMIC_G_E_TXWIN_POSITION_SUPPORT_V2
extern CONST signed short TQ_EPSK_TX_delay;
#endif
/*---------------------------------------------------------------------------*/
#if IS_RF_TOOL_CUSTOMIZATION_SUPPORT
#define RFDEF (signed short)0xABCD
#define URFDEF (unsigned short)0xABCD
typedef struct
{
int start; // the special pattern of start position
int version; // Struct Version ID
int RF_Type; // RF type
char is_data_update; // default is false, and will be changed as true after tool update
signed short xPDATA_TABLE[5][2][5];
signed short xPDATA_TABLE3[5][3][3];
signed short xRX_START_TQ_TABLE[8];
signed short xRX_END_TQ_TABLE[5];
signed short xRX_MIDDLE_TQ_TABLE[3];
signed short xRX_MIDDLE_TQ_TABLE2[2];
signed short xTX_START_TQ_TABLE[8];
signed short xTX_START_TQ_TABLE2[1];
signed short xTX_START_TQ_TABLE3[1];
signed short xTX_END_TQ_TABLE[6];
signed short xTX_MIDDLE_TQ_TABLE[4];
signed short xTX_MIDDLE_TQ_TABLE2[2][4];
signed short xPM_START_TQ_TABLE[7];
signed short xPM_TQ_TABLE[10];
signed short xPM_IN_IDLE_TQ_TABLE[10];
signed short xPM_1R7PM_TQ_TABLE[10];
signed short xFSWIN_STOP_DATA_TABLE[9];
unsigned short xtxios_pcl_tab[2][2][5];
unsigned short xtxitc_pcl_tab[2][2][5];
unsigned short xtxmod_gc_tab[2][2][5];
long XO_CapID; // L1 Rf data
int end1; // the special pattern of end1 position
signed short xPDATA_GMSK;
signed short xPDATA_8PSK;
signed short xGSM850_GSM900_SWAP;
signed short xDCS1800_PCS1900_SWAP;
int xBAT_VOLTAGE_SAMPLE_PERIOD;
int xBAT_VOLTAGE_AVERAGE_COUNT;
int xBAT_TEMPERATURE_SAMPLE_PERIOD;
int xBAT_TEMPERATURE_AVERAGE_COUNT;
int xBAT_LOW_VOLTAGE;
int xBAT_HIGH_VOLTAGE;
int xBAT_LOW_TEMPERATURE;
int xBAT_HIGH_TEMPERATURE;
int end2; // the special pattern of end2 position
} sRF_TABLE;
extern sRF_TABLE l1_rf_table;
#endif
/*-------------------------------------------------------------------------------------------------------------------*/
/*----------------------------------------------- TDD Dual Mode Begin -----------------------------------------------*/
/*-------------------------------------------------------------------------------------------------------------------*/
#if IS_TDD_DUAL_MODE_SUPPORT
/*TDD*/ #define TQ_CTIRQ2_HF2_TD_DM TQ_VALIDATE-100 // 4839
/* The tming margin left for DSP PM decoded is not enough. 5000us-675us*2 = 3954QB.
If 2 PM (at max 2PM created in a TD slot gap) created 3954+2*(256+128+8)= 4738QB.
4738QB+100QB = 4838QB ~= 4939-100 to read PM */
/*TDD*/ extern const signed short TD_DM_PM_BEGIN_POINT_TABLE[8];
/*TDD*/ extern const signed short TD_DM_PM_END_POINT_TABLE[8];
/*TDD*/ extern CONST signed short TD_DM_PM_TQ_TABLE[11];
#if IS_DSP_ENHANCE_SHORT_FBSB_SUPPORT
/*TDD*/ #define FB_ENHANCE_TQ_LEN_TABLE_SIZE 4
/*TDD*/ extern CONST signed short FB_ENHANCE_TQ_LEN_TABLE[FB_ENHANCE_TQ_LEN_TABLE_SIZE];
/*TDD*/ extern CONST signed short FB_BURST_SCALOR_TABLE[FB_ENHANCE_TQ_LEN_TABLE_SIZE];
#if IS_DSP_SHORT_FBSB_V2
/*TDD*/ extern CONST signed short FB_BURST_RESOLUTION_TABLE[FB_ENHANCE_TQ_LEN_TABLE_SIZE];
#endif
/*TDD*/ #define SB_EXTEND_TQ_LEN_TABLE_SIZE 3
/*TDD*/ extern CONST signed short SB_EXTEND_TQ_LEN_TABLE[SB_EXTEND_TQ_LEN_TABLE_SIZE];
/*TDD*/ extern CONST signed short SB_BURST_SCALOR_TABLE[SB_EXTEND_TQ_LEN_TABLE_SIZE];
#if IS_DSP_SHORT_FBSB_V2
/*TDD*/ extern CONST signed short SB_BURST_RESOLUTION_TABLE[SB_EXTEND_TQ_LEN_TABLE_SIZE];
#endif
#endif
#endif
/*-------------------------------------------------------------------------------------------------------------------*/
/*----------------------------------------------- TDD Dual Mode End -------------------------------------------------*/
/*-------------------------------------------------------------------------------------------------------------------*/
#endif /*End of "#ifndef _L1D_DATA_H_" */