t30_trc_gen.h
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#ifndef _T30_TRC_GEN_H_
#define _T30_TRC_GEN_H_
// FUNC_t30_csm_activate_req_hdlr
#define FUNC_t30_csm_activate_req_hdlr_size "d"
#define FUNC_t30_csm_activate_req_hdlr FUNC_t30_csm_activate_req_hdlr__enum,FUNC_t30_csm_activate_req_hdlr_size
// FUNC_t30_csm_deactivate_req_hdlr
#define FUNC_t30_csm_deactivate_req_hdlr_size "d"
#define FUNC_t30_csm_deactivate_req_hdlr FUNC_t30_csm_deactivate_req_hdlr__enum,FUNC_t30_csm_deactivate_req_hdlr_size
// FUNC_t30_process_cmd_ind
#define FUNC_t30_process_cmd_ind_size "d"
#define FUNC_t30_process_cmd_ind FUNC_t30_process_cmd_ind__enum,FUNC_t30_process_cmd_ind_size
// FUNC_t30_send_ul_cmd
#define FUNC_t30_send_ul_cmd_size "d"
#define FUNC_t30_send_ul_cmd FUNC_t30_send_ul_cmd__enum,FUNC_t30_send_ul_cmd_size
// T30_STATE
#define T30_STATE_size "d"
#define T30_STATE T30_STATE__enum,T30_STATE_size
// T30_TIMER_EXPIRY_INDEX
#define T30_TIMER_EXPIRY_INDEX_size "dh"
#define T30_TIMER_EXPIRY_INDEX T30_TIMER_EXPIRY_INDEX__enum,T30_TIMER_EXPIRY_INDEX_size
// T30_START_TIMER_INDEX
#define T30_START_TIMER_INDEX_size "dh"
#define T30_START_TIMER_INDEX T30_START_TIMER_INDEX__enum,T30_START_TIMER_INDEX_size
// T30_STOP_TIMER_INDEX
#define T30_STOP_TIMER_INDEX_size "dh"
#define T30_STOP_TIMER_INDEX T30_STOP_TIMER_INDEX__enum,T30_STOP_TIMER_INDEX_size
// T30_FLAG_STATUS
#define T30_FLAG_STATUS_size "‚h"
#define T30_FLAG_STATUS T30_FLAG_STATUS__enum,T30_FLAG_STATUS_size
// T30_RX_HDLC_FCS_ERROR
#define T30_RX_HDLC_FCS_ERROR_size NULL
#define T30_RX_HDLC_FCS_ERROR T30_RX_HDLC_FCS_ERROR__enum,T30_RX_HDLC_FCS_ERROR_size
// T30_RX_HDLC_CMD_ERROR
#define T30_RX_HDLC_CMD_ERROR_size "h"
#define T30_RX_HDLC_CMD_ERROR T30_RX_HDLC_CMD_ERROR__enum,T30_RX_HDLC_CMD_ERROR_size
// T30_DETECT_UART_BREAK
#define T30_DETECT_UART_BREAK_size NULL
#define T30_DETECT_UART_BREAK T30_DETECT_UART_BREAK__enum,T30_DETECT_UART_BREAK_size
// T31_UART_WRITE_BCS_FAIL
#define T31_UART_WRITE_BCS_FAIL_size NULL
#define T31_UART_WRITE_BCS_FAIL T31_UART_WRITE_BCS_FAIL__enum,T31_UART_WRITE_BCS_FAIL_size
// T31_TXBCS_TX_BUFF_OVERFLOW
#define T31_TXBCS_TX_BUFF_OVERFLOW_size NULL
#define T31_TXBCS_TX_BUFF_OVERFLOW T31_TXBCS_TX_BUFF_OVERFLOW__enum,T31_TXBCS_TX_BUFF_OVERFLOW_size
// T30_DL_QUEUE_FULL
#define T30_DL_QUEUE_FULL_size NULL
#define T30_DL_QUEUE_FULL T30_DL_QUEUE_FULL__enum,T30_DL_QUEUE_FULL_size
// T30_TXMSG_UART_EMPTY
#define T30_TXMSG_UART_EMPTY_size NULL
#define T30_TXMSG_UART_EMPTY T30_TXMSG_UART_EMPTY__enum,T30_TXMSG_UART_EMPTY_size
// T31_TXBCS_UART_EMPTY
#define T31_TXBCS_UART_EMPTY_size NULL
#define T31_TXBCS_UART_EMPTY T31_TXBCS_UART_EMPTY__enum,T31_TXBCS_UART_EMPTY_size
// T30_UART_WRITE_FAIL
#define T30_UART_WRITE_FAIL_size NULL
#define T30_UART_WRITE_FAIL T30_UART_WRITE_FAIL__enum,T30_UART_WRITE_FAIL_size
// T30_TX_BUFF_INFO
#define T30_TX_BUFF_INFO_size "‚h"
#define T30_TX_BUFF_INFO T30_TX_BUFF_INFO__enum,T30_TX_BUFF_INFO_size
// T30_RX_BUFF_INFO
#define T30_RX_BUFF_INFO_size "‚h"
#define T30_RX_BUFF_INFO T30_RX_BUFF_INFO__enum,T30_RX_BUFF_INFO_size
// T30_RX_UART_BUFF_INFO
#define T30_RX_UART_BUFF_INFO_size "‚h"
#define T30_RX_UART_BUFF_INFO T30_RX_UART_BUFF_INFO__enum,T30_RX_UART_BUFF_INFO_size
#endif // T30_TRC_GEN.H