cpll.h
12.1 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
/*******************************************************************************
* Copyright Statement:
* --------------------
* This software is protected by Copyright and the information contained
* herein is confidential. The software may not be copied and the information
* contained herein may not be used or disclosed except with the written
* permission of MediaTek Inc. (C) 2005
*
* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
*
* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
*
* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
*
*******************************************************************************/
/*******************************************************************************
* Filename:
* ---------
* cpll.h
*
* Project:
* --------
* MT6238
*
* Description:
* ------------
* This file is intends for ISP HW.
*
* Author:
* -------
* -------
*
*============================================================================
* HISTORY
* Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
*------------------------------------------------------------------------------
* removed!
*
* removed!
* removed!
* removed!
*
* removed!
* removed!
* removed!
*
* removed!
* removed!
* removed!
*
* removed!
* removed!
* removed!
*
* removed!
* removed!
* removed!
*
* removed!
* removed!
* removed!
*
* removed!
* removed!
* removed!
*
* removed!
* removed!
* removed!
*
* removed!
* removed!
* removed!
*
* removed!
* removed!
* removed!
*
* removed!
* removed!
* removed!
*
* removed!
* removed!
* removed!
*
* removed!
* removed!
* removed!
*
* removed!
* removed!
* removed!
*
* removed!
* removed!
* removed!
*
* removed!
* removed!
* removed!
*
* removed!
* removed!
* removed!
*
* removed!
* removed!
* removed!
*
*
*------------------------------------------------------------------------------
* Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
*============================================================================
****************************************************************************/
#ifndef _CPLL_H_
#define _CPLL_H_
#include "drv_features.h"
#include "reg_base.h"
#if(defined(DRV_ISP_MT6238_HW_SUPPORT))
#define CPLL_BASE PLL_base
//0x83000000
#define REG_CPLL_CTRL_REGISTER1 *((volatile unsigned int *) (CPLL_BASE + 0x0008))
#define REG_CPLL_CTRL_REGISTER2 *((volatile unsigned int *) (CPLL_BASE + 0x000C))
#define REG_CPLL_DIGDIV_MASK 0x0000F000
#define REG_CPLL_RST_BIT 0x00000800
#define REG_CPLL_DIVCTRL_MASK 0x000007E0
#define REG_CPLL_CALI_MASK 0x0000001F
#define REG_CPLL_PDN_BIT 0x00000001
#define SET_CPLL_DIGITAL_DIVIDER(n) REG_CPLL_CTRL_REGISTER1 &= ~REG_CPLL_DIGDIV_MASK; \
REG_CPLL_CTRL_REGISTER1 |= ((n)<<12);
#define SET_CPLL_RST REG_CPLL_CTRL_REGISTER1 |= REG_CPLL_RST_BIT;
#define CLEAR_CPLL_RST REG_CPLL_CTRL_REGISTER1 &= ~REG_CPLL_RST_BIT;
#define SET_CPLL_DIVCTRL(n) REG_CPLL_CTRL_REGISTER1 &= ~REG_CPLL_DIVCTRL_MASK; \
REG_CPLL_CTRL_REGISTER1 |= ((n)<<5);
#define SET_CPLL_CALI(n) REG_CPLL_CTRL_REGISTER1 &= ~REG_CPLL_CALI_MASK; \
REG_CPLL_CTRL_REGISTER1 |= (n);
#define SET_CPLL_PWR_ON REG_CPLL_CTRL_REGISTER2 &= ~REG_CPLL_PDN_BIT;
#define SET_CPLL_PWR_DOWN REG_CPLL_CTRL_REGISTER2 |= REG_CPLL_PDN_BIT;
#elif(defined(DRV_ISP_MT6268_HW_SUPPORT))
#define CPLL_BASE MIXED_base
//0x840C0000
#define REG_CPLL_CTRL_REGISTER1 *((volatile unsigned int *) (CPLL_BASE + 0x0038))
#define REG_CPLL_CTRL_REGISTER2 *((volatile unsigned int *) (CPLL_BASE + 0x003C))
#define REG_CPLL_CTRL_REGISTER3 *((volatile unsigned int *) (CPLL_BASE + 0x0048))
/*cpll register1*/
#define REG_CPLL_RST_BIT 0x00000800
#define REG_CPLL_FBDIV_MASK 0x000007E0
#define REG_CPLL_CM_MASK 0x0000001F
/*cpll register2*/
#define REG_CPLL_PDN_BIT 0x00000001
/*cpll register3*/
#define REG_CPLL_DIGDIV_MASK 0x0000000F
#define SET_CPLL_RST REG_CPLL_CTRL_REGISTER1 |= REG_CPLL_RST_BIT;
#define CLEAR_CPLL_RST REG_CPLL_CTRL_REGISTER1 &= ~REG_CPLL_RST_BIT;
#define SET_CPLL_DIVCTRL(n) REG_CPLL_CTRL_REGISTER1 &= ~REG_CPLL_FBDIV_MASK; \
REG_CPLL_CTRL_REGISTER1 |= ((n)<<5);
#define SET_CPLL_CALI(n) REG_CPLL_CTRL_REGISTER1 &= ~REG_CPLL_CM_MASK; \
REG_CPLL_CTRL_REGISTER1 |= (n);
#define SET_CPLL_PWR_ON REG_CPLL_CTRL_REGISTER2 |= REG_CPLL_PDN_BIT;
#define SET_CPLL_PWR_DOWN REG_CPLL_CTRL_REGISTER2 &= ~REG_CPLL_PDN_BIT;
#define SET_CPLL_DIGITAL_DIVIDER(n) REG_CPLL_CTRL_REGISTER3 &= ~REG_CPLL_DIGDIV_MASK; \
REG_CPLL_CTRL_REGISTER3 |= (n);
#elif(defined(DRV_ISP_MT6236_HW_SUPPORT))
#define CPLL_BASE PLL_SD_base
//0x801A0000
#define REG_CPLL_CTRL_REGISTER1 *((volatile unsigned int *) (CPLL_BASE + 0x0600))
#define REG_CPLL_CTRL_REGISTER2 *((volatile unsigned int *) (CPLL_BASE + 0x0604))
#define REG_CPLL_CTRL_REGISTER3 *((volatile unsigned int *) (CPLL_BASE + 0x0608))
/*cpll register1*/
#define REG_CPLL_CM_MASK 0x000000F0
/*cpll register2*/
#define REG_CPLL_RST_BIT 0x00000001
#define REG_CPLL_PDN_BIT 0x00000002
/*cpll register3*/
#define REG_CPLL_DIGDIV_MASK 0x0000F000
#define REG_CPLL_FBDIV_MASK 0x0000003F
#define SET_CPLL_CALI(n) REG_CPLL_CTRL_REGISTER1 &= ~REG_CPLL_CM_MASK; \
REG_CPLL_CTRL_REGISTER1 |= ((n&0xF) <<4);
#define SET_CPLL_RST REG_CPLL_CTRL_REGISTER2 |= REG_CPLL_RST_BIT;
#define CLEAR_CPLL_RST REG_CPLL_CTRL_REGISTER2 &= ~REG_CPLL_RST_BIT;
#define SET_CPLL_PWR_ON REG_CPLL_CTRL_REGISTER2 |= REG_CPLL_PDN_BIT;
#define SET_CPLL_PWR_DOWN REG_CPLL_CTRL_REGISTER2 &= ~REG_CPLL_PDN_BIT;
#define SET_CPLL_DIVCTRL(n) REG_CPLL_CTRL_REGISTER3 &= ~REG_CPLL_FBDIV_MASK; \
REG_CPLL_CTRL_REGISTER3 |= (n);
#define SET_CPLL_DIGITAL_DIVIDER(n) REG_CPLL_CTRL_REGISTER3 &= ~REG_CPLL_DIGDIV_MASK; \
REG_CPLL_CTRL_REGISTER3 |= ((n&0xF)<<12);
#elif(defined(DRV_ISP_MT6276_HW_SUPPORT))
#if defined(MT6276)
#define CPLL_BASE MIX_ABB_base
//0x61140000
#define REG_PLL_CTRL_REGISTER4 *((volatile unsigned int *) (CPLL_BASE + 0x0110))
#define REG_CPLL_CON0 *((volatile unsigned int *) (CPLL_BASE + 0x0200))
/*cpll register1*/
#define REG_FROM_CPLL_208M_MASK 0x00000001 //from cam pll output 208MHz clock
#define REG_CPLL_EN_MASK 0x00000001
#define REG_CPLL_LCON_MASK 0x0000000c
#define REG_CPLL_FX_CTRL_MASK 0x00000070
#define REG_CPLL_FSEL_MASK 0x00003F00
#define SET_CPLL_208M REG_CPLL_CON0 &= ~REG_CPLL_FSEL_MASK; \
REG_CPLL_CON0 |= (0x3A00);
#define SET_CPLL_156M REG_CPLL_CON0 &= ~REG_CPLL_FSEL_MASK; \
REG_CPLL_CON0 |= (0x2A00);
#define SET_CPLL_124_8M REG_CPLL_CON0 &= ~REG_CPLL_FSEL_MASK; \
REG_CPLL_CON0 |= (0x1100);
#define SET_CPLL_104M REG_CPLL_CON0 &= ~REG_CPLL_FSEL_MASK; \
REG_CPLL_CON0 |= (0x1A00);
#define SET_CPLL_PWR_ON REG_PLL_CTRL_REGISTER4 |= REG_FROM_CPLL_208M_MASK; \
REG_CPLL_CON0 |= REG_CPLL_EN_MASK; \
REG_CPLL_CON0 |= (0x4D);
#define SET_CPLL_PWR_DOWN REG_PLL_CTRL_REGISTER4 &= ~REG_FROM_CPLL_208M_MASK; \
REG_CPLL_CON0 &= ~REG_CPLL_EN_MASK;
#define SET_CPLL_CLK(n) REG_CPLL_CON0 &= ~REG_CPLL_FSEL_MASK; \
REG_CPLL_CON0 |= (n<<8);
#define SET_CPLL_RST //not use in MT6276
#define CLEAR_CPLL_RST //not use in MT6276
#define SET_CPLL_DIVCTRL(n) //not use in MT6276
#define SET_CPLL_DIGITAL_DIVIDER(n) //not use in MT6276
#elif defined(MT6256)||defined(MT6255) //MT6256/55 use UPLL
#define UPLL_BASE 0x801A0000
#define REG_UPLL_CTRL_REGISTER3 *((volatile unsigned int *) (UPLL_BASE + 0x020C))
#define MM_CLK_GATING_CLR_REGISTER *((volatile unsigned int *) (MMCONFG_base + 0x008))
#define MM_CLK_GATING_SET_REGISTER *((volatile unsigned int *) (MMCONFG_base + 0x008))
#define MM_CAM_CLK_GATING_MASK 0x00000020
#define REG_UPLL_RST_MASK 0x00000001
#define REG_UPLL_EN_MASK 0x00000002
#define REG_UPLL_FSEL_MASK 0x000000c0
/*
UPLL_CON3 bit 7:6 0x801A020c
0: 96, 1: 124, 2: 156, 3: 208
*/
#define UPLL_96M_CLK 0
#define UPLL_124M_CLK 1
#define UPLL_156M_CLK 2
#define UPLL_208M_CLK 3
#define SET_CAM_GATING MM_CLK_GATING_SET_REGISTER |= MM_CAM_CLK_GATING_MASK;
#define CLR_CAM_GATING MM_CLK_GATING_CLR_REGISTER |= MM_CAM_CLK_GATING_MASK;
#define SET_CPLL_208M REG_UPLL_CTRL_REGISTER3 &= ~REG_UPLL_FSEL_MASK; \
REG_UPLL_CTRL_REGISTER3 |= UPLL_208M_CLK<<6;
#define SET_CPLL_156M REG_UPLL_CTRL_REGISTER3 &= ~REG_UPLL_FSEL_MASK; \
REG_UPLL_CTRL_REGISTER3 |= UPLL_156M_CLK<<6;
#define SET_CPLL_124_8M REG_UPLL_CTRL_REGISTER3 &= ~REG_UPLL_FSEL_MASK; \
REG_UPLL_CTRL_REGISTER3 |= UPLL_124M_CLK<<6;
#define SET_CPLL_96M REG_UPLL_CTRL_REGISTER3 &= ~REG_UPLL_FSEL_MASK; \
REG_UPLL_CTRL_REGISTER3 |= UPLL_96M_CLK<<6;
#define SET_CPLL_PWR_ON REG_UPLL_CTRL_REGISTER3 |= REG_UPLL_EN_MASK; \
CLR_CAM_GATING;
#define SET_CPLL_PWR_DOWN SET_CAM_GATING; //Don't Diable UPLL which also used by other module(TDMA etc.)
#define SET_CPLL_RST REG_UPLL_CTRL_REGISTER3 |= REG_UPLL_RST_MASK;
#define CLEAR_CPLL_RST REG_UPLL_CTRL_REGISTER3 &= ~REG_UPLL_RST_MASK;
#define SET_CPLL_DIVCTRL(n) //not use in MT6276
#define SET_CPLL_DIGITAL_DIVIDER(n) //not use in MT6276
#endif
#else // other chip
#define CPLL_BASE
//0x840C0000
#define REG_CPLL_CTRL_REGISTER1
#define REG_CPLL_CTRL_REGISTER2
#define REG_CPLL_CTRL_REGISTER3
/*cpll register1*/
#define REG_CPLL_RST_BIT
#define REG_CPLL_FBDIV_MASK
#define REG_CPLL_CM_MASK
/*cpll register2*/
#define REG_CPLL_PDN_BIT
/*cpll register3*/
#define REG_CPLL_DIGDIV_MASK
#define SET_CPLL_RST
#define CLEAR_CPLL_RST
#define SET_CPLL_DIVCTRL(n)
#define SET_CPLL_CALI(n)
#define SET_CPLL_PWR_ON
#define SET_CPLL_PWR_DOWN
#define SET_CPLL_DIGITAL_DIVIDER(n)
#endif //MT6238,MT6268,MT6236
#endif