Echo / T3212_B2B_723 · Files

drv_features_adc.h 20.1 KB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 
/*****************************************************************************
*  Copyright Statement:
*  --------------------
*  This software is protected by Copyright and the information contained
*  herein is confidential. The software may not be copied and the information
*  contained herein may not be used or disclosed except with the written
*  permission of MediaTek Inc. (C) 2005
*
*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
*
*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. 
*
*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
*
*****************************************************************************/

/*****************************************************************************
 *
 * Filename:
 * ---------
 *    drv_features_adc.h
 *
 * Project:
 * --------
 *   Maui_Software
 *
 * Description:
 * ------------
 *   This file is for the ADC driver features
 *
 * Author:
 * -------
 * -------
 *
 *============================================================================
 *             HISTORY
 * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
 *------------------------------------------------------------------------------
 * removed!
 * removed!
 * removed!
 *
 * removed!
 * removed!
 * removed!
 *
 * removed!
 * removed!
 * removed!
 *
 * removed!
 * removed!
 * removed!
 *
 * removed!
 * removed!
 * removed!
 *
 * removed!
 * removed!
 * removed!
 *
 * removed!
 * removed!
 * removed!
 *
 * removed!
 * removed!
 * removed!
 *
 * removed!
 * removed!
 * removed!
 * removed!
 * removed!
 * removed!
 * removed!
 *
 * removed!
 * removed!
 * removed!
 *
 * removed!
 * removed!
 * removed!
 *
 * removed!
 * removed!
 * removed!
 *
 * removed!
 * removed!
 * removed!
 *
 * removed!
 * removed!
 * removed!
 *
 * removed!
 * removed!
 * removed!
 *
 * removed!
 * removed!
 * removed!
 *
 * removed!
 * removed!
 * removed!
 *
 * removed!
 * removed!
 * removed!
 *
 * removed!
 * removed!
 * removed!
 *
 * removed!
 * removed!
 * removed!
 *
 * removed!
 * removed!
 * removed!
 *
 * removed!
 * removed!
 * removed!
 *
 * removed!
 * removed!
 * removed!
 *
 * removed!
 * removed!
 * removed!
 *
 * removed!
 * removed!
 * removed!
 *
 * removed!
 * removed!
 * removed!
 *
 * removed!
 * removed!
 * removed!
 *
 * removed!
 * removed!
 * removed!
 *
 * removed!
 * removed!
 * removed!
 *
 * removed!
 * removed!
 * removed!
 *
 * removed!
 * removed!
 * removed!
 *
 * removed!
 * removed!
 * removed!
 *
 * removed!
 * removed!
 * removed!
 *
 * removed!
 * removed!
 * removed!
 *
 * removed!
 * removed!
 * removed!
 *
 * removed!
 * removed!
 * removed!
 * removed!
 *
 *------------------------------------------------------------------------------
 * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
 *============================================================================
 ****************************************************************************/
 
#ifndef __DRV_FEATURES_ADC_H__
#define __DRV_FEATURES_ADC_H__

/**************** ADC ******************/
#include "drv_features_chip_select.h"

#if defined(DRV_ADC_6205_SERIES)
   #define DRV_ADC_LIMIT_REG
   #define DRV_ADC_OLD_FUNC
   #define DRV_ADC_NO_IMM
   
#elif defined(DRV_ADC_6205B_SERIES)
   #define DRV_ADC_BASIC_REG
   #define DRV_ADC_MAX_CH_5
   #define ADC_MAX_CHANNEL 5
   #define DRV_ADC_FULL_FUNC
   #define DRV_ADC_TDMA_TIME
   #define DRV_ADC_IMM
   
#elif defined(DRV_ADC_6208_SERIES)
   #define DRV_ADC_LIMIT_REG
   /* for adc_pwrdown_enable() */
   #define DRV_ADC_6208_PWRDOWN
   #define DRV_ADC_NO_IMM
   
#elif defined(DRV_ADC_6217_SERIES)
   #define DRV_ADC_BASIC_REG
   #define DRV_ADC_MAX_CH_7
   #define ADC_MAX_CHANNEL 7
   #define DRV_ADC_FULL_FUNC
   #define DRV_ADC_TDMA_TIME
   #define DRV_ADC_IMM
   
#elif defined(DRV_ADC_6218B_SERIES)
   #define DRV_ADC_BASIC_REG
   #define DRV_ADC_MAX_CH_7
   #define ADC_MAX_CHANNEL 7
   #define DRV_ADC_FULL_FUNC
   #define DRV_ADC_TDMA_TIME
   #define DRV_ADC_IMM
   #define DRV_AUX_AC_CON_DEF_F

#elif defined(DRV_ADC_6223_SERIES)
   #define DRV_ADC_BASIC_REG
   #define DRV_ADC_TDMA_EVENT_REG_POS2
   #define DRV_ADC_TDMA_EN_REG_POS1
   #define DRV_ADC_MAX_CH_7
   #define ADC_MAX_CHANNEL 7
   #define DRV_ADC_FULL_FUNC
   #define DRV_ADC_TDMA_TIME
   #define DRV_ADC_IMM
   #define DRV_AUX_AC_CON_DEF_0
      
#elif defined(DRV_ADC_6225_SERIES)
   #define DRV_ADC_BASIC_REG
   #define DRV_ADC_TDMA_EVENT_REG_POS1
   #define DRV_ADC_MAX_CH_7
   #define ADC_MAX_CHANNEL 7
   #define DRV_ADC_FULL_FUNC
   #define DRV_ADC_TDMA_TIME
   #define DRV_ADC_IMM
   #define DRV_AUX_AC_CON_DEF_0
   
#elif defined(DRV_ADC_6226_SERIES)
   #define DRV_ADC_BASIC_REG
   #define DRV_ADC_TDMA_EVENT_REG_POS1
   #define DRV_ADC_MAX_CH_7
   #define ADC_MAX_CHANNEL 7
   #define DRV_ADC_FULL_FUNC
   #define DRV_ADC_TDMA_TIME
   #define DRV_ADC_IMM
   #define DRV_AUX_AC_CON_DEF_F
   
#elif defined(DRV_ADC_6228_SERIES)
   #define DRV_ADC_BASIC_REG
   #define DRV_ADC_MAX_CH_7
   #define ADC_MAX_CHANNEL 7
   #define DRV_ADC_FULL_FUNC
   #define DRV_ADC_TDMA_TIME
   #define DRV_ADC_IMM
   #define DRV_AUX_AC_CON_DEF_X
    
#elif defined(DRV_ADC_6229_SERIES)
   #define DRV_ADC_BASIC_REG
   #define DRV_ADC_TDMA_EVENT_REG_POS2
   #define DRV_ADC_TDMA_EN_REG_POS1
   #define DRV_ADC_MAX_CH_7
   #define ADC_MAX_CHANNEL 7
   #define DRV_ADC_FULL_FUNC
   #define DRV_ADC_TDMA_TIME
   #define DRV_ADC_IMM
   #define DRV_AUX_AC_CON_DEF_X
      
#elif defined(DRV_ADC_6235_SERIES)
   #define DRV_ADC_BASIC_REG
   #define DRV_ADC_TDMA_EVENT_REG_POS2
   #define DRV_ADC_TDMA_EN_REG_POS1
   #define DRV_ADC_MAX_CH_7
   #define ADC_MAX_CHANNEL 7
   #define DRV_ADC_FULL_FUNC
   #define DRV_ADC_TDMA_TIME
   #define DRV_ADC_IMM
   #define DRV_AUX_AC_CON_DEF_0

#elif defined(DRV_ADC_6238_SERIES)
   #define DRV_ADC_BASIC_REG
   #define DRV_ADC_TDMA_EVENT_REG_POS2
   #define DRV_ADC_TDMA_EN_REG_POS1
   #define DRV_ADC_MAX_CH_7
   #define ADC_MAX_CHANNEL 7
   #define DRV_ADC_FULL_FUNC
   #define DRV_ADC_TDMA_TIME
   #define DRV_ADC_IMM
   #define DRV_AUX_AC_CON_DEF_0

#elif defined(DRV_ADC_6268_SERIES)
   #define DRV_ADC_BASIC_REG
   #define DRV_ADC_TDMA_EVENT_REG_POS2
   #define DRV_ADC_TDMA_EN_REG_POS1
   #define DRV_ADC_MAX_CH_9
   #define ADC_MAX_CHANNEL 9
   #define DRV_ADC_FULL_FUNC
   #define DRV_ADC_TDMA_TIME
   #define DRV_ADC_IMM
   #define DRV_AUX_AC_CON_DEF_0
   /*
      Indicate we do NOT need to configure ADC related TDMA settings
      in ADC_Init()
      This will overwrite DRV_AUX_AC_CON_DEF_XXX defines
      MT6268A does NOT have 0x8050XXXX address for AUX_ADC to configure default settings
   */
   #define DRV_ADC_NO_ADC_DEF_CONFIG
  
   /*
      MT6268A ADC Sync mode issue temp workaround
   */
   #define __CHARGER_WITH_IMMEDIMATE_ADC__
   
   #define __DRV_ADC_PMIC_TURN_ON_MEASURE_DELAY__
   
#elif defined(DRV_ADC_6252_SERIES)
   #define DRV_ADC_BASIC_REG
   #define DRV_ADC_TDMA_EVENT_REG_POS2
   #define DRV_ADC_TDMA_EN_REG_POS1
   #define DRV_ADC_MAX_CH_6
   #define ADC_MAX_CHANNEL 6
   #define DRV_ADC_FULL_FUNC
   #define DRV_ADC_TDMA_TIME
   #define DRV_ADC_IMM
   #define DRV_AUX_AC_CON_DEF_0
   #define DRV_ADC_NO_ADC_DEF_CONFIG
   /*
      ADC S/W reset: Use BIT7, the bit is used as TEST_DACMON in MT6205B
      Write 1: Reset AuxADC module, after 1 tick, AuxADC module is reset
      Write 0: Back to normal mode
      From MT6229, TEST_DACMON feature is gone
      The S/W reset design is from MT6253T
   */
   #define DRV_ADC_SW_RESET
   /*
     Indicate TEST_DACMON feature is NOT support
   */
   #define DRV_ADC_NO_TEST_DACMON
   #define DRV_ADC_CALIBRATION_EFUSE // For ADC Efuse
 
   #define DRV_DISABLE_SAP_ID
#elif defined(DRV_ADC_6250_SERIES)
   #define DRV_ADC_BASIC_REG
   #define DRV_ADC_TDMA_EVENT_REG_POS2
   #define DRV_ADC_TDMA_EN_REG_POS1
   #define DRV_ADC_MAX_CH_12
   #define ADC_MAX_CHANNEL 12
   #define DRV_ADC_FULL_FUNC
   #define DRV_ADC_TDMA_TIME
   #define DRV_ADC_IMM
   #define DRV_AUX_AC_CON_DEF_0
   #define DRV_ADC_NO_ADC_DEF_CONFIG
   /*
	 ADC S/W reset: Use BIT7, the bit is used as TEST_DACMON in MT6205B
	 Write 1: Reset AuxADC module, after 1 tick, AuxADC module is reset
	 Write 0: Back to normal mode
	 From MT6229, TEST_DACMON feature is gone
	 The S/W reset design is from MT6253T
     */
   #define DRV_ADC_SW_RESET

   /*
   	when BT and sleep mode are enabled , adc might read small wrong value (ex:vbat = 2v)
   	the option will double check vbat value , if it is not valid (>2.9v) ,reset adc
   */
   #define DRV_ADC_CHECK_IS_VBAT_VALID
   
   /*
	     Indicate TEST_DACMON feature is NOT support
      */
   #define DRV_ADC_NO_TEST_DACMON
  	
   #define DRV_DISABLE_SAP_ID

   #define DRV_ADC_DELAY_FOR_ADCCAP // make sure the capacitance is fully charge

   #define DRV_ADC_NO_PUWAIT_EN		//	it will affect 2GTx when it enable
   #define DRV_ADC_SAMPLE_10bIT	
   #define DRV_ADC_CALIBRATION_EFUSE // For ADC Efuse	
   #define DRV_DIE_TO_DIE_INTERFACE
   #define DRV_MISC_ADC_MEASURE_REMOVE_IRQMASK
   
   #define DRV_ADC_BUSYBIT_ASSERT_CHECK
  // #define __CHARGER_WITH_IMMEDIMATE_ADC__
   #define DRV_ADC_WAKE_UP_TDMA_TIMER
   #define __DRV_ADC_SYNC_META__
   #define DRV_ADC_SW_RESET_CHECK_FOR_BUSY_BIT

#elif defined(DRV_ADC_6260_SERIES)
   #define DRV_ADC_BASIC_REG
   #define DRV_ADC_MAX_CH_12
   #define ADC_MAX_CHANNEL 12
   #define DRV_ADC_FULL_FUNC
   #define DRV_ADC_TDMA_TIME
   #define DRV_ADC_IMM
   #define DRV_ADC_NO_ADC_DEF_CONFIG
   //#define __CHARGER_WITH_IMMEDIMATE_ADC__
   //#define DRV_MISC_ADC_FIXED_VBAT_WA


   #define DRV_ADC_SW_RESET

      /*
	     Indicate TEST_DACMON feature is NOT support
      */
   #define DRV_ADC_NO_TEST_DACMON

   #define DRV_DISABLE_SAP_ID
   #define DRV_ADC_DELAY_FOR_ADCCAP // make sure the capacitance is fully charge

   #define DRV_ADC_NO_PUWAIT_EN		//	it will affect 2GTx when it enable
   #define DRV_ADC_SAMPLE_10bIT	
   #define DRV_ADC_CALIBRATION_EFUSE // For ADC Efuse	
   #define DRV_DIE_TO_DIE_INTERFACE_V2
   #define DRV_MISC_ADC_MEASURE_REMOVE_IRQMASK
   #define DRV_ADC_WAKE_UP_TDMA_TIMER

#elif defined(DRV_ADC_6261_SERIES)
   #define DRV_ADC_BASIC_REG
   #define DRV_ADC_MAX_CH_16
   #define ADC_MAX_CHANNEL 16
   #define DRV_ADC_FULL_FUNC
   #define DRV_ADC_TDMA_TIME
   #define DRV_ADC_IMM
   #define DRV_ADC_NO_ADC_DEF_CONFIG
   #define __CHARGER_WITH_IMMEDIMATE_ADC__
   //#define DRV_MISC_ADC_FIXED_VBAT_WA

   #define DRV_ADC_TP_ADC

   #define PMIC_FIXED_3_ADC_CH
   #define PMIC_FIXED_4_ADC_CH

   /* adc number for measuring VBAT/VISENSE/VCHARGER is fixed internally. */
   #define PMU_ADC_VBAT_CH_NUM      0
   #define PMU_ADC_VISENSE_CH_NUM   1
   #define PMU_ADC_VCHARGER_CH_NUM  2
   #define PMU_ADC_VBATTEMP_CH_NUM  3

   /* adc factor for VBAT/VISENSE/VCHARGER */
   #define PMU_ADC_FACTOR_VBAT      100
   #define PMU_ADC_FACTOR_VISENSE   100
   #define PMU_ADC_FACTOR_VCHARGER  473  // (369/39 * 50)
   #define PMU_ADC_FACTOR_VBATTEMP  50

  //#define DRV_ADC_DVT
  #define DRV_ADC_ZCV_SUPPORT  
   #define DRV_ADC_SW_RESET

      /*
	     Indicate TEST_DACMON feature is NOT support
      */
   #define DRV_ADC_NO_TEST_DACMON

   #define DRV_DISABLE_SAP_ID
   #define DRV_ADC_DELAY_FOR_ADCCAP // make sure the capacitance is fully charge

   #define DRV_ADC_NO_PUWAIT_EN		//	it will affect 2GTx when it enable
   #define DRV_ADC_SAMPLE_10bIT	
   #define DRV_ADC_CALIBRATION_EFUSE // For ADC Efuse	
   #define DRV_MISC_ADC_MEASURE_REMOVE_IRQMASK
   #define DRV_ADC_WAKE_UP_TDMA_TIMER
   #define DRV_ADC_ZCV_SUPPORT

   
#elif defined(DRV_ADC_6253_SERIES)
   #define DRV_ADC_BASIC_REG
   #define DRV_ADC_TDMA_EVENT_REG_POS2
   #define DRV_ADC_TDMA_EN_REG_POS1
   #define DRV_ADC_MAX_CH_6
   #define ADC_MAX_CHANNEL 6
   #define DRV_ADC_FULL_FUNC
   #define DRV_ADC_TDMA_TIME
   #define DRV_ADC_IMM
   #define DRV_AUX_AC_CON_DEF_0
   #define DRV_ADC_NO_ADC_DEF_CONFIG
   /*
      ADC S/W reset: Use BIT7, the bit is used as TEST_DACMON in MT6205B
      Write 1: Reset AuxADC module, after 1 tick, AuxADC module is reset
      Write 0: Back to normal mode
      From MT6229, TEST_DACMON feature is gone
      The S/W reset design is from MT6253T
   */
   #define DRV_ADC_SW_RESET
   /*
     Indicate TEST_DACMON feature is NOT support
   */
   #define DRV_ADC_NO_TEST_DACMON

#elif defined(DRV_ADC_MT6516_AP_SERIES)
   #define DRV_ADC_BASIC_REG
   #define DRV_ADC_TDMA_EVENT_REG_POS2
   #define DRV_ADC_TDMA_EN_REG_POS1
   #define DRV_ADC_MAX_CH_9
   #define ADC_MAX_CHANNEL 9
   #define DRV_ADC_FULL_FUNC
   #define DRV_ADC_TDMA_TIME
   #define DRV_ADC_IMM
   #define DRV_AUX_AC_CON_DEF_0
   /*
      Indicate we do NOT need to configure ADC related TDMA settings
      in ADC_Init()
      This will overwrite DRV_AUX_AC_CON_DEF_XXX defines
      MT6268A does NOT have 0x8050XXXX address for AUX_ADC to configure default settings
   */
   #define DRV_ADC_NO_ADC_DEF_CONFIG

   /*
      Indicate there is ADC background detection mechanism V1
   */
   #define DRV_ADC_BACKGROUND_DET_REG_V1

   /*
      Indicate ADC CG/PDN control is at CON0
   */
   #define ADC_CG_PDN_CON0   

#elif defined(DRV_ADC_6236_SERIES)
   #define DRV_ADC_BASIC_REG
   #define DRV_ADC_TDMA_EVENT_REG_POS2
   #define DRV_ADC_TDMA_EN_REG_POS1
   #define DRV_ADC_MAX_CH_8 //The difference with MT6253
   #define ADC_MAX_CHANNEL 8
   #define DRV_ADC_FULL_FUNC
   #define DRV_ADC_TDMA_TIME
   #define DRV_ADC_IMM
   #define DRV_AUX_AC_CON_DEF_0
   #define DRV_ADC_NO_ADC_DEF_CONFIG
   /*
      ADC S/W reset: Use BIT7, the bit is used as TEST_DACMON in MT6205B
      Write 1: Reset AuxADC module, after 1 tick, AuxADC module is reset
      Write 0: Back to normal mode
      From MT6229, TEST_DACMON feature is gone
      The S/W reset design is from MT6253T
   */
   #define DRV_ADC_SW_RESET
   /*
     Indicate TEST_DACMON feature is NOT support
   */
   #define DRV_ADC_NO_TEST_DACMON
    /*
	For 6236 E2, E3 ADC Parameter Change
    */
	#define DRV_ADC_VCHARGE_FACTOR_OVERWRITE
	 
#elif defined(DRV_ADC_6256_SERIES)
   #define DRV_ADC_BASIC_REG
   #define DRV_ADC_TDMA_EVENT_REG_POS2
   #define DRV_ADC_TDMA_EN_REG_POS1
   #define DRV_ADC_MAX_CH_13
   #define ADC_MAX_CHANNEL 13
   #define DRV_ADC_FULL_FUNC
   #define DRV_ADC_TDMA_TIME
   #define DRV_ADC_IMM
   #define DRV_AUX_AC_CON_DEF_0
   #define DRV_ADC_NO_ADC_DEF_CONFIG
   #define DRV_ADC_DELAY_FOR_ADCCAP	// make sure the capacitance is fully charge
   /*
      ADC S/W reset: Use BIT7, the bit is used as TEST_DACMON in MT6205B
      Write 1: Reset AuxADC module, after 1 tick, AuxADC module is reset
      Write 0: Back to normal mode
      From MT6229, TEST_DACMON feature is gone
      The S/W reset design is from MT6253T
   */
   #define DRV_ADC_SW_RESET
   /*
     Indicate TEST_DACMON feature is NOT support
   */
   #define DRV_ADC_NO_TEST_DACMON
   #define DRV_ADC_NO_PUWAIT_EN		//	it will affect 2GTx when it enable
   #define DRV_ADC_SAMPLE_12bIT	
   #define DRV_ADC_CALIBRATION_EFUSE // For ADC Efuse	 

#elif defined(DRV_ADC_6276_SERIES)
   #define DRV_ADC_BASIC_REG
   #define DRV_ADC_TDMA_EVENT_REG_POS2
   #define DRV_ADC_TDMA_EN_REG_POS1
   #define DRV_ADC_MAX_CH_13
   #define ADC_MAX_CHANNEL 13
   #define DRV_ADC_FULL_FUNC
   #define DRV_ADC_TDMA_TIME
   #define DRV_ADC_IMM
   #define DRV_AUX_AC_CON_DEF_0
   #define DRV_ADC_NO_ADC_DEF_CONFIG
   /*
      ADC S/W reset: Use BIT7, the bit is used as TEST_DACMON in MT6205B
      Write 1: Reset AuxADC module, after 1 tick, AuxADC module is reset
      Write 0: Back to normal mode
      From MT6229, TEST_DACMON feature is gone
      The S/W reset design is from MT6253T
   */
   #define DRV_ADC_SW_RESET
   /*
     Indicate TEST_DACMON feature is NOT support
   */
   #define DRV_ADC_NO_TEST_DACMON 
   
   /*
      MT6268A ADC Sync mode issue temp workaround
   */
   #define __CHARGER_WITH_IMMEDIMATE_ADC__

   /* To adjust bias current to 1.5 times than original to avoid current issue  */	
   #define DRV_ADC_BIAS_CURRENT_ENLARGE   
   #define DRV_ADC_VCHARGER_EXTEND_READING	// extend adc read period for VCHARGER
   #define DRV_ADC_SAMPLE_12bIT

#elif defined(DRV_ADC_6251_SERIES)
   #define DRV_ADC_BASIC_REG
   #define DRV_ADC_TDMA_EVENT_REG_POS2
   #define DRV_ADC_TDMA_EN_REG_POS1
   #define DRV_ADC_MAX_CH_13
   #define ADC_MAX_CHANNEL 13
   #define DRV_ADC_FULL_FUNC
   #define DRV_ADC_TDMA_TIME
   #define DRV_ADC_IMM
   #define DRV_AUX_AC_CON_DEF_0
   #define DRV_ADC_NO_ADC_DEF_CONFIG
   /*
      ADC S/W reset: Use BIT7, the bit is used as TEST_DACMON in MT6205B
      Write 1: Reset AuxADC module, after 1 tick, AuxADC module is reset
      Write 0: Back to normal mode
      From MT6229, TEST_DACMON feature is gone
      The S/W reset design is from MT6253T
   */
   #define DRV_ADC_SW_RESET
   /*
     Indicate TEST_DACMON feature is NOT support
   */
   #define DRV_ADC_NO_TEST_DACMON

   /* ADC_VBAT channel use factor = 3 inside PMU, this define for NVRAM ADC setting*/
   #define __DRV_ADC_VBAT_FACTOR_3__

   #define DRV_ADC_SAMPLE_12bIT
#elif defined(DRV_ADC_6573_SERIES)
    #define DRV_ADC_BASIC_REG
    #define DRV_ADC_MAX_CH_13
    #define ADC_MAX_CHANNEL 13
    #define DRV_ADC_FULL_FUNC
    #define DRV_ADC_TDMA_TIME
    #define DRV_ADC_IMM
    #define DRV_ADC_MODEM_SIDE // For Modem Side Measure RF_TEMP
    #define __CHARGER_WITH_IMMEDIMATE_ADC__
    #define DRV_ADC_SAMPLE_12bIT

#elif defined(DRV_ADC_6575_SERIES)
    #define DRV_ADC_BASIC_REG
    #define DRV_ADC_MAX_CH_13
    #define ADC_MAX_CHANNEL 13
    #define DRV_ADC_FULL_FUNC
    #define DRV_ADC_TDMA_TIME
    #define DRV_ADC_IMM
    #define DRV_ADC_MODEM_SIDE // For Modem Side Measure RF_TEMP
    #define __CHARGER_WITH_IMMEDIMATE_ADC__
 	#define DRV_ADC_SET_CLR
	
    #define DRV_ADC_SAMPLE_12bIT
	#define ADC_CPU_TEMP_SENSOR_USE
	#define DRV_ADC_CALIBRATION_EFUSE
	
#elif defined(DRV_ADC_6255_SERIES)
   #define DRV_ADC_BASIC_REG
   #define DRV_ADC_TDMA_EVENT_REG_POS2
   #define DRV_ADC_TDMA_EN_REG_POS1
   #define DRV_ADC_MAX_CH_13
   #define ADC_MAX_CHANNEL 13
   #define DRV_ADC_FULL_FUNC
   #define DRV_ADC_TDMA_TIME
   #define DRV_ADC_IMM
   #define DRV_AUX_AC_CON_DEF_0
   #define DRV_ADC_NO_ADC_DEF_CONFIG
   #define DRV_ADC_DELAY_FOR_ADCCAP	// make sure the capacitance is fully charge
	   /*
		  ADC S/W reset: Use BIT7, the bit is used as TEST_DACMON in MT6205B
		  Write 1: Reset AuxADC module, after 1 tick, AuxADC module is reset
		  Write 0: Back to normal mode
		  From MT6229, TEST_DACMON feature is gone
		  The S/W reset design is from MT6253T
	   */
   #define DRV_ADC_SW_RESET
	   /*
		 Indicate TEST_DACMON feature is NOT support
	   */
   #define DRV_ADC_NO_TEST_DACMON
   #define DRV_ADC_NO_PUWAIT_EN		//	it will affect 2GTx when it enable
   #define DRV_ADC_SAMPLE_12bIT	
   #define DRV_ADC_CALIBRATION_EFUSE

   #if defined(__UMTS_TDD128_MODE__)
   #define __CHARGER_WITH_IMMEDIMATE_ADC__	
   #endif
   	
       
#elif defined(DRV_ADC_NOT_EXIST)
#if !defined(DRV_ADC_MAX_CH_1)
#define DRV_ADC_MAX_CH_1
#define ADC_MAX_CHANNEL 1
#define DRV_ADC_TDMA_TIME
#endif

#endif // ADC series

//#ifdef __MEUT__
#define DCL_ADC_INTERFACE
//#endif

#endif /*End __DRV_FEATURES_ADC_H__*/