~reg_base_after_transform.tmp
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#include ".\hal\system\regbase\inc\reg_base_mt6261.h"
typedef struct dummy_reg
{
int VERSION_base_decl = VERSION_base;
int CONFIG_base_decl = CONFIG_base;
int GPIO_base_decl = GPIO_base;
int RGU_base_decl = RGU_base;
int EMI_base_decl = EMI_base;
int CIRQ_base_decl = CIRQ_base;
int DMA_base_decl = DMA_base;
int UART1_base_decl = UART1_base;
int UART2_base_decl = UART2_base;
int UART3_base_decl = UART3_base;
int BTIF_base_decl = BTIF_base;
int GPT_base_decl = GPT_base;
int KP_base_decl = KP_base;
int PWM_base_decl = PWM_base;
int SIM_base_decl = SIM_base;
int SIM2_base_decl = SIM2_base;
int SEJ_base_decl = SEJ_base;
int I2C_base_decl = I2C_base;
int MSDC_base_decl = MSDC_base;
int SFI_base_decl = SFI_base;
int MIXED_base_decl = MIXED_base;
int PLL_base_decl = PLL_base;
int MCU_TOPSM_base_decl = MCU_TOPSM_base;
int EFUSE_base_decl = EFUSE_base;
int SPI_base_decl = SPI_base;
int OSTIMER_base_decl = OSTIMER_base;
int ANALOG_MAP__base_decl = ANALOG_MAP__base;
int MCU_MBIST_base_decl = MCU_MBIST_base;
int FSPI_MAS_base_decl = FSPI_MAS_base;
int MSDC2_base_decl = MSDC2_base;
int PWM2_base_decl = PWM2_base;
int SPI_SLAVE_base_decl = SPI_SLAVE_base;
int I2C_18V_base_decl = I2C_18V_base;
int ROT_DMA_base_decl = ROT_DMA_base;
int CRZ_base_decl = CRZ_base;
int CAMERA_base_decl = CAMERA_base;
int CAM_base_decl = CAM_base;
int SCAM_base_decl = SCAM_base;
int G2D_base_decl = G2D_base;
int LCD_base_decl = LCD_base;
int MMSYS_MBIST_base_decl = MMSYS_MBIST_base;
int MM_COLOR_base_decl = MM_COLOR_base;
int MMSYS_CONFIG_base_decl = MMSYS_CONFIG_base;
int ARM_CONFG_base_decl = ARM_CONFG_base;
int BOOT_ENG_base_decl = BOOT_ENG_base;
int CDCMP_base_decl = CDCMP_base;
int L1_CACHE_base_decl = L1_CACHE_base;
int MPU_base_decl = MPU_base;
int PMU_base_decl = PMU_base;
int RTC_base_decl = RTC_base;
int ABBSYS_base_decl = ABBSYS_base;
int ANA_CFGSYS_base_decl = ANA_CFGSYS_base;
int PWM_2CH_base_decl = PWM_2CH_base;
int ACCDET_base_decl = ACCDET_base;
int ADIE_CIRQ_base_decl = ADIE_CIRQ_base;
int AUXADC_base_decl = AUXADC_base;
int USB_base_decl = USB_base;
int USB_SIFSLV_base_decl = USB_SIFSLV_base;
int DMA_AHB_base_decl = DMA_AHB_base;
int BT_CONFG_base_decl = BT_CONFG_base;
int BT_CIRQ_base_decl = BT_CIRQ_base;
int BT_DMA_base_decl = BT_DMA_base;
int BT_BTIF_base_decl = BT_BTIF_base;
int BT_PKV_base_decl = BT_PKV_base;
int BT_TIM_base_decl = BT_TIM_base;
int BT_RF_base_decl = BT_RF_base;
int BT_MODEM_base_decl = BT_MODEM_base;
int BT_DBGIF_base_decl = BT_DBGIF_base;
int BT_MBIST_CONFG__base_decl = BT_MBIST_CONFG__base;
int IDMA_base_decl = IDMA_base;
int DPRAM_CPU_base_decl = DPRAM_CPU_base;
int AHB2DSPIO_base_decl = AHB2DSPIO_base;
int MD2GCONFG_base_decl = MD2GCONFG_base;
int MD2G_MBIST_CONFG_base_decl = MD2G_MBIST_CONFG_base;
int APC_base_decl = APC_base;
int CSD_ACC_base_decl = CSD_ACC_base;
int SHARE_base_decl = SHARE_base;
int IRDMA_base_decl = IRDMA_base;
int PATCH_base_decl = PATCH_base;
int AFE_base_decl = AFE_base;
int BFE_base_decl = BFE_base;
int MDCONFIG_base_decl = MDCONFIG_base;
int MODEM_MBIST_CONFIG_base_decl = MODEM_MBIST_CONFIG_base;
int MODEM2G_TOPSM_base_decl = MODEM2G_TOPSM_base;
int TDMA_base_decl = TDMA_base;
int SHAREG2_base_decl = SHAREG2_base;
int DIVIDER_base_decl = DIVIDER_base;
int FCS_base_decl = FCS_base;
int GCU_base_decl = GCU_base;
int BSI_base_decl = BSI_base;
int BPI_base_decl = BPI_base;
int VERSION_SD_base_decl = VERSION_SD_base;
int CONFIG_SD_base_decl = CONFIG_SD_base;
int GPIO_SD_base_decl = GPIO_SD_base;
int RGU_SD_base_decl = RGU_SD_base;
int EMI_SD_base_decl = EMI_SD_base;
int CIRQ_SD_base_decl = CIRQ_SD_base;
int DMA_SD_base_decl = DMA_SD_base;
int UART1_SD_base_decl = UART1_SD_base;
int UART2_SD_base_decl = UART2_SD_base;
int UART3_SD_base_decl = UART3_SD_base;
int BTIF_SD_base_decl = BTIF_SD_base;
int GPT_SD_base_decl = GPT_SD_base;
int KP_SD_base_decl = KP_SD_base;
int PWM_SD_base_decl = PWM_SD_base;
int SIM_SD_base_decl = SIM_SD_base;
int SIM2_SD_base_decl = SIM2_SD_base;
int SEJ_SD_base_decl = SEJ_SD_base;
int I2C_SD_base_decl = I2C_SD_base;
int MSDC_SD_base_decl = MSDC_SD_base;
int SFI_SD_base_decl = SFI_SD_base;
int MIXED_SD_base_decl = MIXED_SD_base;
int PLL_SD_base_decl = PLL_SD_base;
int MCU_TOPSM_SD_base_decl = MCU_TOPSM_SD_base;
int EFUSE_SD_base_decl = EFUSE_SD_base;
int SPI_SD_base_decl = SPI_SD_base;
int OSTIMER_SD_base_decl = OSTIMER_SD_base;
int ANALOG_MAP__SD_base_decl = ANALOG_MAP__SD_base;
int MCU_MBIST_SD_base_decl = MCU_MBIST_SD_base;
int FSPI_MAS_SD_base_decl = FSPI_MAS_SD_base;
int MSDC2_SD_base_decl = MSDC2_SD_base;
int PWM2_SD_base_decl = PWM2_SD_base;
int SPI_SLAVE_SD_base_decl = SPI_SLAVE_SD_base;
int I2C_18V_SD_base_decl = I2C_18V_SD_base;
int ROT_DMA_SD_base_decl = ROT_DMA_SD_base;
int CRZ_SD_base_decl = CRZ_SD_base;
int CAMERA_SD_base_decl = CAMERA_SD_base;
int CAM_SD_base_decl = CAM_SD_base;
int SCAM_SD_base_decl = SCAM_SD_base;
int G2D_SD_base_decl = G2D_SD_base;
int LCD_SD_base_decl = LCD_SD_base;
int MMSYS_MBIST_SD_base_decl = MMSYS_MBIST_SD_base;
int MM_COLOR_SD_base_decl = MM_COLOR_SD_base;
int MMSYS_CONFIG_SD_base_decl = MMSYS_CONFIG_SD_base;
int ARM_CONFG_SD_base_decl = ARM_CONFG_SD_base;
int BOOT_ENG_SD_base_decl = BOOT_ENG_SD_base;
int CDCMP_SD_base_decl = CDCMP_SD_base;
int L1_CACHE_SD_base_decl = L1_CACHE_SD_base;
int MPU_SD_base_decl = MPU_SD_base;
int PMU_SD_base_decl = PMU_SD_base;
int RTC_SD_base_decl = RTC_SD_base;
int ABBSYS_SD_base_decl = ABBSYS_SD_base;
int ANA_CFGSYS_SD_base_decl = ANA_CFGSYS_SD_base;
int PWM_2CH_SD_base_decl = PWM_2CH_SD_base;
int ACCDET_SD_base_decl = ACCDET_SD_base;
int ADIE_CIRQ_SD_base_decl = ADIE_CIRQ_SD_base;
int AUXADC_SD_base_decl = AUXADC_SD_base;
int USB_SD_base_decl = USB_SD_base;
int USB_SIFSLV_SD_base_decl = USB_SIFSLV_SD_base;
int DMA_AHB_SD_base_decl = DMA_AHB_SD_base;
int BT_CONFG_SD_base_decl = BT_CONFG_SD_base;
int BT_CIRQ_SD_base_decl = BT_CIRQ_SD_base;
int BT_DMA_SD_base_decl = BT_DMA_SD_base;
int BT_BTIF_SD_base_decl = BT_BTIF_SD_base;
int BT_PKV_SD_base_decl = BT_PKV_SD_base;
int BT_TIM_SD_base_decl = BT_TIM_SD_base;
int BT_RF_SD_base_decl = BT_RF_SD_base;
int BT_MODEM_SD_base_decl = BT_MODEM_SD_base;
int BT_DBGIF_SD_base_decl = BT_DBGIF_SD_base;
int BT_MBIST_CONFG__SD_base_decl = BT_MBIST_CONFG__SD_base;
int IDMA_SD_base_decl = IDMA_SD_base;
int AHB2DSPIO_SD_base_decl = AHB2DSPIO_SD_base;
int MD2GCONFG_SD_base_decl = MD2GCONFG_SD_base;
int MD2G_MBIST_CONFG_SD_base_decl = MD2G_MBIST_CONFG_SD_base;
int APC_SD_base_decl = APC_SD_base;
int CSD_ACC_SD_base_decl = CSD_ACC_SD_base;
int SHARE_SD_base_decl = SHARE_SD_base;
int IRDMA_SD_base_decl = IRDMA_SD_base;
int PATCH_SD_base_decl = PATCH_SD_base;
int AFE_SD_base_decl = AFE_SD_base;
int BFE_SD_base_decl = BFE_SD_base;
int MDCONFIG_SD_base_decl = MDCONFIG_SD_base;
int MODEM_MBIST_CONFIG_SD_base_decl = MODEM_MBIST_CONFIG_SD_base;
int MODEM2G_TOPSM_SD_base_decl = MODEM2G_TOPSM_SD_base;
int TDMA_SD_base_decl = TDMA_SD_base;
int SHAREG2_SD_base_decl = SHAREG2_SD_base;
int DIVIDER_SD_base_decl = DIVIDER_SD_base;
int FCS_SD_base_decl = FCS_SD_base;
int GCU_SD_base_decl = GCU_SD_base;
int BSI_SD_base_decl = BSI_SD_base;
int BPI_SD_base_decl = BPI_SD_base;
}