#ifndef _SST_TRC_GEN_H_
#define _SST_TRC_GEN_H_

// SST_NEWLINE
#define SST_NEWLINE_size ""
#define SST_NEWLINE SST_NEWLINE__enum,SST_NEWLINE_size

// SST_NO
#define SST_NO_size "d"
#define SST_NO SST_NO__enum,SST_NO_size

// SST_4_HEX_VALUES
#define SST_4_HEX_VALUES_size "dddd"
#define SST_4_HEX_VALUES SST_4_HEX_VALUES__enum,SST_4_HEX_VALUES_size

// SST_3_HEX_VALUES
#define SST_3_HEX_VALUES_size "ddd"
#define SST_3_HEX_VALUES SST_3_HEX_VALUES__enum,SST_3_HEX_VALUES_size

// SST_2_HEX_VALUES
#define SST_2_HEX_VALUES_size "dd"
#define SST_2_HEX_VALUES SST_2_HEX_VALUES__enum,SST_2_HEX_VALUES_size

// SST_1_HEX_VALUES
#define SST_1_HEX_VALUES_size "d"
#define SST_1_HEX_VALUES SST_1_HEX_VALUES__enum,SST_1_HEX_VALUES_size

// SST_NAME
#define SST_NAME_size "cccccccc"
#define SST_NAME SST_NAME__enum,SST_NAME_size

// SST_TITLE1
#define SST_TITLE1_size ""
#define SST_TITLE1 SST_TITLE1__enum,SST_TITLE1_size

// SST_TITLE2
#define SST_TITLE2_size ""
#define SST_TITLE2 SST_TITLE2__enum,SST_TITLE2_size

// SST_ENDING1
#define SST_ENDING1_size ""
#define SST_ENDING1 SST_ENDING1__enum,SST_ENDING1_size

// SST_ENDING2
#define SST_ENDING2_size ""
#define SST_ENDING2 SST_ENDING2__enum,SST_ENDING2_size

// SST_DESCRIPTION
#define SST_DESCRIPTION_size ""
#define SST_DESCRIPTION SST_DESCRIPTION__enum,SST_DESCRIPTION_size

// SST_BOOTMODE_FACTORY_BOOT
#define SST_BOOTMODE_FACTORY_BOOT_size ""
#define SST_BOOTMODE_FACTORY_BOOT SST_BOOTMODE_FACTORY_BOOT__enum,SST_BOOTMODE_FACTORY_BOOT_size

// SST_BOOTMODE_NORMAL
#define SST_BOOTMODE_NORMAL_size ""
#define SST_BOOTMODE_NORMAL SST_BOOTMODE_NORMAL__enum,SST_BOOTMODE_NORMAL_size

// SST_BOOTMODE_USBMS_BOOT
#define SST_BOOTMODE_USBMS_BOOT_size ""
#define SST_BOOTMODE_USBMS_BOOT SST_BOOTMODE_USBMS_BOOT__enum,SST_BOOTMODE_USBMS_BOOT_size

// SST_RUNNING_TASK
#define SST_RUNNING_TASK_size "cccccccc"
#define SST_RUNNING_TASK SST_RUNNING_TASK__enum,SST_RUNNING_TASK_size

// SST_RUNNING_HISR
#define SST_RUNNING_HISR_size "cccccccc"
#define SST_RUNNING_HISR SST_RUNNING_HISR__enum,SST_RUNNING_HISR_size

// SST_RUNNING_LISR
#define SST_RUNNING_LISR_size ""
#define SST_RUNNING_LISR SST_RUNNING_LISR__enum,SST_RUNNING_LISR_size

// SST_RUNNING_INITIAL
#define SST_RUNNING_INITIAL_size ""
#define SST_RUNNING_INITIAL SST_RUNNING_INITIAL__enum,SST_RUNNING_INITIAL_size

// SST_RUNNING_UNKNOWN
#define SST_RUNNING_UNKNOWN_size ""
#define SST_RUNNING_UNKNOWN SST_RUNNING_UNKNOWN__enum,SST_RUNNING_UNKNOWN_size

// SST_EXCEPTION_ANALYSIS
#define SST_EXCEPTION_ANALYSIS_size ""
#define SST_EXCEPTION_ANALYSIS SST_EXCEPTION_ANALYSIS__enum,SST_EXCEPTION_ANALYSIS_size

// SST_EXCEPTION_GUIDELINE
#define SST_EXCEPTION_GUIDELINE_size ""
#define SST_EXCEPTION_GUIDELINE SST_EXCEPTION_GUIDELINE__enum,SST_EXCEPTION_GUIDELINE_size

// SST_MEMORY_CORRUPTION
#define SST_MEMORY_CORRUPTION_size ""
#define SST_MEMORY_CORRUPTION SST_MEMORY_CORRUPTION__enum,SST_MEMORY_CORRUPTION_size

// SST_LOOKS_GOOD
#define SST_LOOKS_GOOD_size ""
#define SST_LOOKS_GOOD SST_LOOKS_GOOD__enum,SST_LOOKS_GOOD_size

// SST_CPU_EXCEPTIONS
#define SST_CPU_EXCEPTIONS_size "d"
#define SST_CPU_EXCEPTIONS SST_CPU_EXCEPTIONS__enum,SST_CPU_EXCEPTIONS_size

// SST_PHASE1_UNDEFINED
#define SST_PHASE1_UNDEFINED_size "dd"
#define SST_PHASE1_UNDEFINED SST_PHASE1_UNDEFINED__enum,SST_PHASE1_UNDEFINED_size

// SST_PHASE1_CONSTRUCTION
#define SST_PHASE1_CONSTRUCTION_size "dd"
#define SST_PHASE1_CONSTRUCTION SST_PHASE1_CONSTRUCTION__enum,SST_PHASE1_CONSTRUCTION_size

// SST_PHASE1_UNDEFINED_ERROR_CODE
#define SST_PHASE1_UNDEFINED_ERROR_CODE_size "cccccdd"
#define SST_PHASE1_UNDEFINED_ERROR_CODE SST_PHASE1_UNDEFINED_ERROR_CODE__enum,SST_PHASE1_UNDEFINED_ERROR_CODE_size

// SST_DUMP_STACK
#define SST_DUMP_STACK_size "d"
#define SST_DUMP_STACK SST_DUMP_STACK__enum,SST_DUMP_STACK_size

// SST_DUMP_PROBLEM_STACK
#define SST_DUMP_PROBLEM_STACK_size "cccccccc"
#define SST_DUMP_PROBLEM_STACK SST_DUMP_PROBLEM_STACK__enum,SST_DUMP_PROBLEM_STACK_size

// SST_DUMP_STACK_FAILED
#define SST_DUMP_STACK_FAILED_size ""
#define SST_DUMP_STACK_FAILED SST_DUMP_STACK_FAILED__enum,SST_DUMP_STACK_FAILED_size

// SST_IRREGULAR_STACK_POINTER
#define SST_IRREGULAR_STACK_POINTER_size ""
#define SST_IRREGULAR_STACK_POINTER SST_IRREGULAR_STACK_POINTER__enum,SST_IRREGULAR_STACK_POINTER_size

// SST_SUSPEND_DISALLOWED_P1
#define SST_SUSPEND_DISALLOWED_P1_size ""
#define SST_SUSPEND_DISALLOWED_P1 SST_SUSPEND_DISALLOWED_P1__enum,SST_SUSPEND_DISALLOWED_P1_size

// SST_REFER_TO_ERROR_CODE
#define SST_REFER_TO_ERROR_CODE_size "d"
#define SST_REFER_TO_ERROR_CODE SST_REFER_TO_ERROR_CODE__enum,SST_REFER_TO_ERROR_CODE_size

// SST_PHASE3_JTAG_WB
#define SST_PHASE3_JTAG_WB_size "d"
#define SST_PHASE3_JTAG_WB SST_PHASE3_JTAG_WB__enum,SST_PHASE3_JTAG_WB_size

// SST_PHASE3_JTAG_WBS
#define SST_PHASE3_JTAG_WBS_size ""
#define SST_PHASE3_JTAG_WBS SST_PHASE3_JTAG_WBS__enum,SST_PHASE3_JTAG_WBS_size

// SST_PHASE3_OWNER
#define SST_PHASE3_OWNER_size "cccccccc"
#define SST_PHASE3_OWNER SST_PHASE3_OWNER__enum,SST_PHASE3_OWNER_size

// SST_PHASE3_OWNER_MSGID
#define SST_PHASE3_OWNER_MSGID_size "d"
#define SST_PHASE3_OWNER_MSGID SST_PHASE3_OWNER_MSGID__enum,SST_PHASE3_OWNER_MSGID_size

// SST_PHASE3_OWNER_MOD
#define SST_PHASE3_OWNER_MOD_size "ccccccccd"
#define SST_PHASE3_OWNER_MOD SST_PHASE3_OWNER_MOD__enum,SST_PHASE3_OWNER_MOD_size

// SST_PHASE3_OWNER_FILE
#define SST_PHASE3_OWNER_FILE_size "cccccccccccccccc"
#define SST_PHASE3_OWNER_FILE SST_PHASE3_OWNER_FILE__enum,SST_PHASE3_OWNER_FILE_size

// SST_PHASE3_OWNER_LR
#define SST_PHASE3_OWNER_LR_size "d"
#define SST_PHASE3_OWNER_LR SST_PHASE3_OWNER_LR__enum,SST_PHASE3_OWNER_LR_size

// SST_PHASE3_MAKE_SURE
#define SST_PHASE3_MAKE_SURE_size "cccccccc"
#define SST_PHASE3_MAKE_SURE SST_PHASE3_MAKE_SURE__enum,SST_PHASE3_MAKE_SURE_size

// SST_PHASE3_CALL_SST
#define SST_PHASE3_CALL_SST_size ""
#define SST_PHASE3_CALL_SST SST_PHASE3_CALL_SST__enum,SST_PHASE3_CALL_SST_size

// SST_PHASE3_DUMP_MEMORY
#define SST_PHASE3_DUMP_MEMORY_size ""
#define SST_PHASE3_DUMP_MEMORY SST_PHASE3_DUMP_MEMORY__enum,SST_PHASE3_DUMP_MEMORY_size

// SST_PHASE3_REMIND_DUMP_MEMORY
#define SST_PHASE3_REMIND_DUMP_MEMORY_size ""
#define SST_PHASE3_REMIND_DUMP_MEMORY SST_PHASE3_REMIND_DUMP_MEMORY__enum,SST_PHASE3_REMIND_DUMP_MEMORY_size

// SST_PHASE3_FOLLOW_RULE_CUSTOMIZATION
#define SST_PHASE3_FOLLOW_RULE_CUSTOMIZATION_size ""
#define SST_PHASE3_FOLLOW_RULE_CUSTOMIZATION SST_PHASE3_FOLLOW_RULE_CUSTOMIZATION__enum,SST_PHASE3_FOLLOW_RULE_CUSTOMIZATION_size

// SST_PHASE2_TASK_INFO
#define SST_PHASE2_TASK_INFO_size "d"
#define SST_PHASE2_TASK_INFO SST_PHASE2_TASK_INFO__enum,SST_PHASE2_TASK_INFO_size

// SST_PHASE2_TASK_INFO_G1
#define SST_PHASE2_TASK_INFO_G1_size "cccccc"
#define SST_PHASE2_TASK_INFO_G1 SST_PHASE2_TASK_INFO_G1__enum,SST_PHASE2_TASK_INFO_G1_size

// SST_PHASE2_TASK_INFO_G2
#define SST_PHASE2_TASK_INFO_G2_size "cccccc"
#define SST_PHASE2_TASK_INFO_G2 SST_PHASE2_TASK_INFO_G2__enum,SST_PHASE2_TASK_INFO_G2_size

// SST_PHASE2_TASK_INFO_G3
#define SST_PHASE2_TASK_INFO_G3_size "d"
#define SST_PHASE2_TASK_INFO_G3 SST_PHASE2_TASK_INFO_G3__enum,SST_PHASE2_TASK_INFO_G3_size

// SST_PHASE2_TASK_INFO_G4
#define SST_PHASE2_TASK_INFO_G4_size "d"
#define SST_PHASE2_TASK_INFO_G4 SST_PHASE2_TASK_INFO_G4__enum,SST_PHASE2_TASK_INFO_G4_size

// SST_PHASE2_TASK_INFO_G5
#define SST_PHASE2_TASK_INFO_G5_size "d"
#define SST_PHASE2_TASK_INFO_G5 SST_PHASE2_TASK_INFO_G5__enum,SST_PHASE2_TASK_INFO_G5_size

// SST_PHASE2_TASK_INFO_G6
#define SST_PHASE2_TASK_INFO_G6_size "d"
#define SST_PHASE2_TASK_INFO_G6 SST_PHASE2_TASK_INFO_G6__enum,SST_PHASE2_TASK_INFO_G6_size

// SST_PHASE2_TASK_INFO_G7
#define SST_PHASE2_TASK_INFO_G7_size "d"
#define SST_PHASE2_TASK_INFO_G7 SST_PHASE2_TASK_INFO_G7__enum,SST_PHASE2_TASK_INFO_G7_size

// SST_PHASE2_TASK_INFO_G8_1
#define SST_PHASE2_TASK_INFO_G8_1_size ""
#define SST_PHASE2_TASK_INFO_G8_1 SST_PHASE2_TASK_INFO_G8_1__enum,SST_PHASE2_TASK_INFO_G8_1_size

// SST_PHASE2_TASK_INFO_G8_2
#define SST_PHASE2_TASK_INFO_G8_2_size ""
#define SST_PHASE2_TASK_INFO_G8_2 SST_PHASE2_TASK_INFO_G8_2__enum,SST_PHASE2_TASK_INFO_G8_2_size

// SST_PHASE2_TASK_INFO_G9
#define SST_PHASE2_TASK_INFO_G9_size "d"
#define SST_PHASE2_TASK_INFO_G9 SST_PHASE2_TASK_INFO_G9__enum,SST_PHASE2_TASK_INFO_G9_size

// SST_PHASE2_TASK_INFO_G10
#define SST_PHASE2_TASK_INFO_G10_size "d"
#define SST_PHASE2_TASK_INFO_G10 SST_PHASE2_TASK_INFO_G10__enum,SST_PHASE2_TASK_INFO_G10_size

// SST_PHASE2_TASK_INFO_G11
#define SST_PHASE2_TASK_INFO_G11_size "d"
#define SST_PHASE2_TASK_INFO_G11 SST_PHASE2_TASK_INFO_G11__enum,SST_PHASE2_TASK_INFO_G11_size

// SST_PHASE2_TASK_INFO_STACK_ERROR
#define SST_PHASE2_TASK_INFO_STACK_ERROR_size "d"
#define SST_PHASE2_TASK_INFO_STACK_ERROR SST_PHASE2_TASK_INFO_STACK_ERROR__enum,SST_PHASE2_TASK_INFO_STACK_ERROR_size

// SST_PHASE2_TASK_INFO_ENTRY_ERROR
#define SST_PHASE2_TASK_INFO_ENTRY_ERROR_size "d"
#define SST_PHASE2_TASK_INFO_ENTRY_ERROR SST_PHASE2_TASK_INFO_ENTRY_ERROR__enum,SST_PHASE2_TASK_INFO_ENTRY_ERROR_size

// SST_ILM_STRUCT
#define SST_ILM_STRUCT_size "d"
#define SST_ILM_STRUCT SST_ILM_STRUCT__enum,SST_ILM_STRUCT_size

// SST_ILM_STRUCT_SOURCE
#define SST_ILM_STRUCT_SOURCE_size "d"
#define SST_ILM_STRUCT_SOURCE SST_ILM_STRUCT_SOURCE__enum,SST_ILM_STRUCT_SOURCE_size

// SST_ILM_STRUCT_DESTINATION
#define SST_ILM_STRUCT_DESTINATION_size "d"
#define SST_ILM_STRUCT_DESTINATION SST_ILM_STRUCT_DESTINATION__enum,SST_ILM_STRUCT_DESTINATION_size

// SST_ILM_STRUCT_SAP
#define SST_ILM_STRUCT_SAP_size "d"
#define SST_ILM_STRUCT_SAP SST_ILM_STRUCT_SAP__enum,SST_ILM_STRUCT_SAP_size

// SST_ILM_STRUCT_MESSID
#define SST_ILM_STRUCT_MESSID_size "d"
#define SST_ILM_STRUCT_MESSID SST_ILM_STRUCT_MESSID__enum,SST_ILM_STRUCT_MESSID_size

// SST_ILM_STRUCT_LOCAL
#define SST_ILM_STRUCT_LOCAL_size "d"
#define SST_ILM_STRUCT_LOCAL SST_ILM_STRUCT_LOCAL__enum,SST_ILM_STRUCT_LOCAL_size

// SST_ILM_STRUCT_PEER
#define SST_ILM_STRUCT_PEER_size "d"
#define SST_ILM_STRUCT_PEER SST_ILM_STRUCT_PEER__enum,SST_ILM_STRUCT_PEER_size

// SST_INIT
#define SST_INIT_size ""
#define SST_INIT SST_INIT__enum,SST_INIT_size

// SST_PHASE1_201_01
#define SST_PHASE1_201_01_size ""
#define SST_PHASE1_201_01 SST_PHASE1_201_01__enum,SST_PHASE1_201_01_size

// SST_PHASE1_201_02
#define SST_PHASE1_201_02_size ""
#define SST_PHASE1_201_02 SST_PHASE1_201_02__enum,SST_PHASE1_201_02_size

// SST_PHASE1_201_04
#define SST_PHASE1_201_04_size ""
#define SST_PHASE1_201_04 SST_PHASE1_201_04__enum,SST_PHASE1_201_04_size

// SST_PHASE1_201_07
#define SST_PHASE1_201_07_size ""
#define SST_PHASE1_201_07 SST_PHASE1_201_07__enum,SST_PHASE1_201_07_size

// SST_PHASE1_203_01
#define SST_PHASE1_203_01_size ""
#define SST_PHASE1_203_01 SST_PHASE1_203_01__enum,SST_PHASE1_203_01_size

// SST_PHASE1_203_02
#define SST_PHASE1_203_02_size ""
#define SST_PHASE1_203_02 SST_PHASE1_203_02__enum,SST_PHASE1_203_02_size

// SST_PHASE1_203_22_
#define SST_PHASE1_203_22__size ""
#define SST_PHASE1_203_22_ SST_PHASE1_203_22___enum,SST_PHASE1_203_22__size

// SST_PHASE1_203_25_
#define SST_PHASE1_203_25__size ""
#define SST_PHASE1_203_25_ SST_PHASE1_203_25___enum,SST_PHASE1_203_25__size

// SST_PHASE1_207_TASKID_P1
#define SST_PHASE1_207_TASKID_P1_size ""
#define SST_PHASE1_207_TASKID_P1 SST_PHASE1_207_TASKID_P1__enum,SST_PHASE1_207_TASKID_P1_size

// SST_PHASE1_207_TASKID_P2
#define SST_PHASE1_207_TASKID_P2_size "dd"
#define SST_PHASE1_207_TASKID_P2 SST_PHASE1_207_TASKID_P2__enum,SST_PHASE1_207_TASKID_P2_size

// SST_PHASE1_211_01
#define SST_PHASE1_211_01_size ""
#define SST_PHASE1_211_01 SST_PHASE1_211_01__enum,SST_PHASE1_211_01_size

// SST_PHASE1_211_02
#define SST_PHASE1_211_02_size ""
#define SST_PHASE1_211_02 SST_PHASE1_211_02__enum,SST_PHASE1_211_02_size

// SST_PHASE1_211_04
#define SST_PHASE1_211_04_size ""
#define SST_PHASE1_211_04 SST_PHASE1_211_04__enum,SST_PHASE1_211_04_size

// SST_PHASE1_211_07
#define SST_PHASE1_211_07_size ""
#define SST_PHASE1_211_07 SST_PHASE1_211_07__enum,SST_PHASE1_211_07_size

// SST_PHASE1_213_01
#define SST_PHASE1_213_01_size ""
#define SST_PHASE1_213_01 SST_PHASE1_213_01__enum,SST_PHASE1_213_01_size

// SST_PHASE1_213_02
#define SST_PHASE1_213_02_size ""
#define SST_PHASE1_213_02 SST_PHASE1_213_02__enum,SST_PHASE1_213_02_size

// SST_PHASE1_213_03
#define SST_PHASE1_213_03_size ""
#define SST_PHASE1_213_03 SST_PHASE1_213_03__enum,SST_PHASE1_213_03_size

// SST_PHASE1_213_04
#define SST_PHASE1_213_04_size ""
#define SST_PHASE1_213_04 SST_PHASE1_213_04__enum,SST_PHASE1_213_04_size

// SST_PHASE1_213_05
#define SST_PHASE1_213_05_size "d"
#define SST_PHASE1_213_05 SST_PHASE1_213_05__enum,SST_PHASE1_213_05_size

// SST_PHASE1_216_9__P1
#define SST_PHASE1_216_9__P1_size ""
#define SST_PHASE1_216_9__P1 SST_PHASE1_216_9__P1__enum,SST_PHASE1_216_9__P1_size

// SST_PHASE2_203_01
#define SST_PHASE2_203_01_size ""
#define SST_PHASE2_203_01 SST_PHASE2_203_01__enum,SST_PHASE2_203_01_size

// SST_PHASE2_203_02
#define SST_PHASE2_203_02_size ""
#define SST_PHASE2_203_02 SST_PHASE2_203_02__enum,SST_PHASE2_203_02_size

// SST_PHASE2_207_TASKID_SUB1_P1
#define SST_PHASE2_207_TASKID_SUB1_P1_size ""
#define SST_PHASE2_207_TASKID_SUB1_P1 SST_PHASE2_207_TASKID_SUB1_P1__enum,SST_PHASE2_207_TASKID_SUB1_P1_size

// SST_PHASE2_207_TASKID_SUB1_P2
#define SST_PHASE2_207_TASKID_SUB1_P2_size ""
#define SST_PHASE2_207_TASKID_SUB1_P2 SST_PHASE2_207_TASKID_SUB1_P2__enum,SST_PHASE2_207_TASKID_SUB1_P2_size

// SST_PHASE2_207_TASKID_SUB2_P1
#define SST_PHASE2_207_TASKID_SUB2_P1_size "ccccccccd"
#define SST_PHASE2_207_TASKID_SUB2_P1 SST_PHASE2_207_TASKID_SUB2_P1__enum,SST_PHASE2_207_TASKID_SUB2_P1_size

// SST_PHASE2_207_TASKID_SUB2_P2
#define SST_PHASE2_207_TASKID_SUB2_P2_size "d"
#define SST_PHASE2_207_TASKID_SUB2_P2 SST_PHASE2_207_TASKID_SUB2_P2__enum,SST_PHASE2_207_TASKID_SUB2_P2_size

// SST_PHASE2_TASK_INFO_G_CORRUPTED_P1
#define SST_PHASE2_TASK_INFO_G_CORRUPTED_P1_size "d"
#define SST_PHASE2_TASK_INFO_G_CORRUPTED_P1 SST_PHASE2_TASK_INFO_G_CORRUPTED_P1__enum,SST_PHASE2_TASK_INFO_G_CORRUPTED_P1_size

// SST_PHASE2_TASK_INFO_G_CORRUPTED_P2
#define SST_PHASE2_TASK_INFO_G_CORRUPTED_P2_size ""
#define SST_PHASE2_TASK_INFO_G_CORRUPTED_P2 SST_PHASE2_TASK_INFO_G_CORRUPTED_P2__enum,SST_PHASE2_TASK_INFO_G_CORRUPTED_P2_size

// SST_PHASE2_216_9_1_P1
#define SST_PHASE2_216_9_1_P1_size ""
#define SST_PHASE2_216_9_1_P1 SST_PHASE2_216_9_1_P1__enum,SST_PHASE2_216_9_1_P1_size

// SST_PHASE2_216_9_1_P2
#define SST_PHASE2_216_9_1_P2_size ""
#define SST_PHASE2_216_9_1_P2 SST_PHASE2_216_9_1_P2__enum,SST_PHASE2_216_9_1_P2_size

// SST_PHASE2_216_9_2
#define SST_PHASE2_216_9_2_size ""
#define SST_PHASE2_216_9_2 SST_PHASE2_216_9_2__enum,SST_PHASE2_216_9_2_size

// SST_PHASE3_203_22__P1
#define SST_PHASE3_203_22__P1_size "ccccc"
#define SST_PHASE3_203_22__P1 SST_PHASE3_203_22__P1__enum,SST_PHASE3_203_22__P1_size

// SST_PHASE3_203_22__P2
#define SST_PHASE3_203_22__P2_size ""
#define SST_PHASE3_203_22__P2 SST_PHASE3_203_22__P2__enum,SST_PHASE3_203_22__P2_size

// SST_PHASE3_203_25__P1
#define SST_PHASE3_203_25__P1_size "ccccc"
#define SST_PHASE3_203_25__P1 SST_PHASE3_203_25__P1__enum,SST_PHASE3_203_25__P1_size

// SST_PHASE3_203_25__P2
#define SST_PHASE3_203_25__P2_size ""
#define SST_PHASE3_203_25__P2 SST_PHASE3_203_25__P2__enum,SST_PHASE3_203_25__P2_size

// SST_PHASE3_207_TASKID
#define SST_PHASE3_207_TASKID_size "d"
#define SST_PHASE3_207_TASKID SST_PHASE3_207_TASKID__enum,SST_PHASE3_207_TASKID_size

// SST_TC_HCB_CREATED
#define SST_TC_HCB_CREATED_size "d"
#define SST_TC_HCB_CREATED SST_TC_HCB_CREATED__enum,SST_TC_HCB_CREATED_size

// SST_TC_HCB_ID
#define SST_TC_HCB_ID_size "d"
#define SST_TC_HCB_ID SST_TC_HCB_ID__enum,SST_TC_HCB_ID_size

// SST_TC_HCB_NAME
#define SST_TC_HCB_NAME_size "cccccccc"
#define SST_TC_HCB_NAME SST_TC_HCB_NAME__enum,SST_TC_HCB_NAME_size

// SST_TC_HCB_PRIORITY
#define SST_TC_HCB_PRIORITY_size "d"
#define SST_TC_HCB_PRIORITY SST_TC_HCB_PRIORITY__enum,SST_TC_HCB_PRIORITY_size

// SST_TC_HCB_SCHEDULED
#define SST_TC_HCB_SCHEDULED_size "d"
#define SST_TC_HCB_SCHEDULED SST_TC_HCB_SCHEDULED__enum,SST_TC_HCB_SCHEDULED_size

// SST_TC_HCB_TIMESLICE
#define SST_TC_HCB_TIMESLICE_size "d"
#define SST_TC_HCB_TIMESLICE SST_TC_HCB_TIMESLICE__enum,SST_TC_HCB_TIMESLICE_size

// SST_TC_HCB_STACK_START
#define SST_TC_HCB_STACK_START_size "d"
#define SST_TC_HCB_STACK_START SST_TC_HCB_STACK_START__enum,SST_TC_HCB_STACK_START_size

// SST_TC_HCB_STACK_END
#define SST_TC_HCB_STACK_END_size "d"
#define SST_TC_HCB_STACK_END SST_TC_HCB_STACK_END__enum,SST_TC_HCB_STACK_END_size

// SST_TC_HCB_SP
#define SST_TC_HCB_SP_size "d"
#define SST_TC_HCB_SP SST_TC_HCB_SP__enum,SST_TC_HCB_SP_size

// SST_TC_HCB_STACK_SIZE
#define SST_TC_HCB_STACK_SIZE_size "d"
#define SST_TC_HCB_STACK_SIZE SST_TC_HCB_STACK_SIZE__enum,SST_TC_HCB_STACK_SIZE_size

// SST_TC_HCB_STACK_MIN
#define SST_TC_HCB_STACK_MIN_size "d"
#define SST_TC_HCB_STACK_MIN SST_TC_HCB_STACK_MIN__enum,SST_TC_HCB_STACK_MIN_size

// SST_TC_HCB_CURR_PROTECT
#define SST_TC_HCB_CURR_PROTECT_size "d"
#define SST_TC_HCB_CURR_PROTECT SST_TC_HCB_CURR_PROTECT__enum,SST_TC_HCB_CURR_PROTECT_size

// SST_TC_HCB_ACTIVE_NEXT
#define SST_TC_HCB_ACTIVE_NEXT_size "d"
#define SST_TC_HCB_ACTIVE_NEXT SST_TC_HCB_ACTIVE_NEXT__enum,SST_TC_HCB_ACTIVE_NEXT_size

// SST_TC_HCB_ACTIVATION
#define SST_TC_HCB_ACTIVATION_size "d"
#define SST_TC_HCB_ACTIVATION SST_TC_HCB_ACTIVATION__enum,SST_TC_HCB_ACTIVATION_size

// SST_TC_HCB_ENTRY
#define SST_TC_HCB_ENTRY_size "d"
#define SST_TC_HCB_ENTRY SST_TC_HCB_ENTRY__enum,SST_TC_HCB_ENTRY_size

// SST_TASK_READY
#define SST_TASK_READY_size "cccccccc"
#define SST_TASK_READY SST_TASK_READY__enum,SST_TASK_READY_size

// SST_TASK_PURE_SUSPEND
#define SST_TASK_PURE_SUSPEND_size "cccccccc"
#define SST_TASK_PURE_SUSPEND SST_TASK_PURE_SUSPEND__enum,SST_TASK_PURE_SUSPEND_size

// SST_TASK_SLEEP_SUSPEND
#define SST_TASK_SLEEP_SUSPEND_size "cccccccc"
#define SST_TASK_SLEEP_SUSPEND SST_TASK_SLEEP_SUSPEND__enum,SST_TASK_SLEEP_SUSPEND_size

// SST_TASK_QUEUE_SUSPEND
#define SST_TASK_QUEUE_SUSPEND_size "cccccccc"
#define SST_TASK_QUEUE_SUSPEND SST_TASK_QUEUE_SUSPEND__enum,SST_TASK_QUEUE_SUSPEND_size

// SST_TASK_SEMAPHORE_SUSPEND
#define SST_TASK_SEMAPHORE_SUSPEND_size "cccccccc"
#define SST_TASK_SEMAPHORE_SUSPEND SST_TASK_SEMAPHORE_SUSPEND__enum,SST_TASK_SEMAPHORE_SUSPEND_size

// SST_TASK_EVENT_SUSPEND
#define SST_TASK_EVENT_SUSPEND_size "cccccccc"
#define SST_TASK_EVENT_SUSPEND SST_TASK_EVENT_SUSPEND__enum,SST_TASK_EVENT_SUSPEND_size

// SST_TASK_PARTITION_SUSPEND
#define SST_TASK_PARTITION_SUSPEND_size "cccccccc"
#define SST_TASK_PARTITION_SUSPEND SST_TASK_PARTITION_SUSPEND__enum,SST_TASK_PARTITION_SUSPEND_size

// SST_TASK_FINISH
#define SST_TASK_FINISH_size "cccccccc"
#define SST_TASK_FINISH SST_TASK_FINISH__enum,SST_TASK_FINISH_size

// SST_TASK_TERMINATED
#define SST_TASK_TERMINATED_size "cccccccc"
#define SST_TASK_TERMINATED SST_TASK_TERMINATED__enum,SST_TASK_TERMINATED_size

// SST_TASK_UNKOWN
#define SST_TASK_UNKOWN_size "ccccccccd"
#define SST_TASK_UNKOWN SST_TASK_UNKOWN__enum,SST_TASK_UNKOWN_size

// SST_ITC_COMMON_ILM1
#define SST_ITC_COMMON_ILM1_size ""
#define SST_ITC_COMMON_ILM1 SST_ITC_COMMON_ILM1__enum,SST_ITC_COMMON_ILM1_size

// SST_ITC_COMMON_ILM2
#define SST_ITC_COMMON_ILM2_size "d"
#define SST_ITC_COMMON_ILM2 SST_ITC_COMMON_ILM2__enum,SST_ITC_COMMON_ILM2_size

// SST_PHASE1_301_01
#define SST_PHASE1_301_01_size ""
#define SST_PHASE1_301_01 SST_PHASE1_301_01__enum,SST_PHASE1_301_01_size

// SST_PHASE1_301_03
#define SST_PHASE1_301_03_size ""
#define SST_PHASE1_301_03 SST_PHASE1_301_03__enum,SST_PHASE1_301_03_size

// SST_PHASE1_301_04
#define SST_PHASE1_301_04_size ""
#define SST_PHASE1_301_04 SST_PHASE1_301_04__enum,SST_PHASE1_301_04_size

// SST_PHASE1_303_9999_P1
#define SST_PHASE1_303_9999_P1_size ""
#define SST_PHASE1_303_9999_P1 SST_PHASE1_303_9999_P1__enum,SST_PHASE1_303_9999_P1_size

// SST_PHASE1_303_6666_P1
#define SST_PHASE1_303_6666_P1_size ""
#define SST_PHASE1_303_6666_P1 SST_PHASE1_303_6666_P1__enum,SST_PHASE1_303_6666_P1_size

// SST_PHASE1_305_01
#define SST_PHASE1_305_01_size ""
#define SST_PHASE1_305_01 SST_PHASE1_305_01__enum,SST_PHASE1_305_01_size

// SST_PHASE1_305_02
#define SST_PHASE1_305_02_size ""
#define SST_PHASE1_305_02 SST_PHASE1_305_02__enum,SST_PHASE1_305_02_size

// SST_PHASE1_305_19__P1
#define SST_PHASE1_305_19__P1_size ""
#define SST_PHASE1_305_19__P1 SST_PHASE1_305_19__P1__enum,SST_PHASE1_305_19__P1_size

// SST_PHASE1_305_19__P2
#define SST_PHASE1_305_19__P2_size ""
#define SST_PHASE1_305_19__P2 SST_PHASE1_305_19__P2__enum,SST_PHASE1_305_19__P2_size

// SST_PHASE1_305_24_
#define SST_PHASE1_305_24__size ""
#define SST_PHASE1_305_24_ SST_PHASE1_305_24___enum,SST_PHASE1_305_24__size

// SST_PHASE1_305_8888
#define SST_PHASE1_305_8888_size ""
#define SST_PHASE1_305_8888 SST_PHASE1_305_8888__enum,SST_PHASE1_305_8888_size

// SST_PHASE1_305_7777
#define SST_PHASE1_305_7777_size ""
#define SST_PHASE1_305_7777 SST_PHASE1_305_7777__enum,SST_PHASE1_305_7777_size

// SST_PHASE1_305_FF
#define SST_PHASE1_305_FF_size ""
#define SST_PHASE1_305_FF SST_PHASE1_305_FF__enum,SST_PHASE1_305_FF_size

// SST_PHASE1_307_0
#define SST_PHASE1_307_0_size ""
#define SST_PHASE1_307_0 SST_PHASE1_307_0__enum,SST_PHASE1_307_0_size

// SST_PHASE1_307_1
#define SST_PHASE1_307_1_size ""
#define SST_PHASE1_307_1 SST_PHASE1_307_1__enum,SST_PHASE1_307_1_size

// SST_PHASE1_307_19_
#define SST_PHASE1_307_19__size ""
#define SST_PHASE1_307_19_ SST_PHASE1_307_19___enum,SST_PHASE1_307_19__size

// SST_PHASE1_307_24_
#define SST_PHASE1_307_24__size ""
#define SST_PHASE1_307_24_ SST_PHASE1_307_24___enum,SST_PHASE1_307_24__size

// SST_PHASE1_401_1
#define SST_PHASE1_401_1_size ""
#define SST_PHASE1_401_1 SST_PHASE1_401_1__enum,SST_PHASE1_401_1_size

// SST_PHASE1_401_4
#define SST_PHASE1_401_4_size ""
#define SST_PHASE1_401_4 SST_PHASE1_401_4__enum,SST_PHASE1_401_4_size

// SST_PHASE1_403_FF
#define SST_PHASE1_403_FF_size ""
#define SST_PHASE1_403_FF SST_PHASE1_403_FF__enum,SST_PHASE1_403_FF_size

// SST_PHASE1_404_1
#define SST_PHASE1_404_1_size ""
#define SST_PHASE1_404_1 SST_PHASE1_404_1__enum,SST_PHASE1_404_1_size

// SST_PHASE1_404_21_
#define SST_PHASE1_404_21__size ""
#define SST_PHASE1_404_21_ SST_PHASE1_404_21___enum,SST_PHASE1_404_21__size

// SST_PHASE1_404_24_
#define SST_PHASE1_404_24__size ""
#define SST_PHASE1_404_24_ SST_PHASE1_404_24___enum,SST_PHASE1_404_24__size

// SST_PHASE1_405_0
#define SST_PHASE1_405_0_size ""
#define SST_PHASE1_405_0 SST_PHASE1_405_0__enum,SST_PHASE1_405_0_size

// SST_PHASE1_405_MUID
#define SST_PHASE1_405_MUID_size ""
#define SST_PHASE1_405_MUID SST_PHASE1_405_MUID__enum,SST_PHASE1_405_MUID_size

// SST_PHASE1_405_FF
#define SST_PHASE1_405_FF_size ""
#define SST_PHASE1_405_FF SST_PHASE1_405_FF__enum,SST_PHASE1_405_FF_size

// SST_PHASE1_411_1
#define SST_PHASE1_411_1_size ""
#define SST_PHASE1_411_1 SST_PHASE1_411_1__enum,SST_PHASE1_411_1_size

// SST_PHASE1_411_4
#define SST_PHASE1_411_4_size ""
#define SST_PHASE1_411_4 SST_PHASE1_411_4__enum,SST_PHASE1_411_4_size

// SST_PHASE1_413_FF
#define SST_PHASE1_413_FF_size ""
#define SST_PHASE1_413_FF SST_PHASE1_413_FF__enum,SST_PHASE1_413_FF_size

// SST_PHASE1_414_0
#define SST_PHASE1_414_0_size ""
#define SST_PHASE1_414_0 SST_PHASE1_414_0__enum,SST_PHASE1_414_0_size

// SST_PHASE1_414_21_
#define SST_PHASE1_414_21__size ""
#define SST_PHASE1_414_21_ SST_PHASE1_414_21___enum,SST_PHASE1_414_21__size

// SST_PHASE1_414_24_
#define SST_PHASE1_414_24__size ""
#define SST_PHASE1_414_24_ SST_PHASE1_414_24___enum,SST_PHASE1_414_24__size

// SST_PHASE1_415_0
#define SST_PHASE1_415_0_size ""
#define SST_PHASE1_415_0 SST_PHASE1_415_0__enum,SST_PHASE1_415_0_size

// SST_PHASE1_415_FF
#define SST_PHASE1_415_FF_size ""
#define SST_PHASE1_415_FF SST_PHASE1_415_FF__enum,SST_PHASE1_415_FF_size

// SST_PHASE1_421_1
#define SST_PHASE1_421_1_size ""
#define SST_PHASE1_421_1 SST_PHASE1_421_1__enum,SST_PHASE1_421_1_size

// SST_PHASE1_423_FF
#define SST_PHASE1_423_FF_size ""
#define SST_PHASE1_423_FF SST_PHASE1_423_FF__enum,SST_PHASE1_423_FF_size

// SST_PHASE1_424_21_
#define SST_PHASE1_424_21__size ""
#define SST_PHASE1_424_21_ SST_PHASE1_424_21___enum,SST_PHASE1_424_21__size

// SST_PHASE1_424_13_
#define SST_PHASE1_424_13__size ""
#define SST_PHASE1_424_13_ SST_PHASE1_424_13___enum,SST_PHASE1_424_13__size

// SST_PHASE1_425_13_
#define SST_PHASE1_425_13__size ""
#define SST_PHASE1_425_13_ SST_PHASE1_425_13___enum,SST_PHASE1_425_13__size

// SST_PHASE1_425_24_
#define SST_PHASE1_425_24__size ""
#define SST_PHASE1_425_24_ SST_PHASE1_425_24___enum,SST_PHASE1_425_24__size

// SST_PHASE1_431
#define SST_PHASE1_431_size "d"
#define SST_PHASE1_431 SST_PHASE1_431__enum,SST_PHASE1_431_size

// SST_PHASE1_432
#define SST_PHASE1_432_size "cccccccc"
#define SST_PHASE1_432 SST_PHASE1_432__enum,SST_PHASE1_432_size

// SST_PHASE1_441
#define SST_PHASE1_441_size "d"
#define SST_PHASE1_441 SST_PHASE1_441__enum,SST_PHASE1_441_size

// SST_PHASE2_303_9999_P1
#define SST_PHASE2_303_9999_P1_size "cccccccc"
#define SST_PHASE2_303_9999_P1 SST_PHASE2_303_9999_P1__enum,SST_PHASE2_303_9999_P1_size

// SST_PHASE2_303_9999_P2
#define SST_PHASE2_303_9999_P2_size "dd"
#define SST_PHASE2_303_9999_P2 SST_PHASE2_303_9999_P2__enum,SST_PHASE2_303_9999_P2_size

// SST_PHASE2_303_9999_P3
#define SST_PHASE2_303_9999_P3_size "cccccccc"
#define SST_PHASE2_303_9999_P3 SST_PHASE2_303_9999_P3__enum,SST_PHASE2_303_9999_P3_size

// SST_PHASE2_303_9999_P4
#define SST_PHASE2_303_9999_P4_size ""
#define SST_PHASE2_303_9999_P4 SST_PHASE2_303_9999_P4__enum,SST_PHASE2_303_9999_P4_size

// SST_PHASE2_303_9999_P5
#define SST_PHASE2_303_9999_P5_size "cccccccc"
#define SST_PHASE2_303_9999_P5 SST_PHASE2_303_9999_P5__enum,SST_PHASE2_303_9999_P5_size

// SST_PHASE2_303_9999_P6
#define SST_PHASE2_303_9999_P6_size ""
#define SST_PHASE2_303_9999_P6 SST_PHASE2_303_9999_P6__enum,SST_PHASE2_303_9999_P6_size

// SST_PHASE2_303_QUEUE_ID
#define SST_PHASE2_303_QUEUE_ID_size ""
#define SST_PHASE2_303_QUEUE_ID SST_PHASE2_303_QUEUE_ID__enum,SST_PHASE2_303_QUEUE_ID_size

// SST_PHASE2_303_8888_P1
#define SST_PHASE2_303_8888_P1_size "cccccccccccccccc"
#define SST_PHASE2_303_8888_P1 SST_PHASE2_303_8888_P1__enum,SST_PHASE2_303_8888_P1_size

// SST_PHASE2_303_8888_P2
#define SST_PHASE2_303_8888_P2_size "cccccccc"
#define SST_PHASE2_303_8888_P2 SST_PHASE2_303_8888_P2__enum,SST_PHASE2_303_8888_P2_size

// SST_PHASE2_303_8888_P3
#define SST_PHASE2_303_8888_P3_size ""
#define SST_PHASE2_303_8888_P3 SST_PHASE2_303_8888_P3__enum,SST_PHASE2_303_8888_P3_size

// SST_PHASE2_303_8888_P4
#define SST_PHASE2_303_8888_P4_size "cccccccc"
#define SST_PHASE2_303_8888_P4 SST_PHASE2_303_8888_P4__enum,SST_PHASE2_303_8888_P4_size

// SST_PHASE2_303_8888_P5
#define SST_PHASE2_303_8888_P5_size ""
#define SST_PHASE2_303_8888_P5 SST_PHASE2_303_8888_P5__enum,SST_PHASE2_303_8888_P5_size

// SST_PHASE2_303_8888_P6
#define SST_PHASE2_303_8888_P6_size "cccccccc"
#define SST_PHASE2_303_8888_P6 SST_PHASE2_303_8888_P6__enum,SST_PHASE2_303_8888_P6_size

// SST_PHASE2_QUEUE_MESS_COUNT
#define SST_PHASE2_QUEUE_MESS_COUNT_size "d"
#define SST_PHASE2_QUEUE_MESS_COUNT SST_PHASE2_QUEUE_MESS_COUNT__enum,SST_PHASE2_QUEUE_MESS_COUNT_size

// SST_PHASE2_303_7777_P1
#define SST_PHASE2_303_7777_P1_size "ccccccccdd"
#define SST_PHASE2_303_7777_P1 SST_PHASE2_303_7777_P1__enum,SST_PHASE2_303_7777_P1_size

// SST_PHASE2_405_MUID
#define SST_PHASE2_405_MUID_size "cccccccccccccccc"
#define SST_PHASE2_405_MUID SST_PHASE2_405_MUID__enum,SST_PHASE2_405_MUID_size

// SST_QU_QCB
#define SST_QU_QCB_size ""
#define SST_QU_QCB SST_QU_QCB__enum,SST_QU_QCB_size

// SST_QU_QCB_CREATED
#define SST_QU_QCB_CREATED_size "d"
#define SST_QU_QCB_CREATED SST_QU_QCB_CREATED__enum,SST_QU_QCB_CREATED_size

// SST_QU_QCB_ID
#define SST_QU_QCB_ID_size "d"
#define SST_QU_QCB_ID SST_QU_QCB_ID__enum,SST_QU_QCB_ID_size

// SST_QU_QCB_NAME
#define SST_QU_QCB_NAME_size "cccccccc"
#define SST_QU_QCB_NAME SST_QU_QCB_NAME__enum,SST_QU_QCB_NAME_size

// SST_QU_QCB_FIXED_SIZE
#define SST_QU_QCB_FIXED_SIZE_size "d"
#define SST_QU_QCB_FIXED_SIZE SST_QU_QCB_FIXED_SIZE__enum,SST_QU_QCB_FIXED_SIZE_size

// SST_QU_QCB_SUSP_F
#define SST_QU_QCB_SUSP_F_size "d"
#define SST_QU_QCB_SUSP_F SST_QU_QCB_SUSP_F__enum,SST_QU_QCB_SUSP_F_size

// SST_QU_QCB_SIZE
#define SST_QU_QCB_SIZE_size "d"
#define SST_QU_QCB_SIZE SST_QU_QCB_SIZE__enum,SST_QU_QCB_SIZE_size

// SST_QU_QCB_MESS_COUNT
#define SST_QU_QCB_MESS_COUNT_size "d"
#define SST_QU_QCB_MESS_COUNT SST_QU_QCB_MESS_COUNT__enum,SST_QU_QCB_MESS_COUNT_size

// SST_QU_QCB_MESS_SIZE
#define SST_QU_QCB_MESS_SIZE_size "d"
#define SST_QU_QCB_MESS_SIZE SST_QU_QCB_MESS_SIZE__enum,SST_QU_QCB_MESS_SIZE_size

// SST_QU_QCB_AVAIL
#define SST_QU_QCB_AVAIL_size "d"
#define SST_QU_QCB_AVAIL SST_QU_QCB_AVAIL__enum,SST_QU_QCB_AVAIL_size

// SST_QU_QCB_START_ADDR
#define SST_QU_QCB_START_ADDR_size "d"
#define SST_QU_QCB_START_ADDR SST_QU_QCB_START_ADDR__enum,SST_QU_QCB_START_ADDR_size

// SST_QU_QCB_END_ADDR
#define SST_QU_QCB_END_ADDR_size "d"
#define SST_QU_QCB_END_ADDR SST_QU_QCB_END_ADDR__enum,SST_QU_QCB_END_ADDR_size

// SST_QU_QCB_READ_PTR
#define SST_QU_QCB_READ_PTR_size "d"
#define SST_QU_QCB_READ_PTR SST_QU_QCB_READ_PTR__enum,SST_QU_QCB_READ_PTR_size

// SST_QU_QCB_WRITE_PTR
#define SST_QU_QCB_WRITE_PTR_size "d"
#define SST_QU_QCB_WRITE_PTR SST_QU_QCB_WRITE_PTR__enum,SST_QU_QCB_WRITE_PTR_size

// SST_QU_QCB_TASK_WAITING
#define SST_QU_QCB_TASK_WAITING_size "d"
#define SST_QU_QCB_TASK_WAITING SST_QU_QCB_TASK_WAITING__enum,SST_QU_QCB_TASK_WAITING_size

// SST_QU_QCB_URGENT_LIST
#define SST_QU_QCB_URGENT_LIST_size "d"
#define SST_QU_QCB_URGENT_LIST SST_QU_QCB_URGENT_LIST__enum,SST_QU_QCB_URGENT_LIST_size

// SST_QU_QCB_SUSP_LIST
#define SST_QU_QCB_SUSP_LIST_size "d"
#define SST_QU_QCB_SUSP_LIST SST_QU_QCB_SUSP_LIST__enum,SST_QU_QCB_SUSP_LIST_size

// SST_SM_SCB
#define SST_SM_SCB_size ""
#define SST_SM_SCB SST_SM_SCB__enum,SST_SM_SCB_size

// SST_SM_SCB_CREATED
#define SST_SM_SCB_CREATED_size "d"
#define SST_SM_SCB_CREATED SST_SM_SCB_CREATED__enum,SST_SM_SCB_CREATED_size

// SST_SM_SCB_ID
#define SST_SM_SCB_ID_size "d"
#define SST_SM_SCB_ID SST_SM_SCB_ID__enum,SST_SM_SCB_ID_size

// SST_SM_SCB_NAME
#define SST_SM_SCB_NAME_size "cccccccc"
#define SST_SM_SCB_NAME SST_SM_SCB_NAME__enum,SST_SM_SCB_NAME_size

// SST_SM_SCB_COUNT
#define SST_SM_SCB_COUNT_size "d"
#define SST_SM_SCB_COUNT SST_SM_SCB_COUNT__enum,SST_SM_SCB_COUNT_size

// SST_SM_SCB_FIFO_SUS
#define SST_SM_SCB_FIFO_SUS_size "d"
#define SST_SM_SCB_FIFO_SUS SST_SM_SCB_FIFO_SUS__enum,SST_SM_SCB_FIFO_SUS_size

// SST_SM_SCB_TASKS_WAIT
#define SST_SM_SCB_TASKS_WAIT_size "d"
#define SST_SM_SCB_TASKS_WAIT SST_SM_SCB_TASKS_WAIT__enum,SST_SM_SCB_TASKS_WAIT_size

// SST_SM_SCB_SUSP_LIST
#define SST_SM_SCB_SUSP_LIST_size "d"
#define SST_SM_SCB_SUSP_LIST SST_SM_SCB_SUSP_LIST__enum,SST_SM_SCB_SUSP_LIST_size

// SST_EV_GCB
#define SST_EV_GCB_size ""
#define SST_EV_GCB SST_EV_GCB__enum,SST_EV_GCB_size

// SST_EV_GCB_CREATED
#define SST_EV_GCB_CREATED_size "d"
#define SST_EV_GCB_CREATED SST_EV_GCB_CREATED__enum,SST_EV_GCB_CREATED_size

// SST_EV_GCB_ID
#define SST_EV_GCB_ID_size "d"
#define SST_EV_GCB_ID SST_EV_GCB_ID__enum,SST_EV_GCB_ID_size

// SST_EV_GCB_NAME
#define SST_EV_GCB_NAME_size "cccccccc"
#define SST_EV_GCB_NAME SST_EV_GCB_NAME__enum,SST_EV_GCB_NAME_size

// SST_EV_GCB_CUR_EVENTS
#define SST_EV_GCB_CUR_EVENTS_size "d"
#define SST_EV_GCB_CUR_EVENTS SST_EV_GCB_CUR_EVENTS__enum,SST_EV_GCB_CUR_EVENTS_size

// SST_EV_GCB_TASKS_WAIT
#define SST_EV_GCB_TASKS_WAIT_size "d"
#define SST_EV_GCB_TASKS_WAIT SST_EV_GCB_TASKS_WAIT__enum,SST_EV_GCB_TASKS_WAIT_size

// SST_EV_GCB_SUSP_LIST
#define SST_EV_GCB_SUSP_LIST_size "d"
#define SST_EV_GCB_SUSP_LIST SST_EV_GCB_SUSP_LIST__enum,SST_EV_GCB_SUSP_LIST_size

// SST_PHASE2_SYSTEM_MEMORY
#define SST_PHASE2_SYSTEM_MEMORY_size "d"
#define SST_PHASE2_SYSTEM_MEMORY SST_PHASE2_SYSTEM_MEMORY__enum,SST_PHASE2_SYSTEM_MEMORY_size

// SST_PHASE2_INTERNAL_SYSTEM_MEMORY
#define SST_PHASE2_INTERNAL_SYSTEM_MEMORY_size "d"
#define SST_PHASE2_INTERNAL_SYSTEM_MEMORY SST_PHASE2_INTERNAL_SYSTEM_MEMORY__enum,SST_PHASE2_INTERNAL_SYSTEM_MEMORY_size

// SST_PHASE2_DEBUG__MEMORY
#define SST_PHASE2_DEBUG__MEMORY_size "d"
#define SST_PHASE2_DEBUG__MEMORY SST_PHASE2_DEBUG__MEMORY__enum,SST_PHASE2_DEBUG__MEMORY_size

// SST_PHASE3_INSUFFICEINT__MEMORY
#define SST_PHASE3_INSUFFICEINT__MEMORY_size "d"
#define SST_PHASE3_INSUFFICEINT__MEMORY SST_PHASE3_INSUFFICEINT__MEMORY__enum,SST_PHASE3_INSUFFICEINT__MEMORY_size

// SST_PHASE1_800_01
#define SST_PHASE1_800_01_size ""
#define SST_PHASE1_800_01 SST_PHASE1_800_01__enum,SST_PHASE1_800_01_size

// SST_PHASE1_800_02
#define SST_PHASE1_800_02_size ""
#define SST_PHASE1_800_02 SST_PHASE1_800_02__enum,SST_PHASE1_800_02_size

// SST_PHASE1_800_03
#define SST_PHASE1_800_03_size ""
#define SST_PHASE1_800_03 SST_PHASE1_800_03__enum,SST_PHASE1_800_03_size

// SST_PHASE1_801_01
#define SST_PHASE1_801_01_size ""
#define SST_PHASE1_801_01 SST_PHASE1_801_01__enum,SST_PHASE1_801_01_size

// SST_PHASE1_801_02
#define SST_PHASE1_801_02_size ""
#define SST_PHASE1_801_02 SST_PHASE1_801_02__enum,SST_PHASE1_801_02_size

// SST_PHASE1_801_03
#define SST_PHASE1_801_03_size ""
#define SST_PHASE1_801_03 SST_PHASE1_801_03__enum,SST_PHASE1_801_03_size

// SST_PHASE1_801_04
#define SST_PHASE1_801_04_size ""
#define SST_PHASE1_801_04 SST_PHASE1_801_04__enum,SST_PHASE1_801_04_size

// SST_PHASE1_801_08
#define SST_PHASE1_801_08_size ""
#define SST_PHASE1_801_08 SST_PHASE1_801_08__enum,SST_PHASE1_801_08_size

// SST_PHASE1_820_01
#define SST_PHASE1_820_01_size ""
#define SST_PHASE1_820_01 SST_PHASE1_820_01__enum,SST_PHASE1_820_01_size

// SST_PHASE1_820_02
#define SST_PHASE1_820_02_size ""
#define SST_PHASE1_820_02 SST_PHASE1_820_02__enum,SST_PHASE1_820_02_size

// SST_PHASE1_821_SIZE
#define SST_PHASE1_821_SIZE_size ""
#define SST_PHASE1_821_SIZE SST_PHASE1_821_SIZE__enum,SST_PHASE1_821_SIZE_size

// SST_PHASE1_822_SIZE
#define SST_PHASE1_822_SIZE_size ""
#define SST_PHASE1_822_SIZE SST_PHASE1_822_SIZE__enum,SST_PHASE1_822_SIZE_size

// SST_PHASE1_823_SIZE
#define SST_PHASE1_823_SIZE_size ""
#define SST_PHASE1_823_SIZE SST_PHASE1_823_SIZE__enum,SST_PHASE1_823_SIZE_size

// SST_PHASE1_830_01
#define SST_PHASE1_830_01_size ""
#define SST_PHASE1_830_01 SST_PHASE1_830_01__enum,SST_PHASE1_830_01_size

// SST_PHASE1_840_PTR_P1
#define SST_PHASE1_840_PTR_P1_size ""
#define SST_PHASE1_840_PTR_P1 SST_PHASE1_840_PTR_P1__enum,SST_PHASE1_840_PTR_P1_size

// SST_PHASE1_841_PTR
#define SST_PHASE1_841_PTR_size ""
#define SST_PHASE1_841_PTR SST_PHASE1_841_PTR__enum,SST_PHASE1_841_PTR_size

// SST_PHASE1_842_PTR_P1
#define SST_PHASE1_842_PTR_P1_size ""
#define SST_PHASE1_842_PTR_P1 SST_PHASE1_842_PTR_P1__enum,SST_PHASE1_842_PTR_P1_size

// SST_PHASE1_842_PTR_P2
#define SST_PHASE1_842_PTR_P2_size ""
#define SST_PHASE1_842_PTR_P2 SST_PHASE1_842_PTR_P2__enum,SST_PHASE1_842_PTR_P2_size

// SST_PHASE1_843_PTR_P1
#define SST_PHASE1_843_PTR_P1_size ""
#define SST_PHASE1_843_PTR_P1 SST_PHASE1_843_PTR_P1__enum,SST_PHASE1_843_PTR_P1_size

// SST_PHASE1_843_PTR_P2
#define SST_PHASE1_843_PTR_P2_size ""
#define SST_PHASE1_843_PTR_P2 SST_PHASE1_843_PTR_P2__enum,SST_PHASE1_843_PTR_P2_size

// SST_PHASE1_844_PTR_P1
#define SST_PHASE1_844_PTR_P1_size ""
#define SST_PHASE1_844_PTR_P1 SST_PHASE1_844_PTR_P1__enum,SST_PHASE1_844_PTR_P1_size

// SST_PHASE1_844_PTR_P2
#define SST_PHASE1_844_PTR_P2_size ""
#define SST_PHASE1_844_PTR_P2 SST_PHASE1_844_PTR_P2__enum,SST_PHASE1_844_PTR_P2_size

// SST_PHASE1_852_01
#define SST_PHASE1_852_01_size "cccccccc"
#define SST_PHASE1_852_01 SST_PHASE1_852_01__enum,SST_PHASE1_852_01_size

// SST_PHASE1_853_01
#define SST_PHASE1_853_01_size "cccccccc"
#define SST_PHASE1_853_01 SST_PHASE1_853_01__enum,SST_PHASE1_853_01_size

// SST_PHASE1_880_PTR_P1
#define SST_PHASE1_880_PTR_P1_size ""
#define SST_PHASE1_880_PTR_P1 SST_PHASE1_880_PTR_P1__enum,SST_PHASE1_880_PTR_P1_size

// SST_PHASE1_880_PTR_P2
#define SST_PHASE1_880_PTR_P2_size ""
#define SST_PHASE1_880_PTR_P2 SST_PHASE1_880_PTR_P2__enum,SST_PHASE1_880_PTR_P2_size

// SST_PHASE1_890_01
#define SST_PHASE1_890_01_size ""
#define SST_PHASE1_890_01 SST_PHASE1_890_01__enum,SST_PHASE1_890_01_size

// SST_PHASE1_892_01
#define SST_PHASE1_892_01_size ""
#define SST_PHASE1_892_01 SST_PHASE1_892_01__enum,SST_PHASE1_892_01_size

// SST_PHASE1_893_PTR
#define SST_PHASE1_893_PTR_size ""
#define SST_PHASE1_893_PTR SST_PHASE1_893_PTR__enum,SST_PHASE1_893_PTR_size

// SST_PHASE2_BUFF_UNKNOWN
#define SST_PHASE2_BUFF_UNKNOWN_size ""
#define SST_PHASE2_BUFF_UNKNOWN SST_PHASE2_BUFF_UNKNOWN__enum,SST_PHASE2_BUFF_UNKNOWN_size

// SST_PHASE2_NOT_MONITOR
#define SST_PHASE2_NOT_MONITOR_size ""
#define SST_PHASE2_NOT_MONITOR SST_PHASE2_NOT_MONITOR__enum,SST_PHASE2_NOT_MONITOR_size

// SST_PHASE2_NOT_ALIGNMENT
#define SST_PHASE2_NOT_ALIGNMENT_size "d"
#define SST_PHASE2_NOT_ALIGNMENT SST_PHASE2_NOT_ALIGNMENT__enum,SST_PHASE2_NOT_ALIGNMENT_size

// SST_PHASE2_INVALID_POINTER
#define SST_PHASE2_INVALID_POINTER_size "d"
#define SST_PHASE2_INVALID_POINTER SST_PHASE2_INVALID_POINTER__enum,SST_PHASE2_INVALID_POINTER_size

// SST_PHASE2_POOL_INFO_G_CORRUPTED
#define SST_PHASE2_POOL_INFO_G_CORRUPTED_size ""
#define SST_PHASE2_POOL_INFO_G_CORRUPTED SST_PHASE2_POOL_INFO_G_CORRUPTED__enum,SST_PHASE2_POOL_INFO_G_CORRUPTED_size

// SST_PHASE2_BUFFER_CORRUPT_REASONS
#define SST_PHASE2_BUFFER_CORRUPT_REASONS_size ""
#define SST_PHASE2_BUFFER_CORRUPT_REASONS SST_PHASE2_BUFFER_CORRUPT_REASONS__enum,SST_PHASE2_BUFFER_CORRUPT_REASONS_size

// SST_PHASE2_800_OVERFLOW
#define SST_PHASE2_800_OVERFLOW_size ""
#define SST_PHASE2_800_OVERFLOW SST_PHASE2_800_OVERFLOW__enum,SST_PHASE2_800_OVERFLOW_size

// SST_PHASE2_823_SIZE_NOT_MONITOR_P1
#define SST_PHASE2_823_SIZE_NOT_MONITOR_P1_size "d"
#define SST_PHASE2_823_SIZE_NOT_MONITOR_P1 SST_PHASE2_823_SIZE_NOT_MONITOR_P1__enum,SST_PHASE2_823_SIZE_NOT_MONITOR_P1_size

// SST_PHASE2_823_SIZE_NOT_MONITOR_P2
#define SST_PHASE2_823_SIZE_NOT_MONITOR_P2_size ""
#define SST_PHASE2_823_SIZE_NOT_MONITOR_P2 SST_PHASE2_823_SIZE_NOT_MONITOR_P2__enum,SST_PHASE2_823_SIZE_NOT_MONITOR_P2_size

// SST_PHASE2_823_SIZE_MONITOR_P1
#define SST_PHASE2_823_SIZE_MONITOR_P1_size "dd"
#define SST_PHASE2_823_SIZE_MONITOR_P1 SST_PHASE2_823_SIZE_MONITOR_P1__enum,SST_PHASE2_823_SIZE_MONITOR_P1_size

// SST_PHASE2_823_SIZE_MONITOR_P2
#define SST_PHASE2_823_SIZE_MONITOR_P2_size ""
#define SST_PHASE2_823_SIZE_MONITOR_P2 SST_PHASE2_823_SIZE_MONITOR_P2__enum,SST_PHASE2_823_SIZE_MONITOR_P2_size

// SST_PHASE2_823_SIZE_MONITOR_P3
#define SST_PHASE2_823_SIZE_MONITOR_P3_size "ccccccccdccccccccccccccccd"
#define SST_PHASE2_823_SIZE_MONITOR_P3 SST_PHASE2_823_SIZE_MONITOR_P3__enum,SST_PHASE2_823_SIZE_MONITOR_P3_size

// SST_PHASE2_823_SIZE_MONITOR_P4
#define SST_PHASE2_823_SIZE_MONITOR_P4_size "dd"
#define SST_PHASE2_823_SIZE_MONITOR_P4 SST_PHASE2_823_SIZE_MONITOR_P4__enum,SST_PHASE2_823_SIZE_MONITOR_P4_size

// SST_PHASE2_840_PTR
#define SST_PHASE2_840_PTR_size ""
#define SST_PHASE2_840_PTR SST_PHASE2_840_PTR__enum,SST_PHASE2_840_PTR_size

// SST_PHASE2_841_PTR
#define SST_PHASE2_841_PTR_size ""
#define SST_PHASE2_841_PTR SST_PHASE2_841_PTR__enum,SST_PHASE2_841_PTR_size

// SST_PHASE2_844_PTR
#define SST_PHASE2_844_PTR_size ""
#define SST_PHASE2_844_PTR SST_PHASE2_844_PTR__enum,SST_PHASE2_844_PTR_size

// SST_PHASE2_880_PTR
#define SST_PHASE2_880_PTR_size ""
#define SST_PHASE2_880_PTR SST_PHASE2_880_PTR__enum,SST_PHASE2_880_PTR_size

// SST_PHASE2_893_PTR_MONITOR_P1
#define SST_PHASE2_893_PTR_MONITOR_P1_size "ccccccccddcccccccccccc"
#define SST_PHASE2_893_PTR_MONITOR_P1 SST_PHASE2_893_PTR_MONITOR_P1__enum,SST_PHASE2_893_PTR_MONITOR_P1_size

// SST_PHASE2_893_PTR_MONITOR_P2
#define SST_PHASE2_893_PTR_MONITOR_P2_size "d"
#define SST_PHASE2_893_PTR_MONITOR_P2 SST_PHASE2_893_PTR_MONITOR_P2__enum,SST_PHASE2_893_PTR_MONITOR_P2_size

// SST_PHASE2_893_PTR_MONITOR_P3
#define SST_PHASE2_893_PTR_MONITOR_P3_size ""
#define SST_PHASE2_893_PTR_MONITOR_P3 SST_PHASE2_893_PTR_MONITOR_P3__enum,SST_PHASE2_893_PTR_MONITOR_P3_size

// SST_PHASE2_893_PTR_UNMONITOR_P1
#define SST_PHASE2_893_PTR_UNMONITOR_P1_size "ccccccccdd"
#define SST_PHASE2_893_PTR_UNMONITOR_P1 SST_PHASE2_893_PTR_UNMONITOR_P1__enum,SST_PHASE2_893_PTR_UNMONITOR_P1_size

// SST_PHASE2_893_PTR_UNMONITOR_P2
#define SST_PHASE2_893_PTR_UNMONITOR_P2_size ""
#define SST_PHASE2_893_PTR_UNMONITOR_P2 SST_PHASE2_893_PTR_UNMONITOR_P2__enum,SST_PHASE2_893_PTR_UNMONITOR_P2_size

// SST_PHASE3_823_SIZE_NOT_MONITOR_P1
#define SST_PHASE3_823_SIZE_NOT_MONITOR_P1_size ""
#define SST_PHASE3_823_SIZE_NOT_MONITOR_P1 SST_PHASE3_823_SIZE_NOT_MONITOR_P1__enum,SST_PHASE3_823_SIZE_NOT_MONITOR_P1_size

// SST_PHASE3_823_SIZE_NOT_MONITOR_P2
#define SST_PHASE3_823_SIZE_NOT_MONITOR_P2_size ""
#define SST_PHASE3_823_SIZE_NOT_MONITOR_P2 SST_PHASE3_823_SIZE_NOT_MONITOR_P2__enum,SST_PHASE3_823_SIZE_NOT_MONITOR_P2_size

// SST_PHASE3_823_SIZE_NOT_MONITOR_P3
#define SST_PHASE3_823_SIZE_NOT_MONITOR_P3_size ""
#define SST_PHASE3_823_SIZE_NOT_MONITOR_P3 SST_PHASE3_823_SIZE_NOT_MONITOR_P3__enum,SST_PHASE3_823_SIZE_NOT_MONITOR_P3_size

// SST_PHASE3_823_SIZE_NOT_MONITOR_P4
#define SST_PHASE3_823_SIZE_NOT_MONITOR_P4_size ""
#define SST_PHASE3_823_SIZE_NOT_MONITOR_P4 SST_PHASE3_823_SIZE_NOT_MONITOR_P4__enum,SST_PHASE3_823_SIZE_NOT_MONITOR_P4_size

// SST_PM_PCB
#define SST_PM_PCB_size ""
#define SST_PM_PCB SST_PM_PCB__enum,SST_PM_PCB_size

// SST_PM_PCB_CREATED
#define SST_PM_PCB_CREATED_size "d"
#define SST_PM_PCB_CREATED SST_PM_PCB_CREATED__enum,SST_PM_PCB_CREATED_size

// SST_PM_PCB_ID
#define SST_PM_PCB_ID_size "d"
#define SST_PM_PCB_ID SST_PM_PCB_ID__enum,SST_PM_PCB_ID_size

// SST_PM_PCB_NAME
#define SST_PM_PCB_NAME_size "cccccccc"
#define SST_PM_PCB_NAME SST_PM_PCB_NAME__enum,SST_PM_PCB_NAME_size

// SST_PM_PCB_START_ADDR
#define SST_PM_PCB_START_ADDR_size "d"
#define SST_PM_PCB_START_ADDR SST_PM_PCB_START_ADDR__enum,SST_PM_PCB_START_ADDR_size

// SST_PM_PCB_POOL_SIZE
#define SST_PM_PCB_POOL_SIZE_size "d"
#define SST_PM_PCB_POOL_SIZE SST_PM_PCB_POOL_SIZE__enum,SST_PM_PCB_POOL_SIZE_size

// SST_PM_PCB_PART_SIZE
#define SST_PM_PCB_PART_SIZE_size "d"
#define SST_PM_PCB_PART_SIZE SST_PM_PCB_PART_SIZE__enum,SST_PM_PCB_PART_SIZE_size

// SST_PM_PCB_AVAIL
#define SST_PM_PCB_AVAIL_size "d"
#define SST_PM_PCB_AVAIL SST_PM_PCB_AVAIL__enum,SST_PM_PCB_AVAIL_size

// SST_PM_PCB_ALLOCATED
#define SST_PM_PCB_ALLOCATED_size "d"
#define SST_PM_PCB_ALLOCATED SST_PM_PCB_ALLOCATED__enum,SST_PM_PCB_ALLOCATED_size

// SST_PM_PCB_AVAIL_LIST
#define SST_PM_PCB_AVAIL_LIST_size "d"
#define SST_PM_PCB_AVAIL_LIST SST_PM_PCB_AVAIL_LIST__enum,SST_PM_PCB_AVAIL_LIST_size

// SST_PM_PCB_FIFO_SUSPEND
#define SST_PM_PCB_FIFO_SUSPEND_size "d"
#define SST_PM_PCB_FIFO_SUSPEND SST_PM_PCB_FIFO_SUSPEND__enum,SST_PM_PCB_FIFO_SUSPEND_size

// SST_PM_PCB_TASK_WAIT
#define SST_PM_PCB_TASK_WAIT_size "d"
#define SST_PM_PCB_TASK_WAIT SST_PM_PCB_TASK_WAIT__enum,SST_PM_PCB_TASK_WAIT_size

// SST_PM_PCB_SUSP_LIST
#define SST_PM_PCB_SUSP_LIST_size "d"
#define SST_PM_PCB_SUSP_LIST SST_PM_PCB_SUSP_LIST__enum,SST_PM_PCB_SUSP_LIST_size

// SST_HISTORY
#define SST_HISTORY_size "d"
#define SST_HISTORY SST_HISTORY__enum,SST_HISTORY_size

// SST_HISTORY_STATE
#define SST_HISTORY_STATE_size "d"
#define SST_HISTORY_STATE SST_HISTORY_STATE__enum,SST_HISTORY_STATE_size

// SST_HISTORY_TASK
#define SST_HISTORY_TASK_size "cccccccc"
#define SST_HISTORY_TASK SST_HISTORY_TASK__enum,SST_HISTORY_TASK_size

// SST_HISTORY_FILE
#define SST_HISTORY_FILE_size "cccccccccccc"
#define SST_HISTORY_FILE SST_HISTORY_FILE__enum,SST_HISTORY_FILE_size

// SST_HISTORY_LINE
#define SST_HISTORY_LINE_size "d"
#define SST_HISTORY_LINE SST_HISTORY_LINE__enum,SST_HISTORY_LINE_size

// SST_HISTORY_SIZE
#define SST_HISTORY_SIZE_size "d"
#define SST_HISTORY_SIZE SST_HISTORY_SIZE__enum,SST_HISTORY_SIZE_size

// SST_HISTORY_LR
#define SST_HISTORY_LR_size "d"
#define SST_HISTORY_LR SST_HISTORY_LR__enum,SST_HISTORY_LR_size

// SST_CURRENT_BUFFER_HEADER
#define SST_CURRENT_BUFFER_HEADER_size ""
#define SST_CURRENT_BUFFER_HEADER SST_CURRENT_BUFFER_HEADER__enum,SST_CURRENT_BUFFER_HEADER_size

// SST_PREV_BUFFER_HEADER
#define SST_PREV_BUFFER_HEADER_size ""
#define SST_PREV_BUFFER_HEADER SST_PREV_BUFFER_HEADER__enum,SST_PREV_BUFFER_HEADER_size

// SST_NEXT_BUFFER_HEADER
#define SST_NEXT_BUFFER_HEADER_size ""
#define SST_NEXT_BUFFER_HEADER SST_NEXT_BUFFER_HEADER__enum,SST_NEXT_BUFFER_HEADER_size

// SST_BUFFER_HEADER_RTOS1
#define SST_BUFFER_HEADER_RTOS1_size "d"
#define SST_BUFFER_HEADER_RTOS1 SST_BUFFER_HEADER_RTOS1__enum,SST_BUFFER_HEADER_RTOS1_size

// SST_BUFFER_HEADER_RTOS2
#define SST_BUFFER_HEADER_RTOS2_size "d"
#define SST_BUFFER_HEADER_RTOS2 SST_BUFFER_HEADER_RTOS2__enum,SST_BUFFER_HEADER_RTOS2_size

// SST_BUFFER_HEADER_KAL1
#define SST_BUFFER_HEADER_KAL1_size "d"
#define SST_BUFFER_HEADER_KAL1 SST_BUFFER_HEADER_KAL1__enum,SST_BUFFER_HEADER_KAL1_size

// SST_BUFFER_HEADER_KAL2
#define SST_BUFFER_HEADER_KAL2_size "d"
#define SST_BUFFER_HEADER_KAL2 SST_BUFFER_HEADER_KAL2__enum,SST_BUFFER_HEADER_KAL2_size

// SST_BUFFER_FOOTER_KAL_EXT
#define SST_BUFFER_FOOTER_KAL_EXT_size "dddd"
#define SST_BUFFER_FOOTER_KAL_EXT SST_BUFFER_FOOTER_KAL_EXT__enum,SST_BUFFER_FOOTER_KAL_EXT_size

// SST_BUFFER_FOOTER_KAL_EXT_UNKNOWN
#define SST_BUFFER_FOOTER_KAL_EXT_UNKNOWN_size ""
#define SST_BUFFER_FOOTER_KAL_EXT_UNKNOWN SST_BUFFER_FOOTER_KAL_EXT_UNKNOWN__enum,SST_BUFFER_FOOTER_KAL_EXT_UNKNOWN_size

// SST_BUFFER_FOOTER_KAL2
#define SST_BUFFER_FOOTER_KAL2_size "d"
#define SST_BUFFER_FOOTER_KAL2 SST_BUFFER_FOOTER_KAL2__enum,SST_BUFFER_FOOTER_KAL2_size

// SST_POOL_INFO_G
#define SST_POOL_INFO_G_size ""
#define SST_POOL_INFO_G SST_POOL_INFO_G__enum,SST_POOL_INFO_G_size

// SST_POOL_INFO_G_NO
#define SST_POOL_INFO_G_NO_size "d"
#define SST_POOL_INFO_G_NO SST_POOL_INFO_G_NO__enum,SST_POOL_INFO_G_NO_size

// SST_POOL_INFO_G_ID
#define SST_POOL_INFO_G_ID_size "d"
#define SST_POOL_INFO_G_ID SST_POOL_INFO_G_ID__enum,SST_POOL_INFO_G_ID_size

// SST_POOL_INFO_G_START
#define SST_POOL_INFO_G_START_size "d"
#define SST_POOL_INFO_G_START SST_POOL_INFO_G_START__enum,SST_POOL_INFO_G_START_size

// SST_POOL_INFO_G_END
#define SST_POOL_INFO_G_END_size "d"
#define SST_POOL_INFO_G_END SST_POOL_INFO_G_END__enum,SST_POOL_INFO_G_END_size

// SST_PHASE1_601_01
#define SST_PHASE1_601_01_size ""
#define SST_PHASE1_601_01 SST_PHASE1_601_01__enum,SST_PHASE1_601_01_size

// SST_PHASE1_601_04
#define SST_PHASE1_601_04_size ""
#define SST_PHASE1_601_04 SST_PHASE1_601_04__enum,SST_PHASE1_601_04_size

// SST_PHASE1_602_FF
#define SST_PHASE1_602_FF_size ""
#define SST_PHASE1_602_FF SST_PHASE1_602_FF__enum,SST_PHASE1_602_FF_size

// SST_PHASE1_604_01
#define SST_PHASE1_604_01_size ""
#define SST_PHASE1_604_01 SST_PHASE1_604_01__enum,SST_PHASE1_604_01_size

// SST_PHASE1_604_02
#define SST_PHASE1_604_02_size ""
#define SST_PHASE1_604_02 SST_PHASE1_604_02__enum,SST_PHASE1_604_02_size

// SST_PHASE1_604_FF
#define SST_PHASE1_604_FF_size ""
#define SST_PHASE1_604_FF SST_PHASE1_604_FF__enum,SST_PHASE1_604_FF_size

// SST_PHASE1_605_01
#define SST_PHASE1_605_01_size ""
#define SST_PHASE1_605_01 SST_PHASE1_605_01__enum,SST_PHASE1_605_01_size

// SST_PHASE1_605_FF
#define SST_PHASE1_605_FF_size ""
#define SST_PHASE1_605_FF SST_PHASE1_605_FF__enum,SST_PHASE1_605_FF_size

// SST_PHASE1_609_26_
#define SST_PHASE1_609_26__size ""
#define SST_PHASE1_609_26_ SST_PHASE1_609_26___enum,SST_PHASE1_609_26__size

// SST_PHASE1_TIMER_FF_1
#define SST_PHASE1_TIMER_FF_1_size ""
#define SST_PHASE1_TIMER_FF_1 SST_PHASE1_TIMER_FF_1__enum,SST_PHASE1_TIMER_FF_1_size

// SST_PHASE1_TIMER_FF_2
#define SST_PHASE1_TIMER_FF_2_size ""
#define SST_PHASE1_TIMER_FF_2 SST_PHASE1_TIMER_FF_2__enum,SST_PHASE1_TIMER_FF_2_size

// SST_TM_APP_TCB
#define SST_TM_APP_TCB_size ""
#define SST_TM_APP_TCB SST_TM_APP_TCB__enum,SST_TM_APP_TCB_size

// SST_TM_APP_TCB_CREATED
#define SST_TM_APP_TCB_CREATED_size "d"
#define SST_TM_APP_TCB_CREATED SST_TM_APP_TCB_CREATED__enum,SST_TM_APP_TCB_CREATED_size

// SST_TM_APP_TCB_ID
#define SST_TM_APP_TCB_ID_size "d"
#define SST_TM_APP_TCB_ID SST_TM_APP_TCB_ID__enum,SST_TM_APP_TCB_ID_size

// SST_TM_APP_TCB_NAME
#define SST_TM_APP_TCB_NAME_size "cccccccc"
#define SST_TM_APP_TCB_NAME SST_TM_APP_TCB_NAME__enum,SST_TM_APP_TCB_NAME_size

// SST_TM_APP_TCB_FUNC
#define SST_TM_APP_TCB_FUNC_size "d"
#define SST_TM_APP_TCB_FUNC SST_TM_APP_TCB_FUNC__enum,SST_TM_APP_TCB_FUNC_size

// SST_TM_APP_TCB_EXP_ID
#define SST_TM_APP_TCB_EXP_ID_size "d"
#define SST_TM_APP_TCB_EXP_ID SST_TM_APP_TCB_EXP_ID__enum,SST_TM_APP_TCB_EXP_ID_size

// SST_TM_APP_TCB_ENABLED
#define SST_TM_APP_TCB_ENABLED_size "d"
#define SST_TM_APP_TCB_ENABLED SST_TM_APP_TCB_ENABLED__enum,SST_TM_APP_TCB_ENABLED_size

// SST_TM_APP_TCB_EXP_COUNT
#define SST_TM_APP_TCB_EXP_COUNT_size "d"
#define SST_TM_APP_TCB_EXP_COUNT SST_TM_APP_TCB_EXP_COUNT__enum,SST_TM_APP_TCB_EXP_COUNT_size

// SST_TM_APP_TCB_INIT_TIME
#define SST_TM_APP_TCB_INIT_TIME_size "d"
#define SST_TM_APP_TCB_INIT_TIME SST_TM_APP_TCB_INIT_TIME__enum,SST_TM_APP_TCB_INIT_TIME_size

// SST_TM_APP_TCB_RESCHEDULE
#define SST_TM_APP_TCB_RESCHEDULE_size "d"
#define SST_TM_APP_TCB_RESCHEDULE SST_TM_APP_TCB_RESCHEDULE__enum,SST_TM_APP_TCB_RESCHEDULE_size

// SST_TM_APP_TCB_ACTUAL_LIST
#define SST_TM_APP_TCB_ACTUAL_LIST_size "d"
#define SST_TM_APP_TCB_ACTUAL_LIST SST_TM_APP_TCB_ACTUAL_LIST__enum,SST_TM_APP_TCB_ACTUAL_LIST_size

// SST_PHASE1_c01_01
#define SST_PHASE1_c01_01_size ""
#define SST_PHASE1_c01_01 SST_PHASE1_c01_01__enum,SST_PHASE1_c01_01_size

// SST_PHASE1_c02_FF
#define SST_PHASE1_c02_FF_size ""
#define SST_PHASE1_c02_FF SST_PHASE1_c02_FF__enum,SST_PHASE1_c02_FF_size

// SST_PHASE1_c03_00
#define SST_PHASE1_c03_00_size ""
#define SST_PHASE1_c03_00 SST_PHASE1_c03_00__enum,SST_PHASE1_c03_00_size

// SST_PHASE1_c03_FF
#define SST_PHASE1_c03_FF_size ""
#define SST_PHASE1_c03_FF SST_PHASE1_c03_FF__enum,SST_PHASE1_c03_FF_size

// SST_PHASE1_c04_FF
#define SST_PHASE1_c04_FF_size "d"
#define SST_PHASE1_c04_FF SST_PHASE1_c04_FF__enum,SST_PHASE1_c04_FF_size

// SST_PHASE1_c05_ID
#define SST_PHASE1_c05_ID_size "d"
#define SST_PHASE1_c05_ID SST_PHASE1_c05_ID__enum,SST_PHASE1_c05_ID_size

// SST_PHASE1_b02
#define SST_PHASE1_b02_size ""
#define SST_PHASE1_b02 SST_PHASE1_b02__enum,SST_PHASE1_b02_size

// SST_PHASE1_b03
#define SST_PHASE1_b03_size ""
#define SST_PHASE1_b03 SST_PHASE1_b03__enum,SST_PHASE1_b03_size

// SST_PHASE1_b04
#define SST_PHASE1_b04_size ""
#define SST_PHASE1_b04 SST_PHASE1_b04__enum,SST_PHASE1_b04_size

// SST_PHASE1_1501
#define SST_PHASE1_1501_size "dd"
#define SST_PHASE1_1501 SST_PHASE1_1501__enum,SST_PHASE1_1501_size

// SST_PHASE1_1502
#define SST_PHASE1_1502_size "dd"
#define SST_PHASE1_1502 SST_PHASE1_1502__enum,SST_PHASE1_1502_size

// SST_PHASE1_1503
#define SST_PHASE1_1503_size "dd"
#define SST_PHASE1_1503 SST_PHASE1_1503__enum,SST_PHASE1_1503_size

// SST_PHASE1_1504
#define SST_PHASE1_1504_size "dd"
#define SST_PHASE1_1504 SST_PHASE1_1504__enum,SST_PHASE1_1504_size

// SST_PHASE1_b04_OutOfRange
#define SST_PHASE1_b04_OutOfRange_size ""
#define SST_PHASE1_b04_OutOfRange SST_PHASE1_b04_OutOfRange__enum,SST_PHASE1_b04_OutOfRange_size

// SST_PHASE1_b04_NOT_REG
#define SST_PHASE1_b04_NOT_REG_size "d"
#define SST_PHASE1_b04_NOT_REG SST_PHASE1_b04_NOT_REG__enum,SST_PHASE1_b04_NOT_REG_size

// SST_PHASE1_b04_MEMORY_CORRUPTION
#define SST_PHASE1_b04_MEMORY_CORRUPTION_size "d"
#define SST_PHASE1_b04_MEMORY_CORRUPTION SST_PHASE1_b04_MEMORY_CORRUPTION__enum,SST_PHASE1_b04_MEMORY_CORRUPTION_size

// SST_PHASE2_b04_LISR_DISPATCH_TBL
#define SST_PHASE2_b04_LISR_DISPATCH_TBL_size "d"
#define SST_PHASE2_b04_LISR_DISPATCH_TBL SST_PHASE2_b04_LISR_DISPATCH_TBL__enum,SST_PHASE2_b04_LISR_DISPATCH_TBL_size

// SST_PHASE2_b04_LISR_DISPATCH_TBL_V
#define SST_PHASE2_b04_LISR_DISPATCH_TBL_V_size "d"
#define SST_PHASE2_b04_LISR_DISPATCH_TBL_V SST_PHASE2_b04_LISR_DISPATCH_TBL_V__enum,SST_PHASE2_b04_LISR_DISPATCH_TBL_V_size

// SST_PHASE2_b04_LISR_DISPATCH_TBL_H
#define SST_PHASE2_b04_LISR_DISPATCH_TBL_H_size "d"
#define SST_PHASE2_b04_LISR_DISPATCH_TBL_H SST_PHASE2_b04_LISR_DISPATCH_TBL_H__enum,SST_PHASE2_b04_LISR_DISPATCH_TBL_H_size

// SST_PHASE2_b04_LISR_DISPATCH_TBL_D
#define SST_PHASE2_b04_LISR_DISPATCH_TBL_D_size "cccccccc"
#define SST_PHASE2_b04_LISR_DISPATCH_TBL_D SST_PHASE2_b04_LISR_DISPATCH_TBL_D__enum,SST_PHASE2_b04_LISR_DISPATCH_TBL_D_size

// SST_PHASE1_1700_01
#define SST_PHASE1_1700_01_size ""
#define SST_PHASE1_1700_01 SST_PHASE1_1700_01__enum,SST_PHASE1_1700_01_size

// SST_PHASE1_1700_02
#define SST_PHASE1_1700_02_size ""
#define SST_PHASE1_1700_02 SST_PHASE1_1700_02__enum,SST_PHASE1_1700_02_size

// SST_PHASE1_1710_01
#define SST_PHASE1_1710_01_size ""
#define SST_PHASE1_1710_01 SST_PHASE1_1710_01__enum,SST_PHASE1_1710_01_size

// SST_PHASE1_1720_01
#define SST_PHASE1_1720_01_size ""
#define SST_PHASE1_1720_01 SST_PHASE1_1720_01__enum,SST_PHASE1_1720_01_size

// SST_PHASE1_1720_04
#define SST_PHASE1_1720_04_size ""
#define SST_PHASE1_1720_04 SST_PHASE1_1720_04__enum,SST_PHASE1_1720_04_size

// SST_PHASE1_1726_01
#define SST_PHASE1_1726_01_size ""
#define SST_PHASE1_1726_01 SST_PHASE1_1726_01__enum,SST_PHASE1_1726_01_size

// SST_PHASE1_1726_02
#define SST_PHASE1_1726_02_size ""
#define SST_PHASE1_1726_02 SST_PHASE1_1726_02__enum,SST_PHASE1_1726_02_size

// SST_PHASE1_172C_01
#define SST_PHASE1_172C_01_size ""
#define SST_PHASE1_172C_01 SST_PHASE1_172C_01__enum,SST_PHASE1_172C_01_size

// SST_PHASE1_172C_04
#define SST_PHASE1_172C_04_size ""
#define SST_PHASE1_172C_04 SST_PHASE1_172C_04__enum,SST_PHASE1_172C_04_size

// SST_PHASE1_1730_01
#define SST_PHASE1_1730_01_size ""
#define SST_PHASE1_1730_01 SST_PHASE1_1730_01__enum,SST_PHASE1_1730_01_size

// SST_PHASE1_1730_02
#define SST_PHASE1_1730_02_size ""
#define SST_PHASE1_1730_02 SST_PHASE1_1730_02__enum,SST_PHASE1_1730_02_size

// SST_PHASE1_1732_ADDR
#define SST_PHASE1_1732_ADDR_size ""
#define SST_PHASE1_1732_ADDR SST_PHASE1_1732_ADDR__enum,SST_PHASE1_1732_ADDR_size

// SST_PHASE1_1740_ADDR
#define SST_PHASE1_1740_ADDR_size ""
#define SST_PHASE1_1740_ADDR SST_PHASE1_1740_ADDR__enum,SST_PHASE1_1740_ADDR_size

// SST_PHASE1_1741_ADDR
#define SST_PHASE1_1741_ADDR_size ""
#define SST_PHASE1_1741_ADDR SST_PHASE1_1741_ADDR__enum,SST_PHASE1_1741_ADDR_size

// SST_PHASE1_1750_00
#define SST_PHASE1_1750_00_size ""
#define SST_PHASE1_1750_00 SST_PHASE1_1750_00__enum,SST_PHASE1_1750_00_size

// SST_PHASE1_1751_00
#define SST_PHASE1_1751_00_size ""
#define SST_PHASE1_1751_00 SST_PHASE1_1751_00__enum,SST_PHASE1_1751_00_size

// SST_PHASE1_1752_00
#define SST_PHASE1_1752_00_size ""
#define SST_PHASE1_1752_00 SST_PHASE1_1752_00__enum,SST_PHASE1_1752_00_size

// SST_PHASE1_1753_00
#define SST_PHASE1_1753_00_size ""
#define SST_PHASE1_1753_00 SST_PHASE1_1753_00__enum,SST_PHASE1_1753_00_size

// SST_PHASE1_1754_00
#define SST_PHASE1_1754_00_size ""
#define SST_PHASE1_1754_00 SST_PHASE1_1754_00__enum,SST_PHASE1_1754_00_size

// SST_PHASE1_1760_ID
#define SST_PHASE1_1760_ID_size ""
#define SST_PHASE1_1760_ID SST_PHASE1_1760_ID__enum,SST_PHASE1_1760_ID_size

// SST_PHASE1_1761_ID
#define SST_PHASE1_1761_ID_size ""
#define SST_PHASE1_1761_ID SST_PHASE1_1761_ID__enum,SST_PHASE1_1761_ID_size

// SST_PHASE1_1762_ID
#define SST_PHASE1_1762_ID_size ""
#define SST_PHASE1_1762_ID SST_PHASE1_1762_ID__enum,SST_PHASE1_1762_ID_size

// SST_PHASE1_1763_ID
#define SST_PHASE1_1763_ID_size ""
#define SST_PHASE1_1763_ID SST_PHASE1_1763_ID__enum,SST_PHASE1_1763_ID_size

// SST_PHASE1_1764_ID
#define SST_PHASE1_1764_ID_size ""
#define SST_PHASE1_1764_ID SST_PHASE1_1764_ID__enum,SST_PHASE1_1764_ID_size

// SST_PHASE1_1770_TASK
#define SST_PHASE1_1770_TASK_size ""
#define SST_PHASE1_1770_TASK SST_PHASE1_1770_TASK__enum,SST_PHASE1_1770_TASK_size

// SST_PHASE1_1771_PTR
#define SST_PHASE1_1771_PTR_size ""
#define SST_PHASE1_1771_PTR SST_PHASE1_1771_PTR__enum,SST_PHASE1_1771_PTR_size

// SST_PHASE1_1781_ADDR
#define SST_PHASE1_1781_ADDR_size ""
#define SST_PHASE1_1781_ADDR SST_PHASE1_1781_ADDR__enum,SST_PHASE1_1781_ADDR_size

// SST_PHASE3_1700_01
#define SST_PHASE3_1700_01_size ""
#define SST_PHASE3_1700_01 SST_PHASE3_1700_01__enum,SST_PHASE3_1700_01_size

// SST_PHASE3_1700_02_P1
#define SST_PHASE3_1700_02_P1_size ""
#define SST_PHASE3_1700_02_P1 SST_PHASE3_1700_02_P1__enum,SST_PHASE3_1700_02_P1_size

// SST_PHASE3_1700_02_P2
#define SST_PHASE3_1700_02_P2_size ""
#define SST_PHASE3_1700_02_P2 SST_PHASE3_1700_02_P2__enum,SST_PHASE3_1700_02_P2_size

// SST_PHASE3_1710_01
#define SST_PHASE3_1710_01_size ""
#define SST_PHASE3_1710_01 SST_PHASE3_1710_01__enum,SST_PHASE3_1710_01_size

// SST_PHASE3_1720_01_P1
#define SST_PHASE3_1720_01_P1_size ""
#define SST_PHASE3_1720_01_P1 SST_PHASE3_1720_01_P1__enum,SST_PHASE3_1720_01_P1_size

// SST_PHASE3_1720_01_P2
#define SST_PHASE3_1720_01_P2_size ""
#define SST_PHASE3_1720_01_P2 SST_PHASE3_1720_01_P2__enum,SST_PHASE3_1720_01_P2_size

// SST_PHASE3_1720_04
#define SST_PHASE3_1720_04_size ""
#define SST_PHASE3_1720_04 SST_PHASE3_1720_04__enum,SST_PHASE3_1720_04_size

// SST_PHASE3_1726_01_P1
#define SST_PHASE3_1726_01_P1_size ""
#define SST_PHASE3_1726_01_P1 SST_PHASE3_1726_01_P1__enum,SST_PHASE3_1726_01_P1_size

// SST_PHASE3_1726_01_P2
#define SST_PHASE3_1726_01_P2_size ""
#define SST_PHASE3_1726_01_P2 SST_PHASE3_1726_01_P2__enum,SST_PHASE3_1726_01_P2_size

// SST_PHASE3_1726_02_P1
#define SST_PHASE3_1726_02_P1_size ""
#define SST_PHASE3_1726_02_P1 SST_PHASE3_1726_02_P1__enum,SST_PHASE3_1726_02_P1_size

// SST_PHASE3_1726_02_P2
#define SST_PHASE3_1726_02_P2_size ""
#define SST_PHASE3_1726_02_P2 SST_PHASE3_1726_02_P2__enum,SST_PHASE3_1726_02_P2_size

// SST_PHASE3_172C_01_P1
#define SST_PHASE3_172C_01_P1_size ""
#define SST_PHASE3_172C_01_P1 SST_PHASE3_172C_01_P1__enum,SST_PHASE3_172C_01_P1_size

// SST_PHASE3_172C_01_P2
#define SST_PHASE3_172C_01_P2_size ""
#define SST_PHASE3_172C_01_P2 SST_PHASE3_172C_01_P2__enum,SST_PHASE3_172C_01_P2_size

// SST_PHASE3_172C_01_P3
#define SST_PHASE3_172C_01_P3_size ""
#define SST_PHASE3_172C_01_P3 SST_PHASE3_172C_01_P3__enum,SST_PHASE3_172C_01_P3_size

// SST_PHASE3_172C_01_P4
#define SST_PHASE3_172C_01_P4_size ""
#define SST_PHASE3_172C_01_P4 SST_PHASE3_172C_01_P4__enum,SST_PHASE3_172C_01_P4_size

// SST_PHASE3_172C_04
#define SST_PHASE3_172C_04_size ""
#define SST_PHASE3_172C_04 SST_PHASE3_172C_04__enum,SST_PHASE3_172C_04_size

// SST_PHASE3_1730_01_P1
#define SST_PHASE3_1730_01_P1_size ""
#define SST_PHASE3_1730_01_P1 SST_PHASE3_1730_01_P1__enum,SST_PHASE3_1730_01_P1_size

// SST_PHASE3_1730_01_P2
#define SST_PHASE3_1730_01_P2_size ""
#define SST_PHASE3_1730_01_P2 SST_PHASE3_1730_01_P2__enum,SST_PHASE3_1730_01_P2_size

// SST_PHASE3_1730_02_P1
#define SST_PHASE3_1730_02_P1_size ""
#define SST_PHASE3_1730_02_P1 SST_PHASE3_1730_02_P1__enum,SST_PHASE3_1730_02_P1_size

// SST_PHASE3_1730_02_P2
#define SST_PHASE3_1730_02_P2_size ""
#define SST_PHASE3_1730_02_P2 SST_PHASE3_1730_02_P2__enum,SST_PHASE3_1730_02_P2_size

// SST_PHASE3_1732_ADDR
#define SST_PHASE3_1732_ADDR_size ""
#define SST_PHASE3_1732_ADDR SST_PHASE3_1732_ADDR__enum,SST_PHASE3_1732_ADDR_size

// SST_PHASE3_1740_ADDR_P1
#define SST_PHASE3_1740_ADDR_P1_size ""
#define SST_PHASE3_1740_ADDR_P1 SST_PHASE3_1740_ADDR_P1__enum,SST_PHASE3_1740_ADDR_P1_size

// SST_PHASE3_1740_ADDR_P2
#define SST_PHASE3_1740_ADDR_P2_size ""
#define SST_PHASE3_1740_ADDR_P2 SST_PHASE3_1740_ADDR_P2__enum,SST_PHASE3_1740_ADDR_P2_size

// SST_PHASE3_1741_ADDR_P1
#define SST_PHASE3_1741_ADDR_P1_size ""
#define SST_PHASE3_1741_ADDR_P1 SST_PHASE3_1741_ADDR_P1__enum,SST_PHASE3_1741_ADDR_P1_size

// SST_PHASE3_1741_ADDR_P2
#define SST_PHASE3_1741_ADDR_P2_size ""
#define SST_PHASE3_1741_ADDR_P2 SST_PHASE3_1741_ADDR_P2__enum,SST_PHASE3_1741_ADDR_P2_size

// SST_PHASE3_1750_00
#define SST_PHASE3_1750_00_size ""
#define SST_PHASE3_1750_00 SST_PHASE3_1750_00__enum,SST_PHASE3_1750_00_size

// SST_PHASE3_1751_00
#define SST_PHASE3_1751_00_size ""
#define SST_PHASE3_1751_00 SST_PHASE3_1751_00__enum,SST_PHASE3_1751_00_size

// SST_PHASE3_1752_00
#define SST_PHASE3_1752_00_size ""
#define SST_PHASE3_1752_00 SST_PHASE3_1752_00__enum,SST_PHASE3_1752_00_size

// SST_PHASE3_1753_00
#define SST_PHASE3_1753_00_size ""
#define SST_PHASE3_1753_00 SST_PHASE3_1753_00__enum,SST_PHASE3_1753_00_size

// SST_PHASE3_1754_00
#define SST_PHASE3_1754_00_size ""
#define SST_PHASE3_1754_00 SST_PHASE3_1754_00__enum,SST_PHASE3_1754_00_size

// SST_PHASE3_1760_ID_P1
#define SST_PHASE3_1760_ID_P1_size ""
#define SST_PHASE3_1760_ID_P1 SST_PHASE3_1760_ID_P1__enum,SST_PHASE3_1760_ID_P1_size

// SST_PHASE3_1760_ID_P2
#define SST_PHASE3_1760_ID_P2_size ""
#define SST_PHASE3_1760_ID_P2 SST_PHASE3_1760_ID_P2__enum,SST_PHASE3_1760_ID_P2_size

// SST_PHASE3_1761_ID_P1
#define SST_PHASE3_1761_ID_P1_size ""
#define SST_PHASE3_1761_ID_P1 SST_PHASE3_1761_ID_P1__enum,SST_PHASE3_1761_ID_P1_size

// SST_PHASE3_1761_ID_P2
#define SST_PHASE3_1761_ID_P2_size "d"
#define SST_PHASE3_1761_ID_P2 SST_PHASE3_1761_ID_P2__enum,SST_PHASE3_1761_ID_P2_size

// SST_PHASE3_1762_ID_P1
#define SST_PHASE3_1762_ID_P1_size ""
#define SST_PHASE3_1762_ID_P1 SST_PHASE3_1762_ID_P1__enum,SST_PHASE3_1762_ID_P1_size

// SST_PHASE3_1762_ID_P2
#define SST_PHASE3_1762_ID_P2_size "d"
#define SST_PHASE3_1762_ID_P2 SST_PHASE3_1762_ID_P2__enum,SST_PHASE3_1762_ID_P2_size

// SST_PHASE3_1763_ID_P1
#define SST_PHASE3_1763_ID_P1_size ""
#define SST_PHASE3_1763_ID_P1 SST_PHASE3_1763_ID_P1__enum,SST_PHASE3_1763_ID_P1_size

// SST_PHASE3_1763_ID_P2
#define SST_PHASE3_1763_ID_P2_size "d"
#define SST_PHASE3_1763_ID_P2 SST_PHASE3_1763_ID_P2__enum,SST_PHASE3_1763_ID_P2_size

// SST_PHASE3_1764_ID_P1
#define SST_PHASE3_1764_ID_P1_size ""
#define SST_PHASE3_1764_ID_P1 SST_PHASE3_1764_ID_P1__enum,SST_PHASE3_1764_ID_P1_size

// SST_PHASE3_1764_ID_P2
#define SST_PHASE3_1764_ID_P2_size "d"
#define SST_PHASE3_1764_ID_P2 SST_PHASE3_1764_ID_P2__enum,SST_PHASE3_1764_ID_P2_size

// SST_PHASE3_1770_TASK_P1
#define SST_PHASE3_1770_TASK_P1_size "d"
#define SST_PHASE3_1770_TASK_P1 SST_PHASE3_1770_TASK_P1__enum,SST_PHASE3_1770_TASK_P1_size

// SST_PHASE3_1770_TASK_P2
#define SST_PHASE3_1770_TASK_P2_size "d"
#define SST_PHASE3_1770_TASK_P2 SST_PHASE3_1770_TASK_P2__enum,SST_PHASE3_1770_TASK_P2_size

// SST_PHASE3_1771_PTR
#define SST_PHASE3_1771_PTR_size ""
#define SST_PHASE3_1771_PTR SST_PHASE3_1771_PTR__enum,SST_PHASE3_1771_PTR_size

// SST_PHASE3_1781_ADDR_P1
#define SST_PHASE3_1781_ADDR_P1_size ""
#define SST_PHASE3_1781_ADDR_P1 SST_PHASE3_1781_ADDR_P1__enum,SST_PHASE3_1781_ADDR_P1_size

// SST_PHASE3_1781_ADDR_P2
#define SST_PHASE3_1781_ADDR_P2_size ""
#define SST_PHASE3_1781_ADDR_P2 SST_PHASE3_1781_ADDR_P2__enum,SST_PHASE3_1781_ADDR_P2_size

// SST_PHASE1_1800_01
#define SST_PHASE1_1800_01_size ""
#define SST_PHASE1_1800_01 SST_PHASE1_1800_01__enum,SST_PHASE1_1800_01_size

// SST_PHASE1_1800_02
#define SST_PHASE1_1800_02_size ""
#define SST_PHASE1_1800_02 SST_PHASE1_1800_02__enum,SST_PHASE1_1800_02_size

// SST_PHASE1_1800_03
#define SST_PHASE1_1800_03_size ""
#define SST_PHASE1_1800_03 SST_PHASE1_1800_03__enum,SST_PHASE1_1800_03_size

// SST_PHASE1_1820_05
#define SST_PHASE1_1820_05_size ""
#define SST_PHASE1_1820_05 SST_PHASE1_1820_05__enum,SST_PHASE1_1820_05_size

// SST_PHASE1_1826_01
#define SST_PHASE1_1826_01_size ""
#define SST_PHASE1_1826_01 SST_PHASE1_1826_01__enum,SST_PHASE1_1826_01_size

// SST_PHASE1_1826_02
#define SST_PHASE1_1826_02_size ""
#define SST_PHASE1_1826_02 SST_PHASE1_1826_02__enum,SST_PHASE1_1826_02_size

// SST_PHASE1_1831_ADDR
#define SST_PHASE1_1831_ADDR_size ""
#define SST_PHASE1_1831_ADDR SST_PHASE1_1831_ADDR__enum,SST_PHASE1_1831_ADDR_size

// SST_PHASE1_1840_ADDR
#define SST_PHASE1_1840_ADDR_size ""
#define SST_PHASE1_1840_ADDR SST_PHASE1_1840_ADDR__enum,SST_PHASE1_1840_ADDR_size

// SST_PHASE1_1841_ADDR
#define SST_PHASE1_1841_ADDR_size ""
#define SST_PHASE1_1841_ADDR SST_PHASE1_1841_ADDR__enum,SST_PHASE1_1841_ADDR_size

// SST_PHASE1_1842_ADDR
#define SST_PHASE1_1842_ADDR_size ""
#define SST_PHASE1_1842_ADDR SST_PHASE1_1842_ADDR__enum,SST_PHASE1_1842_ADDR_size

// SST_PHASE1_1843_ADDR
#define SST_PHASE1_1843_ADDR_size ""
#define SST_PHASE1_1843_ADDR SST_PHASE1_1843_ADDR__enum,SST_PHASE1_1843_ADDR_size

// SST_PHASE1_1851_00
#define SST_PHASE1_1851_00_size ""
#define SST_PHASE1_1851_00 SST_PHASE1_1851_00__enum,SST_PHASE1_1851_00_size

// SST_PHASE1_1852_00
#define SST_PHASE1_1852_00_size ""
#define SST_PHASE1_1852_00 SST_PHASE1_1852_00__enum,SST_PHASE1_1852_00_size

// SST_PHASE1_1853_00
#define SST_PHASE1_1853_00_size ""
#define SST_PHASE1_1853_00 SST_PHASE1_1853_00__enum,SST_PHASE1_1853_00_size

// SST_PHASE1_1861_ID
#define SST_PHASE1_1861_ID_size ""
#define SST_PHASE1_1861_ID SST_PHASE1_1861_ID__enum,SST_PHASE1_1861_ID_size

// SST_PHASE1_1862_ID
#define SST_PHASE1_1862_ID_size ""
#define SST_PHASE1_1862_ID SST_PHASE1_1862_ID__enum,SST_PHASE1_1862_ID_size

// SST_PHASE1_1863_ID
#define SST_PHASE1_1863_ID_size ""
#define SST_PHASE1_1863_ID SST_PHASE1_1863_ID__enum,SST_PHASE1_1863_ID_size

// SST_PHASE3_1800_01
#define SST_PHASE3_1800_01_size ""
#define SST_PHASE3_1800_01 SST_PHASE3_1800_01__enum,SST_PHASE3_1800_01_size

// SST_PHASE3_1800_02
#define SST_PHASE3_1800_02_size ""
#define SST_PHASE3_1800_02 SST_PHASE3_1800_02__enum,SST_PHASE3_1800_02_size

// SST_PHASE3_1800_03
#define SST_PHASE3_1800_03_size ""
#define SST_PHASE3_1800_03 SST_PHASE3_1800_03__enum,SST_PHASE3_1800_03_size

// SST_PHASE3_1820_05_P1
#define SST_PHASE3_1820_05_P1_size ""
#define SST_PHASE3_1820_05_P1 SST_PHASE3_1820_05_P1__enum,SST_PHASE3_1820_05_P1_size

// SST_PHASE3_1820_05_P2
#define SST_PHASE3_1820_05_P2_size ""
#define SST_PHASE3_1820_05_P2 SST_PHASE3_1820_05_P2__enum,SST_PHASE3_1820_05_P2_size

// SST_PHASE3_1826_01_P1
#define SST_PHASE3_1826_01_P1_size ""
#define SST_PHASE3_1826_01_P1 SST_PHASE3_1826_01_P1__enum,SST_PHASE3_1826_01_P1_size

// SST_PHASE3_1826_01_P2
#define SST_PHASE3_1826_01_P2_size ""
#define SST_PHASE3_1826_01_P2 SST_PHASE3_1826_01_P2__enum,SST_PHASE3_1826_01_P2_size

// SST_PHASE3_1826_01_P3
#define SST_PHASE3_1826_01_P3_size ""
#define SST_PHASE3_1826_01_P3 SST_PHASE3_1826_01_P3__enum,SST_PHASE3_1826_01_P3_size

// SST_PHASE3_1826_02_P1
#define SST_PHASE3_1826_02_P1_size ""
#define SST_PHASE3_1826_02_P1 SST_PHASE3_1826_02_P1__enum,SST_PHASE3_1826_02_P1_size

// SST_PHASE3_1826_02_P2
#define SST_PHASE3_1826_02_P2_size ""
#define SST_PHASE3_1826_02_P2 SST_PHASE3_1826_02_P2__enum,SST_PHASE3_1826_02_P2_size

// SST_PHASE3_1826_02_P3
#define SST_PHASE3_1826_02_P3_size ""
#define SST_PHASE3_1826_02_P3 SST_PHASE3_1826_02_P3__enum,SST_PHASE3_1826_02_P3_size

// SST_PHASE3_1831_ADDR
#define SST_PHASE3_1831_ADDR_size ""
#define SST_PHASE3_1831_ADDR SST_PHASE3_1831_ADDR__enum,SST_PHASE3_1831_ADDR_size

// SST_PHASE3_1840_ADDR_P1
#define SST_PHASE3_1840_ADDR_P1_size ""
#define SST_PHASE3_1840_ADDR_P1 SST_PHASE3_1840_ADDR_P1__enum,SST_PHASE3_1840_ADDR_P1_size

// SST_PHASE3_1840_ADDR_P2
#define SST_PHASE3_1840_ADDR_P2_size ""
#define SST_PHASE3_1840_ADDR_P2 SST_PHASE3_1840_ADDR_P2__enum,SST_PHASE3_1840_ADDR_P2_size

// SST_PHASE3_1841_ADDR_P1
#define SST_PHASE3_1841_ADDR_P1_size ""
#define SST_PHASE3_1841_ADDR_P1 SST_PHASE3_1841_ADDR_P1__enum,SST_PHASE3_1841_ADDR_P1_size

// SST_PHASE3_1841_ADDR_P2
#define SST_PHASE3_1841_ADDR_P2_size ""
#define SST_PHASE3_1841_ADDR_P2 SST_PHASE3_1841_ADDR_P2__enum,SST_PHASE3_1841_ADDR_P2_size

// SST_PHASE3_1842_ADDR_P1
#define SST_PHASE3_1842_ADDR_P1_size "d"
#define SST_PHASE3_1842_ADDR_P1 SST_PHASE3_1842_ADDR_P1__enum,SST_PHASE3_1842_ADDR_P1_size

// SST_PHASE3_1842_ADDR_P2
#define SST_PHASE3_1842_ADDR_P2_size "d"
#define SST_PHASE3_1842_ADDR_P2 SST_PHASE3_1842_ADDR_P2__enum,SST_PHASE3_1842_ADDR_P2_size

// SST_PHASE3_1843_ADDR_P1
#define SST_PHASE3_1843_ADDR_P1_size "d"
#define SST_PHASE3_1843_ADDR_P1 SST_PHASE3_1843_ADDR_P1__enum,SST_PHASE3_1843_ADDR_P1_size

// SST_PHASE3_1843_ADDR_P2
#define SST_PHASE3_1843_ADDR_P2_size "d"
#define SST_PHASE3_1843_ADDR_P2 SST_PHASE3_1843_ADDR_P2__enum,SST_PHASE3_1843_ADDR_P2_size

// SST_PHASE3_1851_00
#define SST_PHASE3_1851_00_size ""
#define SST_PHASE3_1851_00 SST_PHASE3_1851_00__enum,SST_PHASE3_1851_00_size

// SST_PHASE3_1852_00
#define SST_PHASE3_1852_00_size ""
#define SST_PHASE3_1852_00 SST_PHASE3_1852_00__enum,SST_PHASE3_1852_00_size

// SST_PHASE3_1853_00
#define SST_PHASE3_1853_00_size ""
#define SST_PHASE3_1853_00 SST_PHASE3_1853_00__enum,SST_PHASE3_1853_00_size

// SST_PHASE3_1861_ID_P1
#define SST_PHASE3_1861_ID_P1_size ""
#define SST_PHASE3_1861_ID_P1 SST_PHASE3_1861_ID_P1__enum,SST_PHASE3_1861_ID_P1_size

// SST_PHASE3_1861_ID_P2
#define SST_PHASE3_1861_ID_P2_size "d"
#define SST_PHASE3_1861_ID_P2 SST_PHASE3_1861_ID_P2__enum,SST_PHASE3_1861_ID_P2_size

// SST_PHASE3_1862_ID_P1
#define SST_PHASE3_1862_ID_P1_size ""
#define SST_PHASE3_1862_ID_P1 SST_PHASE3_1862_ID_P1__enum,SST_PHASE3_1862_ID_P1_size

// SST_PHASE3_1862_ID_P2
#define SST_PHASE3_1862_ID_P2_size "d"
#define SST_PHASE3_1862_ID_P2 SST_PHASE3_1862_ID_P2__enum,SST_PHASE3_1862_ID_P2_size

// SST_PHASE3_1863_ID_P1
#define SST_PHASE3_1863_ID_P1_size ""
#define SST_PHASE3_1863_ID_P1 SST_PHASE3_1863_ID_P1__enum,SST_PHASE3_1863_ID_P1_size

// SST_PHASE3_1863_ID_P2
#define SST_PHASE3_1863_ID_P2_size "d"
#define SST_PHASE3_1863_ID_P2 SST_PHASE3_1863_ID_P2__enum,SST_PHASE3_1863_ID_P2_size

// SST_EXC_WATCHDOG_RESET_ENTER
#define SST_EXC_WATCHDOG_RESET_ENTER_size ""
#define SST_EXC_WATCHDOG_RESET_ENTER SST_EXC_WATCHDOG_RESET_ENTER__enum,SST_EXC_WATCHDOG_RESET_ENTER_size

// SST_EXC_WATCHDOG_RESET_EXIT
#define SST_EXC_WATCHDOG_RESET_EXIT_size ""
#define SST_EXC_WATCHDOG_RESET_EXIT SST_EXC_WATCHDOG_RESET_EXIT__enum,SST_EXC_WATCHDOG_RESET_EXIT_size

// SST_EXC_WATCHDOG_DISABLE_ENTER
#define SST_EXC_WATCHDOG_DISABLE_ENTER_size ""
#define SST_EXC_WATCHDOG_DISABLE_ENTER SST_EXC_WATCHDOG_DISABLE_ENTER__enum,SST_EXC_WATCHDOG_DISABLE_ENTER_size

// SST_EXC_WATCHDOG_DISABLE_EXIT
#define SST_EXC_WATCHDOG_DISABLE_EXIT_size ""
#define SST_EXC_WATCHDOG_DISABLE_EXIT SST_EXC_WATCHDOG_DISABLE_EXIT__enum,SST_EXC_WATCHDOG_DISABLE_EXIT_size

// SST_EXC_OPEN_LOGGING_PORT_ENTER
#define SST_EXC_OPEN_LOGGING_PORT_ENTER_size ""
#define SST_EXC_OPEN_LOGGING_PORT_ENTER SST_EXC_OPEN_LOGGING_PORT_ENTER__enum,SST_EXC_OPEN_LOGGING_PORT_ENTER_size

// SST_EXC_OPEN_LOGGING_PORT_EXIT
#define SST_EXC_OPEN_LOGGING_PORT_EXIT_size ""
#define SST_EXC_OPEN_LOGGING_PORT_EXIT SST_EXC_OPEN_LOGGING_PORT_EXIT__enum,SST_EXC_OPEN_LOGGING_PORT_EXIT_size

// SST_EXC_UST_GET_TIME_ENTER
#define SST_EXC_UST_GET_TIME_ENTER_size ""
#define SST_EXC_UST_GET_TIME_ENTER SST_EXC_UST_GET_TIME_ENTER__enum,SST_EXC_UST_GET_TIME_ENTER_size

// SST_EXC_UST_GET_TIME_EXIT
#define SST_EXC_UST_GET_TIME_EXIT_size ""
#define SST_EXC_UST_GET_TIME_EXIT SST_EXC_UST_GET_TIME_EXIT__enum,SST_EXC_UST_GET_TIME_EXIT_size

// SST_EXC_USC_GET_TIME_ENTER
#define SST_EXC_USC_GET_TIME_ENTER_size ""
#define SST_EXC_USC_GET_TIME_ENTER SST_EXC_USC_GET_TIME_ENTER__enum,SST_EXC_USC_GET_TIME_ENTER_size

// SST_EXC_USC_GET_TIME_EXIT
#define SST_EXC_USC_GET_TIME_EXIT_size ""
#define SST_EXC_USC_GET_TIME_EXIT SST_EXC_USC_GET_TIME_EXIT__enum,SST_EXC_USC_GET_TIME_EXIT_size

// SST_EXC_NOTIFY_DSP_ENTER
#define SST_EXC_NOTIFY_DSP_ENTER_size ""
#define SST_EXC_NOTIFY_DSP_ENTER SST_EXC_NOTIFY_DSP_ENTER__enum,SST_EXC_NOTIFY_DSP_ENTER_size

// SST_EXC_NOTIFY_DSP_EXIT
#define SST_EXC_NOTIFY_DSP_EXIT_size ""
#define SST_EXC_NOTIFY_DSP_EXIT SST_EXC_NOTIFY_DSP_EXIT__enum,SST_EXC_NOTIFY_DSP_EXIT_size

// SST_EXC_CCCI_HANDSHAKING_ENTER
#define SST_EXC_CCCI_HANDSHAKING_ENTER_size ""
#define SST_EXC_CCCI_HANDSHAKING_ENTER SST_EXC_CCCI_HANDSHAKING_ENTER__enum,SST_EXC_CCCI_HANDSHAKING_ENTER_size

// SST_EXC_CCCI_HANDSHAKING_EXIT
#define SST_EXC_CCCI_HANDSHAKING_EXIT_size ""
#define SST_EXC_CCCI_HANDSHAKING_EXIT SST_EXC_CCCI_HANDSHAKING_EXIT__enum,SST_EXC_CCCI_HANDSHAKING_EXIT_size

// SST_EXC_RESET_HARDWARE_ENTER
#define SST_EXC_RESET_HARDWARE_ENTER_size ""
#define SST_EXC_RESET_HARDWARE_ENTER SST_EXC_RESET_HARDWARE_ENTER__enum,SST_EXC_RESET_HARDWARE_ENTER_size

// SST_EXC_RESET_HARDWARE_EXIT
#define SST_EXC_RESET_HARDWARE_EXIT_size ""
#define SST_EXC_RESET_HARDWARE_EXIT SST_EXC_RESET_HARDWARE_EXIT__enum,SST_EXC_RESET_HARDWARE_EXIT_size

// SST_EXC_INIT_EXCEPTION_RECORD_ENTER
#define SST_EXC_INIT_EXCEPTION_RECORD_ENTER_size ""
#define SST_EXC_INIT_EXCEPTION_RECORD_ENTER SST_EXC_INIT_EXCEPTION_RECORD_ENTER__enum,SST_EXC_INIT_EXCEPTION_RECORD_ENTER_size

// SST_EXC_INIT_EXCEPTION_RECORD_EXIT
#define SST_EXC_INIT_EXCEPTION_RECORD_EXIT_size ""
#define SST_EXC_INIT_EXCEPTION_RECORD_EXIT SST_EXC_INIT_EXCEPTION_RECORD_EXIT__enum,SST_EXC_INIT_EXCEPTION_RECORD_EXIT_size

// SST_EXC_CHECK_ALICE_ENTER
#define SST_EXC_CHECK_ALICE_ENTER_size ""
#define SST_EXC_CHECK_ALICE_ENTER SST_EXC_CHECK_ALICE_ENTER__enum,SST_EXC_CHECK_ALICE_ENTER_size

// SST_EXC_CHECK_ALICE_EXIT
#define SST_EXC_CHECK_ALICE_EXIT_size ""
#define SST_EXC_CHECK_ALICE_EXIT SST_EXC_CHECK_ALICE_EXIT__enum,SST_EXC_CHECK_ALICE_EXIT_size

// SST_EXC_RESTORE_CALLSTACK_ENTER
#define SST_EXC_RESTORE_CALLSTACK_ENTER_size ""
#define SST_EXC_RESTORE_CALLSTACK_ENTER SST_EXC_RESTORE_CALLSTACK_ENTER__enum,SST_EXC_RESTORE_CALLSTACK_ENTER_size

// SST_EXC_RESTORE_CALLSTACK_EXIT
#define SST_EXC_RESTORE_CALLSTACK_EXIT_size ""
#define SST_EXC_RESTORE_CALLSTACK_EXIT SST_EXC_RESTORE_CALLSTACK_EXIT__enum,SST_EXC_RESTORE_CALLSTACK_EXIT_size

// SST_EXC_RESTORE_CALLSTACK_LOOP
#define SST_EXC_RESTORE_CALLSTACK_LOOP_size "dddd"
#define SST_EXC_RESTORE_CALLSTACK_LOOP SST_EXC_RESTORE_CALLSTACK_LOOP__enum,SST_EXC_RESTORE_CALLSTACK_LOOP_size

// SST_EXC_VFP_REGISTER_DUMP_ENTER
#define SST_EXC_VFP_REGISTER_DUMP_ENTER_size ""
#define SST_EXC_VFP_REGISTER_DUMP_ENTER SST_EXC_VFP_REGISTER_DUMP_ENTER__enum,SST_EXC_VFP_REGISTER_DUMP_ENTER_size

// SST_EXC_VFP_REGISTER_DUMP_EXIT
#define SST_EXC_VFP_REGISTER_DUMP_EXIT_size ""
#define SST_EXC_VFP_REGISTER_DUMP_EXIT SST_EXC_VFP_REGISTER_DUMP_EXIT__enum,SST_EXC_VFP_REGISTER_DUMP_EXIT_size

// SST_EXC_CLEAR_PENDING_LOG_ENTER
#define SST_EXC_CLEAR_PENDING_LOG_ENTER_size ""
#define SST_EXC_CLEAR_PENDING_LOG_ENTER SST_EXC_CLEAR_PENDING_LOG_ENTER__enum,SST_EXC_CLEAR_PENDING_LOG_ENTER_size

// SST_EXC_CLEAR_PENDING_LOG_EXIT
#define SST_EXC_CLEAR_PENDING_LOG_EXIT_size ""
#define SST_EXC_CLEAR_PENDING_LOG_EXIT SST_EXC_CLEAR_PENDING_LOG_EXIT__enum,SST_EXC_CLEAR_PENDING_LOG_EXIT_size

// SST_EXC_OUTPUT_DSP_LOG_ENTER
#define SST_EXC_OUTPUT_DSP_LOG_ENTER_size ""
#define SST_EXC_OUTPUT_DSP_LOG_ENTER SST_EXC_OUTPUT_DSP_LOG_ENTER__enum,SST_EXC_OUTPUT_DSP_LOG_ENTER_size

// SST_EXC_OUTPUT_DSP_LOG_EXIT
#define SST_EXC_OUTPUT_DSP_LOG_EXIT_size ""
#define SST_EXC_OUTPUT_DSP_LOG_EXIT SST_EXC_OUTPUT_DSP_LOG_EXIT__enum,SST_EXC_OUTPUT_DSP_LOG_EXIT_size

// SST_EXC_OUTPUT_EXC_MSG_ENTER
#define SST_EXC_OUTPUT_EXC_MSG_ENTER_size ""
#define SST_EXC_OUTPUT_EXC_MSG_ENTER SST_EXC_OUTPUT_EXC_MSG_ENTER__enum,SST_EXC_OUTPUT_EXC_MSG_ENTER_size

// SST_EXC_OUTPUT_EXC_MSG_EXIT
#define SST_EXC_OUTPUT_EXC_MSG_EXIT_size ""
#define SST_EXC_OUTPUT_EXC_MSG_EXIT SST_EXC_OUTPUT_EXC_MSG_EXIT__enum,SST_EXC_OUTPUT_EXC_MSG_EXIT_size

// SST_EXC_INVOKE_SST_ENGINE_ENTER
#define SST_EXC_INVOKE_SST_ENGINE_ENTER_size ""
#define SST_EXC_INVOKE_SST_ENGINE_ENTER SST_EXC_INVOKE_SST_ENGINE_ENTER__enum,SST_EXC_INVOKE_SST_ENGINE_ENTER_size

// SST_EXC_INVOKE_SST_ENGINE_EXIT
#define SST_EXC_INVOKE_SST_ENGINE_EXIT_size ""
#define SST_EXC_INVOKE_SST_ENGINE_EXIT SST_EXC_INVOKE_SST_ENGINE_EXIT__enum,SST_EXC_INVOKE_SST_ENGINE_EXIT_size

// SST_EXC_LCD_DISPLAY_ENTER
#define SST_EXC_LCD_DISPLAY_ENTER_size ""
#define SST_EXC_LCD_DISPLAY_ENTER SST_EXC_LCD_DISPLAY_ENTER__enum,SST_EXC_LCD_DISPLAY_ENTER_size

// SST_EXC_LCD_DISPLAY_EXIT
#define SST_EXC_LCD_DISPLAY_EXIT_size ""
#define SST_EXC_LCD_DISPLAY_EXIT SST_EXC_LCD_DISPLAY_EXIT__enum,SST_EXC_LCD_DISPLAY_EXIT_size

// SST_EXC_INIT_DEBUG_PRINT_ENTER
#define SST_EXC_INIT_DEBUG_PRINT_ENTER_size ""
#define SST_EXC_INIT_DEBUG_PRINT_ENTER SST_EXC_INIT_DEBUG_PRINT_ENTER__enum,SST_EXC_INIT_DEBUG_PRINT_ENTER_size

// SST_EXC_INIT_DEBUG_PRINT_EXIT
#define SST_EXC_INIT_DEBUG_PRINT_EXIT_size ""
#define SST_EXC_INIT_DEBUG_PRINT_EXIT SST_EXC_INIT_DEBUG_PRINT_EXIT__enum,SST_EXC_INIT_DEBUG_PRINT_EXIT_size

// SST_EXC_DSP_DISPLAY_ENTER
#define SST_EXC_DSP_DISPLAY_ENTER_size ""
#define SST_EXC_DSP_DISPLAY_ENTER SST_EXC_DSP_DISPLAY_ENTER__enum,SST_EXC_DSP_DISPLAY_ENTER_size

// SST_EXC_DSP_DISPLAY_EXIT
#define SST_EXC_DSP_DISPLAY_EXIT_size ""
#define SST_EXC_DSP_DISPLAY_EXIT SST_EXC_DSP_DISPLAY_EXIT__enum,SST_EXC_DSP_DISPLAY_EXIT_size

// SST_EXC_DEBUG_PRINT_ENTER
#define SST_EXC_DEBUG_PRINT_ENTER_size ""
#define SST_EXC_DEBUG_PRINT_ENTER SST_EXC_DEBUG_PRINT_ENTER__enum,SST_EXC_DEBUG_PRINT_ENTER_size

// SST_EXC_DEBUG_PRINT_EXIT
#define SST_EXC_DEBUG_PRINT_EXIT_size ""
#define SST_EXC_DEBUG_PRINT_EXIT SST_EXC_DEBUG_PRINT_EXIT__enum,SST_EXC_DEBUG_PRINT_EXIT_size

// SST_EXC_LCD_DISPLAY_DSP_LOG_ENTER
#define SST_EXC_LCD_DISPLAY_DSP_LOG_ENTER_size ""
#define SST_EXC_LCD_DISPLAY_DSP_LOG_ENTER SST_EXC_LCD_DISPLAY_DSP_LOG_ENTER__enum,SST_EXC_LCD_DISPLAY_DSP_LOG_ENTER_size

// SST_EXC_LCD_DISPLAY_DSP_LOG_EXIT
#define SST_EXC_LCD_DISPLAY_DSP_LOG_EXIT_size ""
#define SST_EXC_LCD_DISPLAY_DSP_LOG_EXIT SST_EXC_LCD_DISPLAY_DSP_LOG_EXIT__enum,SST_EXC_LCD_DISPLAY_DSP_LOG_EXIT_size

// SST_EXC_OUTPUT_EXCEPTION_RECORD_ENTER
#define SST_EXC_OUTPUT_EXCEPTION_RECORD_ENTER_size ""
#define SST_EXC_OUTPUT_EXCEPTION_RECORD_ENTER SST_EXC_OUTPUT_EXCEPTION_RECORD_ENTER__enum,SST_EXC_OUTPUT_EXCEPTION_RECORD_ENTER_size

// SST_EXC_OUTPUT_EXCEPTION_RECORD_EXIT
#define SST_EXC_OUTPUT_EXCEPTION_RECORD_EXIT_size ""
#define SST_EXC_OUTPUT_EXCEPTION_RECORD_EXIT SST_EXC_OUTPUT_EXCEPTION_RECORD_EXIT__enum,SST_EXC_OUTPUT_EXCEPTION_RECORD_EXIT_size

// SST_EXC_PASS_CCCI_EXCINFO_ENTER
#define SST_EXC_PASS_CCCI_EXCINFO_ENTER_size ""
#define SST_EXC_PASS_CCCI_EXCINFO_ENTER SST_EXC_PASS_CCCI_EXCINFO_ENTER__enum,SST_EXC_PASS_CCCI_EXCINFO_ENTER_size

// SST_EXC_PASS_CCCI_EXCINFO_EXIT
#define SST_EXC_PASS_CCCI_EXCINFO_EXIT_size ""
#define SST_EXC_PASS_CCCI_EXCINFO_EXIT SST_EXC_PASS_CCCI_EXCINFO_EXIT__enum,SST_EXC_PASS_CCCI_EXCINFO_EXIT_size

// SST_EXC_FLC_DEBUG_INFO_ENTER
#define SST_EXC_FLC_DEBUG_INFO_ENTER_size ""
#define SST_EXC_FLC_DEBUG_INFO_ENTER SST_EXC_FLC_DEBUG_INFO_ENTER__enum,SST_EXC_FLC_DEBUG_INFO_ENTER_size

// SST_EXC_FLC_DEBUG_INFO_EXIT
#define SST_EXC_FLC_DEBUG_INFO_EXIT_size ""
#define SST_EXC_FLC_DEBUG_INFO_EXIT SST_EXC_FLC_DEBUG_INFO_EXIT__enum,SST_EXC_FLC_DEBUG_INFO_EXIT_size

// SST_EXC_INIT_FDD_TABLE_ENTER
#define SST_EXC_INIT_FDD_TABLE_ENTER_size ""
#define SST_EXC_INIT_FDD_TABLE_ENTER SST_EXC_INIT_FDD_TABLE_ENTER__enum,SST_EXC_INIT_FDD_TABLE_ENTER_size

// SST_EXC_INIT_FDD_TABLE_EXIT
#define SST_EXC_INIT_FDD_TABLE_EXIT_size ""
#define SST_EXC_INIT_FDD_TABLE_EXIT SST_EXC_INIT_FDD_TABLE_EXIT__enum,SST_EXC_INIT_FDD_TABLE_EXIT_size

// SST_EXC_SAVE_EXCEPTION_RECORD_ENTER
#define SST_EXC_SAVE_EXCEPTION_RECORD_ENTER_size ""
#define SST_EXC_SAVE_EXCEPTION_RECORD_ENTER SST_EXC_SAVE_EXCEPTION_RECORD_ENTER__enum,SST_EXC_SAVE_EXCEPTION_RECORD_ENTER_size

// SST_EXC_SAVE_EXCEPTION_RECORD_EXIT
#define SST_EXC_SAVE_EXCEPTION_RECORD_EXIT_size ""
#define SST_EXC_SAVE_EXCEPTION_RECORD_EXIT SST_EXC_SAVE_EXCEPTION_RECORD_EXIT__enum,SST_EXC_SAVE_EXCEPTION_RECORD_EXIT_size

// SST_EXC_FS_UNLOCK_ALL_ENTER
#define SST_EXC_FS_UNLOCK_ALL_ENTER_size ""
#define SST_EXC_FS_UNLOCK_ALL_ENTER SST_EXC_FS_UNLOCK_ALL_ENTER__enum,SST_EXC_FS_UNLOCK_ALL_ENTER_size

// SST_EXC_FS_UNLOCK_ALL_EXIT
#define SST_EXC_FS_UNLOCK_ALL_EXIT_size ""
#define SST_EXC_FS_UNLOCK_ALL_EXIT SST_EXC_FS_UNLOCK_ALL_EXIT__enum,SST_EXC_FS_UNLOCK_ALL_EXIT_size

// SST_EXC_FS_SHUTDOWN_ENTER
#define SST_EXC_FS_SHUTDOWN_ENTER_size ""
#define SST_EXC_FS_SHUTDOWN_ENTER SST_EXC_FS_SHUTDOWN_ENTER__enum,SST_EXC_FS_SHUTDOWN_ENTER_size

// SST_EXC_FS_SHUTDOWN_EXIT
#define SST_EXC_FS_SHUTDOWN_EXIT_size ""
#define SST_EXC_FS_SHUTDOWN_EXIT SST_EXC_FS_SHUTDOWN_EXIT__enum,SST_EXC_FS_SHUTDOWN_EXIT_size

// SST_EXC_NVRAM_WRITE_EXC_ENTER
#define SST_EXC_NVRAM_WRITE_EXC_ENTER_size ""
#define SST_EXC_NVRAM_WRITE_EXC_ENTER SST_EXC_NVRAM_WRITE_EXC_ENTER__enum,SST_EXC_NVRAM_WRITE_EXC_ENTER_size

// SST_EXC_NVRAM_WRITE_EXC_EXIT
#define SST_EXC_NVRAM_WRITE_EXC_EXIT_size ""
#define SST_EXC_NVRAM_WRITE_EXC_EXIT SST_EXC_NVRAM_WRITE_EXC_EXIT__enum,SST_EXC_NVRAM_WRITE_EXC_EXIT_size

// SST_EXC_TST_DUMP2FILE_ENTER
#define SST_EXC_TST_DUMP2FILE_ENTER_size ""
#define SST_EXC_TST_DUMP2FILE_ENTER SST_EXC_TST_DUMP2FILE_ENTER__enum,SST_EXC_TST_DUMP2FILE_ENTER_size

// SST_EXC_TST_DUMP2FILE_EXIT
#define SST_EXC_TST_DUMP2FILE_EXIT_size ""
#define SST_EXC_TST_DUMP2FILE_EXIT SST_EXC_TST_DUMP2FILE_EXIT__enum,SST_EXC_TST_DUMP2FILE_EXIT_size

// SST_EXC_INIT_BBREG_DUMP_ENTER
#define SST_EXC_INIT_BBREG_DUMP_ENTER_size ""
#define SST_EXC_INIT_BBREG_DUMP_ENTER SST_EXC_INIT_BBREG_DUMP_ENTER__enum,SST_EXC_INIT_BBREG_DUMP_ENTER_size

// SST_EXC_INIT_BBREG_DUMP_EXIT
#define SST_EXC_INIT_BBREG_DUMP_EXIT_size ""
#define SST_EXC_INIT_BBREG_DUMP_EXIT SST_EXC_INIT_BBREG_DUMP_EXIT__enum,SST_EXC_INIT_BBREG_DUMP_EXIT_size

// SST_EXC_DUMP_USB_DEBUG_DATA_ENTER
#define SST_EXC_DUMP_USB_DEBUG_DATA_ENTER_size ""
#define SST_EXC_DUMP_USB_DEBUG_DATA_ENTER SST_EXC_DUMP_USB_DEBUG_DATA_ENTER__enum,SST_EXC_DUMP_USB_DEBUG_DATA_ENTER_size

// SST_EXC_DUMP_USB_DEBUG_DATA_EXIT
#define SST_EXC_DUMP_USB_DEBUG_DATA_EXIT_size ""
#define SST_EXC_DUMP_USB_DEBUG_DATA_EXIT SST_EXC_DUMP_USB_DEBUG_DATA_EXIT__enum,SST_EXC_DUMP_USB_DEBUG_DATA_EXIT_size

// SST_EXC_SYSMEM_TO_BE_DUMPED
#define SST_EXC_SYSMEM_TO_BE_DUMPED_size "ddd"
#define SST_EXC_SYSMEM_TO_BE_DUMPED SST_EXC_SYSMEM_TO_BE_DUMPED__enum,SST_EXC_SYSMEM_TO_BE_DUMPED_size

// SST_EXC_HANDOVER2TST
#define SST_EXC_HANDOVER2TST_size ""
#define SST_EXC_HANDOVER2TST SST_EXC_HANDOVER2TST__enum,SST_EXC_HANDOVER2TST_size

// SST_EXC_READY2REBOOT
#define SST_EXC_READY2REBOOT_size ""
#define SST_EXC_READY2REBOOT SST_EXC_READY2REBOOT__enum,SST_EXC_READY2REBOOT_size

// SST_EXC_BBREG_DUMP_COUNT
#define SST_EXC_BBREG_DUMP_COUNT_size "d"
#define SST_EXC_BBREG_DUMP_COUNT SST_EXC_BBREG_DUMP_COUNT__enum,SST_EXC_BBREG_DUMP_COUNT_size

// SST_EXC_BBREG_DUMP_OWNER
#define SST_EXC_BBREG_DUMP_OWNER_size "cccccccccccccccc"
#define SST_EXC_BBREG_DUMP_OWNER SST_EXC_BBREG_DUMP_OWNER__enum,SST_EXC_BBREG_DUMP_OWNER_size

// SST_EXC_BBREG_DUMP_CALLBACK_FUNC_ENTER
#define SST_EXC_BBREG_DUMP_CALLBACK_FUNC_ENTER_size "d"
#define SST_EXC_BBREG_DUMP_CALLBACK_FUNC_ENTER SST_EXC_BBREG_DUMP_CALLBACK_FUNC_ENTER__enum,SST_EXC_BBREG_DUMP_CALLBACK_FUNC_ENTER_size

// SST_EXC_BBREG_DUMP_CALLBACK_FUNC_EXIT
#define SST_EXC_BBREG_DUMP_CALLBACK_FUNC_EXIT_size "d"
#define SST_EXC_BBREG_DUMP_CALLBACK_FUNC_EXIT SST_EXC_BBREG_DUMP_CALLBACK_FUNC_EXIT__enum,SST_EXC_BBREG_DUMP_CALLBACK_FUNC_EXIT_size

// SST_EXC_BBREG_DUMP_SKIP
#define SST_EXC_BBREG_DUMP_SKIP_size ""
#define SST_EXC_BBREG_DUMP_SKIP SST_EXC_BBREG_DUMP_SKIP__enum,SST_EXC_BBREG_DUMP_SKIP_size

// SST_EXC_BBREG_DUMP_TO_BE_DUMPED
#define SST_EXC_BBREG_DUMP_TO_BE_DUMPED_size "dddd"
#define SST_EXC_BBREG_DUMP_TO_BE_DUMPED SST_EXC_BBREG_DUMP_TO_BE_DUMPED__enum,SST_EXC_BBREG_DUMP_TO_BE_DUMPED_size

// TST_EX_MSG_DUMP_UART_RING_BUFFER_START
#define TST_EX_MSG_DUMP_UART_RING_BUFFER_START_size "d"
#define TST_EX_MSG_DUMP_UART_RING_BUFFER_START TST_EX_MSG_DUMP_UART_RING_BUFFER_START__enum,TST_EX_MSG_DUMP_UART_RING_BUFFER_START_size

// TST_EX_MSG_DUMP_UART_RING_BUFFER_END
#define TST_EX_MSG_DUMP_UART_RING_BUFFER_END_size "d"
#define TST_EX_MSG_DUMP_UART_RING_BUFFER_END TST_EX_MSG_DUMP_UART_RING_BUFFER_END__enum,TST_EX_MSG_DUMP_UART_RING_BUFFER_END_size

// TST_EX_MSG_DISABLE_LGA_BUF_UNDER_SS_START
#define TST_EX_MSG_DISABLE_LGA_BUF_UNDER_SS_START_size ""
#define TST_EX_MSG_DISABLE_LGA_BUF_UNDER_SS_START TST_EX_MSG_DISABLE_LGA_BUF_UNDER_SS_START__enum,TST_EX_MSG_DISABLE_LGA_BUF_UNDER_SS_START_size

// TST_EX_MSG_DISABLE_LGA_BUF_UNDER_SS_END
#define TST_EX_MSG_DISABLE_LGA_BUF_UNDER_SS_END_size ""
#define TST_EX_MSG_DISABLE_LGA_BUF_UNDER_SS_END TST_EX_MSG_DISABLE_LGA_BUF_UNDER_SS_END__enum,TST_EX_MSG_DISABLE_LGA_BUF_UNDER_SS_END_size

// TST_EX_MSG_CLEAN_UART_UNDER_SS_START
#define TST_EX_MSG_CLEAN_UART_UNDER_SS_START_size "d"
#define TST_EX_MSG_CLEAN_UART_UNDER_SS_START TST_EX_MSG_CLEAN_UART_UNDER_SS_START__enum,TST_EX_MSG_CLEAN_UART_UNDER_SS_START_size

// TST_EX_MSG_CLEAN_UART_UNDER_SS_END
#define TST_EX_MSG_CLEAN_UART_UNDER_SS_END_size "d"
#define TST_EX_MSG_CLEAN_UART_UNDER_SS_END TST_EX_MSG_CLEAN_UART_UNDER_SS_END__enum,TST_EX_MSG_CLEAN_UART_UNDER_SS_END_size

// TST_EX_MSG_DUMP_PS_BUF_START
#define TST_EX_MSG_DUMP_PS_BUF_START_size ""
#define TST_EX_MSG_DUMP_PS_BUF_START TST_EX_MSG_DUMP_PS_BUF_START__enum,TST_EX_MSG_DUMP_PS_BUF_START_size

// TST_EX_MSG_DUMP_PS_BUF_END
#define TST_EX_MSG_DUMP_PS_BUF_END_size ""
#define TST_EX_MSG_DUMP_PS_BUF_END TST_EX_MSG_DUMP_PS_BUF_END__enum,TST_EX_MSG_DUMP_PS_BUF_END_size

// TST_EX_MSG_DISABLE_LGA_BUF_START
#define TST_EX_MSG_DISABLE_LGA_BUF_START_size ""
#define TST_EX_MSG_DISABLE_LGA_BUF_START TST_EX_MSG_DISABLE_LGA_BUF_START__enum,TST_EX_MSG_DISABLE_LGA_BUF_START_size

// TST_EX_MSG_DISABLE_LGA_BUF_END
#define TST_EX_MSG_DISABLE_LGA_BUF_END_size ""
#define TST_EX_MSG_DISABLE_LGA_BUF_END TST_EX_MSG_DISABLE_LGA_BUF_END__enum,TST_EX_MSG_DISABLE_LGA_BUF_END_size

// TST_EX_MSG_REOPEN_PORT_START
#define TST_EX_MSG_REOPEN_PORT_START_size ""
#define TST_EX_MSG_REOPEN_PORT_START TST_EX_MSG_REOPEN_PORT_START__enum,TST_EX_MSG_REOPEN_PORT_START_size

// TST_EX_MSG_REOPEN_PORT_END
#define TST_EX_MSG_REOPEN_PORT_END_size ""
#define TST_EX_MSG_REOPEN_PORT_END TST_EX_MSG_REOPEN_PORT_END__enum,TST_EX_MSG_REOPEN_PORT_END_size

// TST_EX_MSG_OPEN_PORT_START
#define TST_EX_MSG_OPEN_PORT_START_size "d"
#define TST_EX_MSG_OPEN_PORT_START TST_EX_MSG_OPEN_PORT_START__enum,TST_EX_MSG_OPEN_PORT_START_size

// TST_EX_MSG_OPEN_PORT_END
#define TST_EX_MSG_OPEN_PORT_END_size "d"
#define TST_EX_MSG_OPEN_PORT_END TST_EX_MSG_OPEN_PORT_END__enum,TST_EX_MSG_OPEN_PORT_END_size

// TST_EX_MSG_CLEAN_UART_START
#define TST_EX_MSG_CLEAN_UART_START_size "d"
#define TST_EX_MSG_CLEAN_UART_START TST_EX_MSG_CLEAN_UART_START__enum,TST_EX_MSG_CLEAN_UART_START_size

// TST_EX_MSG_CLEAN_UART_END
#define TST_EX_MSG_CLEAN_UART_END_size "d"
#define TST_EX_MSG_CLEAN_UART_END TST_EX_MSG_CLEAN_UART_END__enum,TST_EX_MSG_CLEAN_UART_END_size

// TST_EX_MSG_CLOSE_PORT_START
#define TST_EX_MSG_CLOSE_PORT_START_size "d"
#define TST_EX_MSG_CLOSE_PORT_START TST_EX_MSG_CLOSE_PORT_START__enum,TST_EX_MSG_CLOSE_PORT_START_size

// TST_EX_MSG_CLOSE_PORT_END
#define TST_EX_MSG_CLOSE_PORT_END_size "d"
#define TST_EX_MSG_CLOSE_PORT_END TST_EX_MSG_CLOSE_PORT_END__enum,TST_EX_MSG_CLOSE_PORT_END_size

// TST_EX_MSG_CHANGE_L1_PORT
#define TST_EX_MSG_CHANGE_L1_PORT_size "dd"
#define TST_EX_MSG_CHANGE_L1_PORT TST_EX_MSG_CHANGE_L1_PORT__enum,TST_EX_MSG_CHANGE_L1_PORT_size

// TST_EX_MSG_NESTED_EX_DETECTED
#define TST_EX_MSG_NESTED_EX_DETECTED_size "d"
#define TST_EX_MSG_NESTED_EX_DETECTED TST_EX_MSG_NESTED_EX_DETECTED__enum,TST_EX_MSG_NESTED_EX_DETECTED_size

// TST_EX_MSG_DUMP_SST_LOG_START
#define TST_EX_MSG_DUMP_SST_LOG_START_size ""
#define TST_EX_MSG_DUMP_SST_LOG_START TST_EX_MSG_DUMP_SST_LOG_START__enum,TST_EX_MSG_DUMP_SST_LOG_START_size

// TST_EX_MSG_DUMP_SST_LOG_END
#define TST_EX_MSG_DUMP_SST_LOG_END_size ""
#define TST_EX_MSG_DUMP_SST_LOG_END TST_EX_MSG_DUMP_SST_LOG_END__enum,TST_EX_MSG_DUMP_SST_LOG_END_size

// TST_EX_MSG_DRV_EX_HANDLER_START
#define TST_EX_MSG_DRV_EX_HANDLER_START_size ""
#define TST_EX_MSG_DRV_EX_HANDLER_START TST_EX_MSG_DRV_EX_HANDLER_START__enum,TST_EX_MSG_DRV_EX_HANDLER_START_size

// TST_EX_MSG_DRV_EX_HANDLER_END
#define TST_EX_MSG_DRV_EX_HANDLER_END_size ""
#define TST_EX_MSG_DRV_EX_HANDLER_END TST_EX_MSG_DRV_EX_HANDLER_END__enum,TST_EX_MSG_DRV_EX_HANDLER_END_size

// TST_EX_MSG_DUMP_LGA_BUF_START
#define TST_EX_MSG_DUMP_LGA_BUF_START_size ""
#define TST_EX_MSG_DUMP_LGA_BUF_START TST_EX_MSG_DUMP_LGA_BUF_START__enum,TST_EX_MSG_DUMP_LGA_BUF_START_size

// TST_EX_MSG_DUMP_LGA_BUF_END
#define TST_EX_MSG_DUMP_LGA_BUF_END_size ""
#define TST_EX_MSG_DUMP_LGA_BUF_END TST_EX_MSG_DUMP_LGA_BUF_END__enum,TST_EX_MSG_DUMP_LGA_BUF_END_size

// TST_EX_MSG_REDUMP_PS_BUF_START
#define TST_EX_MSG_REDUMP_PS_BUF_START_size ""
#define TST_EX_MSG_REDUMP_PS_BUF_START TST_EX_MSG_REDUMP_PS_BUF_START__enum,TST_EX_MSG_REDUMP_PS_BUF_START_size

// TST_EX_MSG_REDUMP_PS_BUF_END
#define TST_EX_MSG_REDUMP_PS_BUF_END_size ""
#define TST_EX_MSG_REDUMP_PS_BUF_END TST_EX_MSG_REDUMP_PS_BUF_END__enum,TST_EX_MSG_REDUMP_PS_BUF_END_size

// TST_EX_MSG_REDUMP_L1_BUF_START
#define TST_EX_MSG_REDUMP_L1_BUF_START_size ""
#define TST_EX_MSG_REDUMP_L1_BUF_START TST_EX_MSG_REDUMP_L1_BUF_START__enum,TST_EX_MSG_REDUMP_L1_BUF_START_size

// TST_EX_MSG_REDUMP_L1_BUF_END
#define TST_EX_MSG_REDUMP_L1_BUF_END_size ""
#define TST_EX_MSG_REDUMP_L1_BUF_END TST_EX_MSG_REDUMP_L1_BUF_END__enum,TST_EX_MSG_REDUMP_L1_BUF_END_size

// TST_EX_MSG_GET_CATCHER_CMD
#define TST_EX_MSG_GET_CATCHER_CMD_size "d"
#define TST_EX_MSG_GET_CATCHER_CMD TST_EX_MSG_GET_CATCHER_CMD__enum,TST_EX_MSG_GET_CATCHER_CMD_size

// TST_EX_MSG_GET_CATCHER_CMD_CHECKSUM_ERROR
#define TST_EX_MSG_GET_CATCHER_CMD_CHECKSUM_ERROR_size "ddd"
#define TST_EX_MSG_GET_CATCHER_CMD_CHECKSUM_ERROR TST_EX_MSG_GET_CATCHER_CMD_CHECKSUM_ERROR__enum,TST_EX_MSG_GET_CATCHER_CMD_CHECKSUM_ERROR_size


#endif // SST_TRC_GEN.H