dcl_pmu6250_hw.h 6.7 KB
/*****************************************************************************
*  Copyright Statement:
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*
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*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
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*****************************************************************************/

/*****************************************************************************
 *
 * Filename:
 * ---------
 *    dcl_pmu6250_hw.h
 *
 * Project:
 * --------
 *   Maui_Software
 *
 * Description:
 * ------------
 *   This file is intended for PMU 6250 driver.
 *
 * Author:
 * -------
 * -------
 *
 *============================================================================
 *             HISTORY
 * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
 *------------------------------------------------------------------------------
 * removed!
 * removed!
 * removed!
 *
 * removed!
 * removed!
 * removed!
 * removed!
 *
 *------------------------------------------------------------------------------
 * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
 *============================================================================
 ****************************************************************************/

#ifndef __PMU6250_HW_H__
#define __PMU6250_HW_H__


#if defined(PMU_6250_REG_API)

#define MIXED_BASE_ADDR            PMU_base

#define MIXED_BASE_ADDR_END        (MIXED_BASE_ADDR + 0x1000)

#include "dcl_mixedsys6250_reg.h"

/* Special Commands */

// LDO Commands
// LDO_CON0
#define LDO_BUCK_EN_OFFSET          	CON0_MIXED_OFFSET
#define LDO_BUCK_EN_MASK               	0x0001
#define LDO_BUCK_EN_SHIFT              	0

#define LDO_BUCK_ON_SEL_OFFSET     		CON0_MIXED_OFFSET
#define LDO_BUCK_ON_SEL_MASK            0x0002
#define LDO_BUCK_ON_SEL_SHIFT           1

#define LDO_BUCK_RS_OFFSET				CON0_MIXED_OFFSET
#define LDO_BUCK_RS_MASK               	0x0004
#define LDO_BUCK_RS_SHIFT              	2

#define LDO_BUCK_VOL_SEL_OFFSET			CON0_MIXED_OFFSET // For VCAMA, VCAMD, VSIM1, VSIM2, VIBR, VMC, VSF, VCORE
#define LDO_BUCK_VOL_SEL_MASK          	0x01F0
#define LDO_BUCK_VOL_SEL_SHIFT         	4

#define LDO_BUCK_NDIS_EN_OFFSET			CON0_MIXED_OFFSET
#define LDO_BUCK_NDIS_EN_MASK          	0x0400
#define LDO_BUCK_NDIS_EN_SHIFT         	10

#define LDO_BUCK_STB_SEL_OFFSET			CON0_MIXED_OFFSET
#define LDO_BUCK_STB_SEL_MASK          	0x0800
#define LDO_BUCK_STB_SEL_SHIFT         	11

#define LDO_BUCK_OC_AUTO_OFF_OFFSET 	CON0_MIXED_OFFSET
#define LDO_BUCK_OC_AUTO_OFF_MASK      	0x1000
#define LDO_BUCK_OC_AUTO_OFF_SHIFT     	12

#define LDO_BUCK_OCFB_EN_OFFSET			CON0_MIXED_OFFSET
#define LDO_BUCK_OCFB_EN_MASK          	0x2000
#define LDO_BUCK_OCFB_EN_SHIFT         	13

#define LDO_BUCK_OC_FLAG_OFFSET			CON0_MIXED_OFFSET
#define LDO_BUCK_OC_FLAG_MASK          	0x4000
#define LDO_BUCK_OC_FLAG_SHIFT         	14

#define LDO_BUCK_STATUS_OFFSET			CON0_MIXED_OFFSET
#define LDO_BUCK_STATUS_MASK          	0x8000
#define LDO_BUCK_STATUS_SHIFT         	15

// LDO_CON1
#define LDO_CAL_OFFSET					CON1_MIXED_OFFSET
#define LDO_CAL_MASK              		0x00F0
#define LDO_CAL_SHIFT             		4

// LDO_CON2
#define LDO_OC_TD_OFFSET		        CON2_MIXED_OFFSET
#define LDO_OC_TD_MASK                  0x0030
#define LDO_OC_TD_SHIFT                 4

#define LDO_STB_TD_OFFSET		        CON2_MIXED_OFFSET
#define LDO_STB_TD_MASK                 0x00C0
#define LDO_STB_TD_SHIFT                6

// BUCK Commands
#define BUCK_VOSEL_SLEEP_OFFSET	        CON3_MIXED_OFFSET
#define BUCK_VOSEL_SLEEP_MASK           0x01F0
#define BUCK_VOSEL_SLEEP_SHIFT          4

#define BUCK_SFSTREN_OFFSET		        CON3_MIXED_OFFSET
#define BUCK_SFSTREN_MASK               0x0008
#define BUCK_SFSTREN_SHIFT              3

// CHR Commands
#define ADC_EN_OFFSET		            CON10_MIXED_OFFSET
#define ADC_EN_MASK                     0x0070   // All ADC channels are enabled at same time
#define ADC_EN_SHIFT                    4

// ISINK Commands
// ISINK_CON0
#define ISINK_EN_OFFSET					CON0_MIXED_OFFSET
#define ISINK_EN_MASK             		0x0001
#define ISINK_EN_SHIFT            		0

#define ISINK_MODE_OFFSET				CON0_MIXED_OFFSET
#define ISINK_MODE_MASK           		0x0002
#define ISINK_MODE_SHIFT          		1

#define ISINK_CHOP_ENB_OFFSET           CON0_MIXED_OFFSET
#define ISINK_CHOP_ENB_MASK             0x0004
#define ISINK_CHOP_ENB_SHIFT            2

#define ISINK_STEP_OFFSET				CON0_MIXED_OFFSET
#define ISINK_STEP_MASK           		0x0070
#define ISINK_STEP_SHIFT          		4

#define ISINK_CLKSEL_MODE_OFFSET        CON0_MIXED_OFFSET
#define ISINK_CLKSEL_MODE_MASK          0x1000
#define ISINK_CLKSEL_MODE_SHIFT         12

#define ISINK_CLKSEL_OFFSET             CON0_MIXED_OFFSET
#define ISINK_CLKSEL_MASK               0x2000
#define ISINK_CLKSEL_SHIFT              13

#define ISINK_STATUS_OFFSET				CON0_MIXED_OFFSET
#define ISINK_STATUS_MASK           	0x8000
#define ISINK_STATUS_SHIFT          	15

#endif // #if defined(PMU_6250_REG_API)

#endif // #ifndef __PMU6250_HW_H__