usb_hw.h
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/*****************************************************************************
* Copyright Statement:
* --------------------
* This software is protected by Copyright and the information contained
* herein is confidential. The software may not be copied and the information
* contained herein may not be used or disclosed except with the written
* permission of MediaTek Inc. (C) 2005
*
* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
*
* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
*
* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
*
*****************************************************************************/
/*****************************************************************************
*
* Filename:
* ---------
* usb_hw.h
*
* Project:
* --------
* Maui_Software
*
* Description:
* ------------
* This file intends for usb hardware register definitions
*
* Author:
* -------
* -------
*
*==============================================================================
* HISTORY
* Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
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*============================================================================
****************************************************************************/
#ifndef USB_HW_H
#define USB_HW_H
#include "reg_base.h"
#include "drv_features.h"
/* USB Controller */
#if (defined(DRV_USB_IP_V4)) //Unit IP
#define USB_FADDR (USB_base+0x00) /* RW */
#define USB_POWER (USB_base+0x01)
#define USB_INTRTX (USB_base+0x02) /* 16-bit, status, read only */
#define USB_INTRRX (USB_base+0x04) /* 16-bit, status, read only */
#define USB_INTRTXE (USB_base+0x06) /* 16-bit, RW */
#define USB_INTRRXE (USB_base+0x08) /* 16-bit, RW */
#define USB_INTRUSB (USB_base+0x0A) /* 8-bit, status, read only*/
#define USB_INTRUSBE (USB_base+0x0B) /* 8-bit, RW */
#define USB_FRAME (USB_base+0x0C) /* 16-bit, read only */ /*Max Frame length = 11 bits*/
#define USB_INDEX (USB_base+0x0E) /* RW, 4bit available*/
#define USB_TESTMODE (USB_base+0x0F) /* RW, 8-bit */
#define USB_CSR0 (USB_base+0x12) /* 16-bit */
#define USB_COUNT0 (USB_base+0x18) /* RO, EP0 only*/
#define USB_NAKLIMIT0 (USB_base+0x1B) /* RW, host mode only*/
#define USB_TXMAXP (USB_base+0x10) /* 16-bit, RW*/
#define USB_TXCSR (USB_base+0x12)
#define USB_RXMAXP (USB_base+0x14) /* 16-bit, RW*/
#define USB_RXCSR (USB_base+0x16)
#define USB_RXCOUNT (USB_base+0x18) /* RO, 14bits */
#define USB_TXTYPE (USB_base+0x1A) /* RW, host mode only */
#define USB_TXINTERVAL (USB_base+0x1B) /* RW, host mode only */
#define USB_RXTYPE (USB_base+0x1C) /* RW, host mode only */
#define USB_RXINTERVAL (USB_base+0x1D) /* RW, host mode only */
#define USB_EP0 (USB_base+0x20) /* 4 byte as 1 queue */
#define USB_EP1 (USB_base+0x24)
#define USB_EP2 (USB_base+0x28)
#define USB_EP3 (USB_base+0x32)
#define USB_EP4 (USB_base+0x40)
#define USB_DEVCTL (USB_base+0x60) /* 8-bit */
#define USB_PWRUPCNT (USB_base+0x61) /* RW */
#define USB_TXFIFOSZ (USB_base+0x62) /* RW */
#define USB_RXFIFOSZ (USB_base+0x63) /* RW */
#define USB_TXFIFOADD (USB_base+0x64) /* RW */
#define USB_RXFIFOADD (USB_base+0x66) /* RW */
#define USB_BUSPERF1 (USB_base+0x70) /* RW */
#define USB_BUSPERF2 (USB_base+0x72) /* RW */
#define USB_BUSPERF3 (USB_base+0x74) /* RW */
#define USB_VPLEN (USB_base+0x7B) /* RW, 8-bits */
#define USB_RSTINFO (USB_base+0x7F) /* RW */
#define USB_L1INTS (USB_base+0xA0) /* RW */
#define USB_L1INTM (USB_base+0xA4) /* RW */
#define USB_L1INTP (USB_base+0xA8) /* RW */
#define USB_L1INTC (USB_base+0xAC) /* RW */
#define USB_EPn_TXCSR(_n) (USB_base+0x102+(0x10*(_n))) /* R */
#define USB_EPn_RXCSR(_n) (USB_base+0x106+(0x10*(_n))) /* R */
//#define USB_DMAINTR (USB_base+0x200) /* 8-bits, W0C */
#define USB_DMA_INTR_STATUS (USB_base+0x200) /* 8-bits, W1C */
#define USB_DMA_INTR_UNMASK (USB_base+0x201) /* 8-bits, R only */
#define USB_DMA_INTR_UNMASK_CLEAR (USB_base+0x202) /* 8-bits, W1S */
#define USB_DMA_INTR_UNMASK_SET (USB_base+0x203) /* 8-bits, W1S */
#define USB_DMALIMITER (USB_base+0x210) /* 8-bits, RW */
#define USB_DMA_CONFIG (USB_base+0x220) /* 8-bits, RW */
#define USB_DMACNTL(_n) (USB_base+0x1F4+(0x10*(_n))) /* RW, _n = 1~6 */
#define USB_DMAADDR(_n) (USB_base+0x1F8+(0x10*(_n))) /* RW, _n = 1~6 */
#define USB_DMACNT(_n) (USB_base+0x1FC+(0x10*(_n))) /* RW, _n = 1~6 */
#define USB_DMA_REALCNT(_n) (USB_base+0x270+(0x10*(_n))) /* RO, _n = 1~6, 32bits */
#define USB_DMA_TIMER(_n) (USB_base+0x274+(0x10*(_n))) /* RW, _n = 1~6, 16bits */
#define USB_RQPKTCOUNT(_n) (USB_base+0x300+(0x04*(_n))) /* RW, 16bits, _n = 1~3, host mode RX ep only */
#define USB_PSR_CTRL (USB_base+0x610) /* 32 bits access only */
#define USB_PSR_CTRL_2 (USB_base+0x614) /* 32 bits access only */
#define USB_DBG_PRB (USB_base+0x620) /* 32 bits access only */
#define USB_OPSTATE (USB_DRV_Reg32(USB_DBG_PRB)&USB_DBG_PRB_OPSTATE_MASK)
#define USB_LINE_STATE (USB_DRV_Reg32(USB_DBG_PRB)&USB_DBG_PRB_LINESTATE_MASK)
//DMAQ
#define USB_DMAQ_QCR0 (USB_base+0x800) //Queue Control Register 0 QCR0
#define USB_DMAQ_QCR1 (USB_base+0x804) //Queue Control Register 1 (wimax) QCR1
#define USB_DMAQ_QCR2 (USB_base+0x808) //Queue Control Register 2 QCR2
#define USB_DMAQ_QCR3 (USB_base+0x80C) //Queue Control Register 3 QCR3
#define USB_DMAQ_RQCSR0 (USB_base+0x810) //RX Queue Command and Status Register0 RQCSR0
#define USB_DMAQ_RQSAR0 (USB_base+0x814) //RX Queue Starting Address Register0 RQSAR0
#define USB_DMAQ_RQCPR0 (USB_base+0x818) //RX Queue Current Pointer Register0 RQCPR0
//#define USB_DMAQ_RQCSR1 (USB_base+0x820) //RX Queue Command and Status Register 1 RQCSR1
//#define USB_DMAQ_RQSAR1 (USB_base+0x824) //RX Queue Starting Address Register 1 RQSAR1
//#define USB_DMAQ_RQCPR1 (USB_base+0x828) //RX Queue Current Pointer Register 1 RQCPR1
//#define USB_DMAQ_RQCSR2 (USB_base+0x830) //RX Queue Command and Status Register2 RQCSR2
//#define USB_DMAQ_RQSAR2 (USB_base+0x834) //RX Queue Starting Address Register 2 RQSAR2
//#define USB_DMAQ_RQCPR2 (USB_base+0x838) //RX Queue Current Pointer Register 2 RQCPR2
//#define USB_DMAQ_RQCSR3 (USB_base+0x840) //RX Queue Command and Status Register 3 RQCSR3
//#define USB_DMAQ_RQSAR3 (USB_base+0x844) //RX Queue Starting Address Register 3 RQSAR3
//#define USB_DMAQ_RQCPR3 (USB_base+0x848) //RX Queue Current Pointer Register 3 RQCPR3
//#define USB_DMAQ_RQCSR4 (USB_base+0x850) //RX Queue Command and Status Register 4 RQCSR4
//#define USB_DMAQ_RQSAR4 (USB_base+0x854) //RX Queue Starting Address Register 4 RQSAR4
//#define USB_DMAQ_RQCPR4 (USB_base+0x858) //RX Queue Current Pointer Register 4 RQCPR4
//#define USB_DMAQ_RQCSR5 (USB_base+0x860) //RX Queue Command and Status Register 5 RQCSR5
//#define USB_DMAQ_RQSAR5 (USB_base+0x864) //RX Queue Starting Address Register 5 RQSAR5
//#define USB_DMAQ_RQCPR5 (USB_base+0x868) //RX Queue Current Pointer Register 5 RQCPR5
//#define USB_DMAQ_RQCSR6 (USB_base+0x870) //RX Queue Command and Status Register 6 RQCSR6
//#define USB_DMAQ_RQSAR6 (USB_base+0x874) //RX Queue Starting Address Register 6 RQSAR6
//#define USB_DMAQ_RQCPR6 (USB_base+0x878) //RX Queue Current Pointer Register 6 RQCPR6
//#define USB_DMAQ_RQCSR7 (USB_base+0x880) //RX Queue Command and Status Register 7 RQCSR7
//#define USB_DMAQ_RQSAR7 (USB_base+0x884) //RX Queue Starting Address Register 7 RQSAR7
//#define USB_DMAQ_RQCPR7 (USB_base+0x888) //RX Queue Current Pointer Register 7 RQCPR7
#define USB_DMAQ_RQTR0 (USB_base+0x890) //RX Queue 0 Timeout Register RQTR0
//#define USB_DMAQ_RQTR1 (USB_base+0x894) //RX Queue 1 Timeout Register RQTR1
//#define USB_DMAQ_RQTR2 (USB_base+0x898) //RX Queue 2 Timeout Register RQTR2
//#define USB_DMAQ_RQTR3 (USB_base+0x89C) //RX Queue 3 Timeout Register RQTR3
//#define USB_DMAQ_RQTR4 (USB_base+0x8A0) //RX Queue 4 Timeout Register RQTR4
//#define USB_DMAQ_RQTR5 (USB_base+0x8A4) //RX Queue 5 Timeout Register RQTR5
//#define USB_DMAQ_RQTR6 (USB_base+0x8A8) //RX Queue 6 Timeout Register RQTR6
//#define USB_DMAQ_RQTR7 (USB_base+0x8AC) //RX Queue 7 Timeout Register RQTR7
#define USB_DMAQ_RQLDPR0 (USB_base+0x900) //RX Queue Last Done Pointer Register 0 RQLDPR0
//#define USB_DMAQ_RQLDPR1 (USB_base+0x904) //RX Queue Last Done Pointer Register 1 RQLDPR1
//#define USB_DMAQ_RQLDPR2 (USB_base+0x908) //RX Queue Last Done Pointer Register 2 RQLDPR2
//#define USB_DMAQ_RQLDPR3 (USB_base+0x90C) //RX Queue Last Done Pointer Register 3 RQLDPR3
//#define USB_DMAQ_RQLDPR4 (USB_base+0x910) //RX Queue Last Done Pointer Register 4 RQLDPR4
//#define USB_DMAQ_RQLDPR5 (USB_base+0x914) //RX Queue Last Done Pointer Register 5 RQLDPR5
//#define USB_DMAQ_RQLDPR6 (USB_base+0x918) //RX Queue Last Done Pointer Register 6 RQLDPR6
//#define USB_DMAQ_RQLDPR7 (USB_base+0x91C) //RX Queue Last Done Pointer Register 7 RQLDPR7
//#define USB_DMAQ_T0QCSR (USB_base+0xA00) //TX 0 Queue Command and Status Register T0QCSR
//#define USB_DMAQ_T0QSAR (USB_base+0xA04) //TX 0 Queue Starting Address Register T0QSAR
//#define USB_DMAQ_T0QCPR (USB_base+0xA08) //TX 0 Queue Current Pointer Register T0QCPR
//#define USB_DMAQ_T1QCSR (USB_base+0xA10) //TX 1 Queue Command and Status Register T1QCSR
//#define USB_DMAQ_T1QSAR (USB_base+0xA14) //TX 1 Queue Starting Address Register T1QSAR
//#define USB_DMAQ_T1QCPR (USB_base+0xA18) //TX 1 Queue Current Pointer Register T1QCPR
//#define USB_DMAQ_T2QCSR (USB_base+0xA20) //TX 2 Queue Command and Status Register T2QCSR
//#define USB_DMAQ_T2QSAR (USB_base+0xA24) //TX 2 Queue Starting Address Register T2QSAR
//#define USB_DMAQ_T2QCPR (USB_base+0xA28) //TX 2 Queue Current Pointer Register T2QCPR
//#define USB_DMAQ_T3QCSR (USB_base+0xA30) //TX 3 Queue Command and Status Register T3QCSR
//#define USB_DMAQ_T3QSAR (USB_base+0xA34) //TX 3 Queue Starting Address Register T3QSAR
//#define USB_DMAQ_T3QCPR (USB_base+0xA38) //TX 3 Queue Current Pointer Register T3QCPR
//#define USB_DMAQ_T4QCSR (USB_base+0xA40) //TX 4 Queue Command and Status Register T4QCSR
//#define USB_DMAQ_T4QSAR (USB_base+0xA44) //TX 4 Queue Starting Address Register T4QSAR
//#define USB_DMAQ_T4QCPR (USB_base+0xA48) //TX 4 Queue Current Pointer Register T4QCPR
//#define USB_DMAQ_T5QCSR (USB_base+0xA50) //TX 5 Queue Command and Status Register T5QCSR
//#define USB_DMAQ_T5QSAR (USB_base+0xA54) //TX 5 Queue Starting Address Register T5QSAR
//#define USB_DMAQ_T5QCPR (USB_base+0xA58) //TX 5 Queue Current Pointer Register T5QCPR
//#define USB_DMAQ_T6QCSR (USB_base+0xA60) //TX 6 Queue Command and Status Register T6QCSR
//#define USB_DMAQ_T6QSAR (USB_base+0xA64) //TX 6 Queue Starting Address Register T6QSAR
//#define USB_DMAQ_T6QCPR (USB_base+0xA68) //TX 6 Queue Current Pointer Register T6QCPR
//#define USB_DMAQ_T7QCSR (USB_base+0xA70) //TX 7 Queue Command and Status Register T7QCSR
//#define USB_DMAQ_T7QSAR (USB_base+0xA74) //TX 7 Queue Starting Address Register T7QSAR
//#define USB_DMAQ_T7QCPR (USB_base+0xA78) //TX 7 Queue Current Pointer Register T7QCPR
#define USB_DMAQ_USBGCSR (USB_base+0xB00) //USB General Control and Status Registers USBGCSR
//#define USB_DMAQ_USB_FW1 (USB_base+0xB04) //USB Firmware read/write Register 1 (wimax) USB_FW1
//#define USB_DMAQ_USB_FW2 (USB_base+0xB08) //USB Firmware read/write Register 2 (wimax) USB_FW2
//#define USB_DMAQ_T0QUSBSC (USB_base+0xB80) //T0Q USB Stream Constraint Register (wimax) T0QUSBSC
//#define USB_DMAQ_T1QUSBSC (USB_base+0xB84) //T1Q USB Stream Constraint Register (wimax) T1QUSBSC
//#define USB_DMAQ_T2QUSBSC (USB_base+0xB88) //T2Q USB Stream Constraint Register (wimax) T2QUSBSC
//#define USB_DMAQ_T3QUSBSC (USB_base+0xB8C) //T3Q USB Stream Constraint Register (wimax) T3QUSBSC
//#define USB_DMAQ_T4QUSBSC (USB_base+0xB90) //T4Q USB Stream Constraint Register (wimax) T4QUSBSC
//#define USB_DMAQ_T5QUSBSC (USB_base+0xB94) //T5Q USB Stream Constraint Register (wimax) T5QUSBSC
//#define USB_DMAQ_T6QUSBSC (USB_base+0xB98) //T6Q USB Stream Constraint Register (wimax) T6QUSBSC
//#define USB_DMAQ_T7QUSBSC (USB_base+0xB9C) //T7Q USB Stream Constraint Register (wimax) T7QUSBSC
#define USB_DMAQ_QISAR (USB_base+0xC00) //QMU Interrupt Status and Acknowledgement Register QISAR
#define USB_DMAQ_QIMR (USB_base+0xC04) //QMU Interrupt Mask Register QIMR
#define USB_DMAQ_QIMCR (USB_base+0xC08) //QMU Interrupt Mask Clear Register QIMCR
#define USB_DMAQ_QIMSR (USB_base+0xC0C) //QMU Interrupt Mask Set Register QIMSR
//#define USB_DMAQ_QSISAR (USB_base+0xC10) //QMU Software Interrupt Status Ack Register (wimax-cmd) QSISAR
//#define USB_DMAQ_DSIMR (USB_base+0xC14) //Device Software Interrupt Mask Register (wimax-cmd) DSIMR
//#define USB_DMAQ_DSIMCR (USB_base+0xC18) //Device Software Interrupt Mask Clear Register (wimax-cmd) DSIMCR
//#define USB_DMAQ_DSIMSR (USB_base+0xC1C) //Device Software Interrupt Mask Set Register (wimax-cmd) DSIMSR
//#define USB_DMAQ_DSICR (USB_base+0xC20) //Device Software Interrupt Command Register (wimax-evt) DSICR
#define USB_DMAQ_IOCDISR (USB_base+0xC30) //GPD Done Interrupt on GPD IOC bit Disable Register IOCDISR
#define USB_DMAQ_QMU_HWVER (USB_base+0xC40) //QMU Hardware Version Register QMU_HWVER
//#define USB_DMAQ_TQEMIR (USB_base+0xC60) //TX Queue Empty Indication Register TQEMIR
//#define USB_DMAQ_TQEMIMR (USB_base+0xC64) //TX Queue Empty Indication Mask Register TQEMIMR
//#define USB_DMAQ_TQEMIMCR (USB_base+0xC68) //TX Queue Empty Indication Mask Clear Register TQEMIMCR
//#define USB_DMAQ_TQEMIMSR (USB_base+0xC6C) //TX Queue Empty Indication Mask Set Register TQEMIMSR
#define USB_DMAQ_RQEMIR (USB_base+0xC70) //RX Queue Empty Indication Register RQEMIR
#define USB_DMAQ_RQEMIMR (USB_base+0xC74) //RX Queue Empty Indication Mask Register RQEMIMR
#define USB_DMAQ_RQEMIMCR (USB_base+0xC78) //RX Queue Empty Indication Mask Clear Register RQEMIMCR
#define USB_DMAQ_RQEMIMSR (USB_base+0xC7C) //RX Queue Empty Indication Mask Set Register RQEMIMSR
#define USB_DMAQ_RQEIR (USB_base+0xC90) //RX Queue Error Indication Register RQEIR
#define USB_DMAQ_RQEIMR (USB_base+0xC94) //RX Queue Error Indication Mask Register RQEIMR
#define USB_DMAQ_RQEIMCR (USB_base+0xC98) //RX Queue Error Indication Mask Clear Register RQEIMCR
#define USB_DMAQ_RQEIMSR (USB_base+0xC9C) //RX Queue Error Indication Mask Set Register RQEIMSR
#define USB_DMAQ_REPEIR (USB_base+0xCA0) //RX Endpoint Error Indication Register REPEIR
#define USB_DMAQ_REPEIMR (USB_base+0xCA4) //RX Endpoint Error Indication Mask Register REPEIMR
#define USB_DMAQ_REPEIMCR (USB_base+0xCA8) //RX Endpoint Error Indication Mask Clear Register REPEIMCR
#define USB_DMAQ_REPEIMSR (USB_base+0xCAC) //RX Endpoint Error Indication Mask Set Register REPEIMSR
//#define USB_DMAQ_TQEIR (USB_base+0xCB0) //TX Queue Error Indication Register TQEIR
//#define USB_DMAQ_TQEIMR (USB_base+0xCB4) //TX Queue Error Indication Mask Register TQEIMR
//#define USB_DMAQ_TQEIMCR (USB_base+0xCB8) //TX Queue Error Indication Mask Clear Register TQEIMCR
//#define USB_DMAQ_TQEIMSR (USB_base+0xCBC) //TX Queue Error Indication Mask Set Register TQEIMSR
//#define USB_DMAQ_TEPEIR (USB_base+0xCC0) //TX Endpoint Error Indication Register TEPEIR
//#define USB_DMAQ_TEPEIMR (USB_base+0xCC4) //TX Endpoint Error Indication Mask Register TEPEIMR
//#define USB_DMAQ_TEPEIMCR (USB_base+0xCC8) //TX Endpoint Error Indication Mask Clear Register TEPEIMCR
//#define USB_DMAQ_TEPEIMSR (USB_base+0xCCC) //TX Endpoint Error Indication Mask Set Register TEPEIMSR
#define USB_DMAQ_DFCR (USB_base+0xCF0) //Debug Flag Control Register DFCR
#define USB_DMAQ_DFMR (USB_base+0xCF4) //Debug Flag Monitor Register DFMR
#define USB_DMAQ_QCR3_RX0_ZLP 0x01000000
#define USB_DMAQ_QCR3_RX_ZLP(n) (USB_DMAQ_QCR3_RX0_ZLP<<((n)-1))
#define USB_DMAQ_RQCSR(_n) (USB_base+0x800+(0x10*(_n)))
#define USB_DMAQ_RQSAR(_n) (USB_base+0x804+(0x10*(_n)))
#define USB_DMAQ_RQCPR(_n) (USB_base+0x808+(0x10*(_n)))
#define USB_DMAQ_USBGCSR_Rx0_EN (0x00010000)
//USB_DMAQ_QIMCR
#define USB_DMAQ_QIMCR_RXEP_ERR 0x04000000
#define USB_DMAQ_QIMCR_RXQ_ERR 0x02000000
#define USB_DMAQ_QIMCR_RQ_EMPTY 0x00020000
#define USB_DMAQ_QIMCR_RX0_DONE 0x00000100
#define USB_DMAQ_QIMCR_RX_DONE(_n) (USB_DMAQ_QIMCR_RX0_DONE<<(_n))
/*USB_DMAQ_QISAR*/
#define USB_DMAQ_QISAR_RX0_DONE 0x00000100
#define USB_DMAQ_QISAR_RX_DONE(n) (USB_DMAQ_QISAR_RX0_DONE<<n)
#define USB_PSR_CTRL_PSR_START 0x01
#define USB_PSR_CTRL_PSR_CLEAN 0x02
#define USB_PSR_CTRL_PSR_INTE 0x04
#define USB_PSR_CTRL_FLT_OUT 0x100
#define USB_PSR_CTRL_FLT_IN 0x200
#define USB_PSR_CTRL_FLT_SOF 0x400
#define USB_PSR_CTRL_FLT_SETUP 0x800
#define USB_PSR_CTRL_FLT_DATA0 0x1000
#define USB_PSR_CTRL_FLT_DATA1 0x2000
#define USB_PSR_CTRL_FLT_DATA2 0x4000
#define USB_PSR_CTRL_FLT_MDATA 0x8000
#define USB_PSR_CTRL_FLT_ACK 0x10000
#define USB_PSR_CTRL_FLT_NAK 0x20000
#define USB_PSR_CTRL_FLT_STALL 0x40000
#define USB_PSR_CTRL_FLT_NYET 0x80000
#define USB_PSR_CTRL_FLT_ERR 0x100000
#define USB_PSR_CTRL_FLT_SPLIT 0x200000
#define USB_PSR_CTRL_FLT_PING 0x400000
#define USB_PSR_CTRL_TR_OUT 0x1000000
#define USB_PSR_CTRL_TR_IN 0x2000000
#define USB_PSR_CTRL_TR_SOF 0x4000000
#define USB_PSR_CTRL_TR_SETUP 0x8000000
#define USB_PSR_CTRL_TR_DATA0 0x10000000
#define USB_PSR_CTRL_TR_DATA1 0x20000000
#define USB_PSR_CTRL_TR_DATA2 0x40000000
#define USB_PSR_CTRL_TR_MDATA 0x80000000
#define USB_PSR_CTRL_2_TR_ACK 0x01
#define USB_PSR_CTRL_2_TR_NAK 0x02
#define USB_PSR_CTRL_2_TR_STALL 0x04
#define USB_PSR_CTRL_2_TR_NYET 0x08
#define USB_PSR_CTRL_2_TR_ERR 0x10
#define USB_PSR_CTRL_2_TR_SPLIT 0x20
#define USB_PSR_CTRL_2_TR_PING 0x40
#define USB_PSR_CTRL_2_TR_FULL 0x100
#define USB_PSR_CTRL_2_TR_RXERROR 0x200
#define USB_PSR_CTRL_2_PSR_INTR 0x1000000
/* USB_POWER */
#define USB_POWER_ENABLESUSPENDM (0x01) /* RW */
#define USB_POWER_SUSPENDMODE (0x02) /* P: RO ; H: WO */ /*Read clear by the intr. register*/
#define USB_POWER_RESUME (0x04) /* RW */
#define USB_POWER_RESET (0x08) /* P: RO ; H: RW */
#define USB_POWER_HSMODE (0x10) /* RO */
#define USB_POWER_HSENAB (0x20) /* RW */
#define USB_POWER_SOFTCONN (0x40) /* RW */
#define USB_POWER_ISOUPDATE (0x80) /* RW */
/* USB_INTRTX */
#define USB_INTRTX_EP0 (0x01) /*RO*/
#define USB_INTRTX_EP1 (0x02) /*RO*/
#define USB_INTRTX_EP2 (0x04) /*RO*/
#define USB_INTRTX_EP3 (0x08) /*RO*/
#define USB_INTRTX_EP4 (0x10) /*RO*/
/* USB_INTRRX */
#define USB_INTRRX_EP1 (0x02) /*RO*/
#define USB_INTRRX_EP2 (0x04) /*RO*/
#define USB_INTRRX_EP3 (0x08) /*RO*/
/* USB_INTRTXE & USB_INTRRXE */
#define USB_INTRE_EPEN (0x01) /* RW */
#define USB_INTRE_EPDIS (0x00) /* RW */
/* USB_INTRUSB */
#define USB_INTRUSB_SUSPEND (0x01) /*RO*/
#define USB_INTRUSB_RESUME (0x02) /*RO*/
#define USB_INTRUSB_RESET (0x04) /*RO*/
#define USB_INTRUSB_BABBLE (0x04) /*RO*/
#define USB_INTRUSB_SOF (0x08) /*RO*/
#define USB_INTRUSB_CONN (0x10) /*RO*/
#define USB_INTRUSB_DISCON (0x20) /*RO*/
#define USB_INTRUSB_SESSREQ (0x40) /*RO*/
#define USB_INTRUSB_VBUSERROR (0x80) /*RO*/
/* USB_INTRUSBE */
#define USB_INTRUSBE_SUSPEND (0x01) /*RW*/
#define USB_INTRUSBE_RESUME (0x02) /*RW*/
#define USB_INTRUSBE_RESET (0x04) /*RW*/
#define USB_INTRUSBE_BABBLE (0x04) /*RW*/
#define USB_INTRUSBE_SOF (0x08) /*RW*/
#define USB_INTRUSBE_CONN (0x10) /*RW*/
#define USB_INTRUSBE_DISCON (0x20) /*RW*/
#define USB_INTRUSBE_SESSREQ (0x40) /*RW*/
#define USB_INTRUSBE_VBUSERROR (0x80) /*RW*/
/* USB_TESTMODE */
#define USB_TESTMODE_TESTSE0NAK (0x01) /* RW */
#define USB_TESTMODE_TESTJ (0x02) /* RW */
#define USB_TESTMODE_TESTK (0x04) /* RW */
#define USB_TESTMODE_TESTPACKET (0x08) /* RW */
#define USB_TESTMODE_FORCEHS (0x10) /* RW */
#define USB_TESTMODE_FORCEFS (0x20) /* RW */
#define USB_TESTMODE_FIFOACCESS (0x40) /* WO, AC */
#define USB_TESTMODE_FORCEHOST (0x80) /* RW */
/* USB_DEVCTL */
#define USB_DEVCTL_SESSION (0x01) /* RW */
#define USB_DEVCTL_HOSTREQ (0x02) /* RW */
#define USB_DEVCTL_HOSTMODE (0x04) /* RO */
#define USB_DEVCTL_VBUS (0x18) /* RO */
#define USB_DEVCTL_LSDEV (0x20) /* RO */
#define USB_DEVCTL_FSDEV (0x40) /* RO */
#define USB_DEVCTL_BDEVICE (0x80) /* RO */
#define USB_DEVCTL_ABOVE_VBUS_VALID (0x18)
#define USB_DEVCTL_ABOVE_A_VALID (0x10)
#define USB_DEVCTL_ABOVE_SESSION_END (0x01)
#define USB_DEVCTL_BELOW_SESSION_END (0x00)
/* USB_CSR0 */
#define USB_CSR0_RXPKTRDY (0x0001) /* RO */
#define USB_CSR0_TXPKTRDY (0x0002) /* RW, AC */
#define USB_CSR0_SENTSTALL (0x0004) /* RC */
#define USB_CSR0_DATAEND (0x0008) /* WO, AC */
#define USB_CSR0_SETUPEND (0x0010) /* RO */
#define USB_CSR0_SENDSTALL (0x0020) /* WO, AC */
#define USB_CSR0_SERVICEDRXPKTRDY (0x0040) /* WO, AC */
#define USB_CSR0_SERVICEDSETUPEND (0x0080) /* WO, AC */
#define USB_CSR0_FLUSHFIFO (0x0100) /* WO, AC */
/* in Host mode */
#define USB_CSR0_RXSTALL (0x0004)
#define USB_CSR0_SETUPPKT (0x0008)
#define USB_CSR0_ERROR (0x0010)
#define USB_CSR0_REQPKT (0x0020)
#define USB_CSR0_STATUSPKT (0x0040)
#define USB_CSR0_NAKTIMEOUT (0x0080)
#define USB_CSR0_FLUSHFIFO (0x0100)
#define USB_CSR0_DISPING (0x0800)
/* USB_TXMAXP */
#define USB_TXMAXP_MAXPAYLOAD_MASK (0x07FF)
#define USB_TXMAXP_HIGHSPEED_MASK (0xF800)
/* USB_TXCSR */
#define USB_TXCSR_TXPKTRDY (0x0001) /* RW */
#define USB_TXCSR_FIFONOTEMPTY (0x0002) /* RO */
#define USB_TXCSR_UNDERRUN (0x0004) /* RW */
#define USB_TXCSR_FLUSHFIFO (0x0008) /* WO */
#define USB_TXCSR_SENDSTALL (0x0010) /* RW */
#define USB_TXCSR_SENTSTALL (0x0020) /* RC */
#define USB_TXCSR_CLRDATATOG (0x0040) /* WO */
#define USB_TXCSR_INCOMPTX (0x0080) /* RC */
#define USB_TXCSR_SETTXPKTRDY_TWICE (0x0100) /* RC */
#define USB_TXCSR_DMAREQMODE (0x0400) /* RW */
#define USB_TXCSR_FRCDATATOG (0x0800) /* RW */
#define USB_TXCSR_DMAREQENAB (0x1000) /* RW */
#define USB_TXCSR_ISO (0x4000) /* RW */
#define USB_TXCSR_AUTOSET (0x8000) /* RW */
/* in Host mode */
#define USB_TXCSR_ERROR (0x0004)
#define USB_TXCSR_RXSTALL (0x0020)
#define USB_TXCSR_NAKTIMEOUT (0x0080)
/* USB_RXMAXP */
#define USB_RXMAXP_MAXPAYLOAD_MASK (0x07FF)
#define USB_RXMAXP_HIGHSPEED_MASK (0xF800)
/* USB_RXCSR */
#define USB_RXCSR_RXPKTRDY (0x0001) /* RC */
#define USB_RXCSR_FIFOFULL (0x0002) /* RO, AC */
#define USB_RXCSR_OVERRUN (0x0004) /* RC */
#define USB_RXCSR_DATAERROR (0x0008) /* RO */
#define USB_RXCSR_FLUSHFIFO (0x0010) /* WO, AC */
#define USB_RXCSR_SENDSTALL (0x0020) /* RW */
#define USB_RXCSR_SENTSTALL (0x0040) /* RC */
#define USB_RXCSR_CLRDATATOG (0x0080) /* WO */
#define USB_RXCSR_INCOMPRX (0x0100) /* RC */
#define USB_RXCSR_KEEPERRCTATUS (0x0200) /* RC */
#define USB_RXCSR_DMAREQMODE (0x0800) /* RW */
#define USB_RXCSR_DISNYET (0x1000) /* RW */
#define USB_RXCSR_PIDERROR (0x1000) /* RO */
#define USB_RXCSR_DMAREQENAB (0x2000) /* RW */
#define USB_RXCSR_ISO (0x4000) /* RW */
#define USB_RXCSR_AUTOCLEAR (0x8000) /* RW */
/* in Host mode */
#define USB_RXCSR_ERROR (0x0004)
#define USB_RXCSR_NAKTIMEOUT (0x0008)
#define USB_RXCSR_REQPKT (0x0020)
#define USB_RXCSR_RXSTALL (0x0040)
#define USB_RXCSR_SETPEQPKT_TWICE (0x0400)
#define USB_RXCSR_AUTOREQ (0x4000)
/* USB_TXTYPE */
#define USB_TXTYPE_EPNUM_MASK (0x0f)
#define USB_TXTYPE_ISO (0x10)
#define USB_TXTYPE_BULK (0x20)
#define USB_TXTYPE_INTR (0x30)
#define USB_TXTYPE_PROTOCOL_MASK (0x30)
/* USB_RXTYPE */
#define USB_RXTYPE_EPNUM_MASK (0x0f)
#define USB_RXTYPE_ISO (0x10)
#define USB_RXTYPE_BULK (0x20)
#define USB_RXTYPE_INTR (0x30)
#define USB_RXTYPE_PROTOCOL_MASK (0x30)
/* USB_PWRUPCNT */
#define USB_PWRUPCNT_MASK (0x0f)
/* USB_FIFOSZ */
#define USB_FIFOSZ_SIZE_MASK (0x0F)
#define USB_FIFOSZ_DPB (0x10)
#define USB_FIFOSZ_SIZE_8 (0x00)
#define USB_FIFOSZ_SIZE_16 (0x01)
#define USB_FIFOSZ_SIZE_32 (0x02)
#define USB_FIFOSZ_SIZE_64 (0x03)
#define USB_FIFOSZ_SIZE_128 (0x04)
#define USB_FIFOSZ_SIZE_256 (0x05)
#define USB_FIFOSZ_SIZE_512 (0x06)
#define USB_FIFOSZ_SIZE_1024 (0x07)
#define USB_FIFOSZ_SIZE_2048 (0x08)
#define USB_FIFOSZ_SIZE_4096 (0x09)
/* USB_FIFOADD */
#define USB_FIFOADD_MASK (0x1FFF)
/* USB_RXFIFOADD */
#define USB_RXFIFOADD_DATAERRINTREN (0x8000)
#define USB_RXFIFOADD_OVERRUNINTREN (0x4000)
/* USB_FIFO2ADD */
#define USB_FIFO2ADD_MASK (0x1FFF)
#define USB_FIFO2ADD_EN (0x8000)
/* USB_BUSPERF3 */
#define USB_BUSPERF3_DISUSBRESET (0x0001)
#define USB_BUSPERF3_SWRST (0x0002)
/* USB_RSTINFO */
#define USB_RSTINFO_WTFSSE0 (0x00F0)
#define USB_RSTINFO_WTCHRP (0x000F)
/* USB_L1INTS */
#define USB_L1INTS_TX_INT_STATUS (0x0001)
#define USB_L1INTS_RX_INT_STATUS (0x0002)
#define USB_L1INTS_USBCOM_INT_STATUS (0x0004)
#define USB_L1INTS_DMA_INT_STATUS (0x0008)
#define USB_L1INTS_PSR_INT_STATUS (0x0010)
#define USB_L1INTS_QINT_STATUS (0x0020)
#define USB_L1INTS_QHIF_INT_STATUS (0x0040)
#define USB_L1INTS_DPDM_INT_STATUS (0x0080)
#define USB_L1INTS_VBUSVALID_INT_STATUS (0x0100)
#define USB_L1INTS_IDDIG_INT_STATUS (0x0200)
#define USB_L1INTS_DRVVBUS_INT_STATUS (0x0400)
#define USB_L1INTS_POWERDOWN_INT_STATUS (0x0800)
/* USB_L1INTM */
#define USB_L1INTM_TX_INT_UNMASK (0x0001)
#define USB_L1INTM_RX_INT_UNMASK (0x0002)
#define USB_L1INTM_USBCOM_INT_UNMASK (0x0004)
#define USB_L1INTM_DMA_INT_UNMASK (0x0008)
#define USB_L1INTM_PSR_INT_UNMASK (0x0010)
#define USB_L1INTM_QINT_UNMASK (0x0020)
#define USB_L1INTM_QHIF_INT_UNMASK (0x0040)
#define USB_L1INTM_DPDM_INT_UNMASK (0x0080)
#define USB_L1INTM_VBUSVALID_INT_UNMASK (0x0100)
#define USB_L1INTM_IDDIG_INT_UNMASK (0x0200)
#define USB_L1INTM_DRVVBUS_INT_UNMASK (0x0400)
#define USB_L1INTM_POWERDOWN_INT_UNMASK (0x0800)
/* USB_L1INTP */
#define USB_L1INTP_VBUSVALID_INT_POL (0x0100)
#define USB_L1INTP_IDDIG_INT_POL (0x0200)
#define USB_L1INTP_DRVVBUS_INT_POL (0x0400)
#define USB_L1INTP_POWERDOWN_INT_POL (0x0800)
/* USB_L1INTC */
#define USB_L1INTC_USB_INT_SYNC (0x0001)
//#define USB_DMA_LIMITER_MASK 0xFFFF00FF
/* USB_DMACNTL */
#define USB_DMACNTL_DMAEN (0x0001)
#define USB_DMACNTL_DMADIR (0x0002)
#define USB_DMACNTL_DMAMODE (0x0004)
#define USB_DMACNTL_INTEN (0x0008)
#define USB_DMACNTL_EP_MASK (0x00F0)
#define USB_DMACNTL_BUSERR (0x0100)
//#define USB_DMACNTL_BURSTMODE_MASK (0x0600)
#define USB_DMACNTL_BURSTMODE_MASK (0x0000)
#define USB_DMACNTL_DMACHEN (0x0800)
/* USB_DMA_TIMER */
#define USB_DMA_TIMER_ENTIMER (0x0080)
#define USB_DMA_TIMER_TIMEOUT_MASK (0x007F)
#define USB_DMA_TIMER_TIMEOUT_STATUS (0x0100) /* W1C */
/*USB_DMAQ_RQCSRn*/
#define USB_DMACNTL_DMAEN_RXQ_ACTIVE (0x8000)
#define USB_DMACNTL_DMAEN_RXQ_STOP (0x0004)
#define USB_DMACNTL_DMAEN_RXQ_RESUME (0x0002)
#define USB_DMACNTL_DMAEN_RXQ_START (0x0001)
#define USB_DBG_PRB_OPSTATE_MASK (0x0000003F)
#define USB_DBG_PRB_LINESTATE_MASK (0x000000C0)
//========================definition of global value===================//
/* descriptor setting limitation */
#ifdef DRV_USB_COST_DOWN_CHIP
#define USB_MAX_FIFO_SIZE 2304 //64(EP0)+64(INT)+512x2(Bulk TX)+512x2(Bulk RX)
#else
#define USB_MAX_FIFO_SIZE 4096
#endif
#define USB_FIFO_START_ADDRESS 64
#define USB_BULK_FIFO_UNIT_SIZE 512
#ifdef __ISO_HB__
#define USB_ISO_FIFO_UNIT_SIZE 3072
#else
#define USB_ISO_FIFO_UNIT_SIZE 1024
#endif
#ifdef __INTR_HB__
#define USB_INTR_FIFO_UNIT_SIZE 3072
#else
#define USB_INTR_FIFO_UNIT_SIZE 32
#endif
//========================definition of PHY===================//
#if (defined(DRV_USB_PHY_U40_IP)) //MT6575
#ifdef __USB_HS_SLEW_RATE_CAL__
#define USB_HS_SLEW_RATE_CAL_TIME_WINDOW 0x400
#define USB_HS_SLEW_RATE_CAL_A 3
#define USB_HS_SLEW_RATE_CAL_FRA (66)
#define USB_FMCR0 (USBSIF_base+0xF00) /* RW */
#define USB_FMCR1 (USBSIF_base+0xF04) /* RW */
#define USB_FMCR2 (USBSIF_base+0xF08) /* RW */
#define USB_FMMONR0 (USBSIF_base+0xF0C) /* RW */
#define USB_FMMONR1 (USBSIF_base+0xF10) /* RW */
#endif //USB_HS_SLEW_RATE_CAL
#define USB_U2PHYAC0 (USBSIF_base+0x800) //USB2.0 PHYA Common Registers
#define USB_U2PHYAC1 (USBSIF_base+0x804) //USB2.0 PHYA Common Registers
#define USB_U2PHYAC2 (USBSIF_base+0x808) //USB2.0 PHYA Common Registers
#define USB_U2PHYACR0 (USBSIF_base+0x810) //USB2.0 PHYA Control Registers
#define USB_U2PHYACR1 (USBSIF_base+0x814) //USB2.0 PHYA Control Registers
#define USB_U2PHYACR2 (USBSIF_base+0x818) //USB2.0 PHYA Control Registers
#define USB_U2PHYACR3 (USBSIF_base+0x81C) //USB2.0 PHYA Control Registers
#define USB_U2PHYACR4 (USBSIF_base+0x820) //USB2.0 PHYA Control Registers
#define USB_U2PHYDCR0 (USBSIF_base+0x860) //USB2.0 PHYD Control Registers
#define USB_U2PHYDCR1 (USBSIF_base+0x864) //USB2.0 PHYD Control Registers
#define USB_U2PHYDTM0 (USBSIF_base+0x868) //USB2.0 PHYD TestMode Registers
#define USB_U2PHYDTM1 (USBSIF_base+0x86C) //USB2.0 PHYD TestMode Registers
#define USB_U2PHYDMON0 (USBSIF_base+0x870) //USB2.0 PHYD Monitor Registers
#define USB_U2PHYDMON1 (USBSIF_base+0x874) //USB2.0 PHYD Monitor Registers
#define USB_U2PHYDMON2 (USBSIF_base+0x878) //USB2.0 PHYD Monitor Registers
#define USB_U1PHYCR0 (USBSIF_base+0x8C0) //USB1.1 PHY Control Registers
#define USB_U1PHYCR1 (USBSIF_base+0x8C4) //USB1.1 PHY Control Registers
#define USB_U1PHYCR2 (USBSIF_base+0x8C8) //USB1.1 PHY Control Registers
#define USB_REGFPPC (USBSIF_base+0x8E0) //RegFile Per-Page Common Registers
#define USB_VERSIONC (USBSIF_base+0x8F0) //Version Code
#define USB_REGFCOM (USBSIF_base+0x8FC) //RegFile Common Registers
#define USB_U2PHYDTM0_force_uart_en (1<<26)
#define USB_U2PHYDTM0_force_suspendm (1<<18)
#define USB_U2PHYDTM0_RG_SUSPENDM (1<<3)
#define USB_U2PHYDTM1_RG_UART_EN (1<<16)
#define USB_U2PHYAC0_RG_USB20_USBPLL_FBDIV_6_0_CLR (0x7F<<16) //[6:0]
#define USB_U2PHYAC0_RG_USB20_USBPLL_FBDIV_6_0 (9<<16) //[6:0]
#define USB_U2PHYACR2_RG_USB20_OTG_VBUSCMP_EN (1<<27)
#define USB_U2PHYACR3_RG_USB20_PHY_REV_7 (1<<7)
#define USB_U2PHYACR4_RG_USB20_DP_100K_EN (1<<16)
#define USB_U2PHYACR4_RG_USB20_DM_100K_EN (1<<17)
#define USB_U2PHYDTM0_RG_DPPULLDOWN (1<<6)
#define USB_U2PHYDTM0_RG_DMPULLDOWN (1<<7)
#define USB_U2PHYDTM0_RG_XCVRSEL_1_0_CLR (0x3<<4) //[1:0]
#define USB_U2PHYDTM0_RG_XCVRSEL_1_0 (0x1<<4) //[1:0]
#define USB_U2PHYDTM0_RG_DATAIN_3_0_CLR (0xF<<10) //[3:0]
#define USB_U2PHYDTM0_force_dp_pulldown (1<<20)
#define USB_U2PHYDTM0_force_dm_pulldown (1<<21)
#define USB_U2PHYDTM0_force_termsel (1<<17)
#define USB_U2PHYDTM0_force_xcvrsel (1<<19)
#define USB_U2PHYDTM0_force_datain (1<<23)
#define USB_U2PHYDTM0_RG_TERMSEL (1<<2)
#define USB_U2PHYDCR1_RG_PLL_STABL (1<<19)
#define USB_U2PHYDMON1_USB20_LINE_STATE_DP (1<<22)
#define USB_U2PHYDMON1_USB20_LINE_STATE_DM (1<<23)
#define USB_U2PHYAC0_RG_USB20_INTR_EN (1<<14)
#elif (defined(DRV_USB_PHY_M60_IP))
#ifdef __USB_HS_SLEW_RATE_CAL__
#define USB_HS_SLEW_RATE_CAL_TIME_WINDOW 0x400
#define USB_HS_SLEW_RATE_CAL_A 28
#define USB_HS_SLEW_RATE_CAL_FRA (1000)
#define USB_FMMONR1_RG_FRCK_EN (1<<8)
#define USB_FMCR0 (USB_base+0xF00) /* RW */
#define USB_FMCR1 (USB_base+0xF04) /* RW */
#define USB_FMCR2 (USB_base+0xF08) /* RW */
#define USB_FMMONR0 (USB_base+0xF0C) /* RW */
#define USB_FMMONR1 (USB_base+0xF10) /* RW */
#endif //USB_HS_SLEW_RATE_CAL
#define USB_U2PHYAC0 (USBSIF_base+0x800) //USB2.0 PHYA Common Registers
#define USB_U2PHYAC1 (USBSIF_base+0x804) //USB2.0 PHYA Common Registers
#define USB_U2PHYAC2 (USBSIF_base+0x808) //USB2.0 PHYA Common Registers
#define USB_U2PHYACR0 (USBSIF_base+0x810) //USB2.0 PHYA Control Registers
#define USB_U2PHYACR1 (USBSIF_base+0x814) //USB2.0 PHYA Control Registers
#define USB_U2PHYACR2 (USBSIF_base+0x818) //USB2.0 PHYA Control Registers
#define USB_U2PHYACR3 (USBSIF_base+0x81C) //USB2.0 PHYA Control Registers
#define USB_U2PHYACR4 (USBSIF_base+0x820) //USB2.0 PHYA Control Registers
#define USB_U2PHYDCR0 (USBSIF_base+0x860) //USB2.0 PHYD Control Registers
#define USB_U2PHYDCR1 (USBSIF_base+0x864) //USB2.0 PHYD Control Registers
#define USB_U2PHYDTM0 (USBSIF_base+0x868) //USB2.0 PHYD TestMode Registers
#define USB_U2PHYDTM1 (USBSIF_base+0x86C) //USB2.0 PHYD TestMode Registers
#define USB_U2PHYDMON0 (USBSIF_base+0x870) //USB2.0 PHYD Monitor Registers
#define USB_U2PHYDMON1 (USBSIF_base+0x874) //USB2.0 PHYD Monitor Registers
#define USB_U2PHYDMON2 (USBSIF_base+0x878) //USB2.0 PHYD Monitor Registers
#define USB_U1PHYCR0 (USBSIF_base+0x8C0) //USB1.1 PHY Control Registers
#define USB_U1PHYCR1 (USBSIF_base+0x8C4) //USB1.1 PHY Control Registers
#define USB_U1PHYCR2 (USBSIF_base+0x8C8) //USB1.1 PHY Control Registers
#define USB_REGFPPC (USBSIF_base+0x8E0) //RegFile Per-Page Common Registers
#define USB_VERSIONC (USBSIF_base+0x8F0) //Version Code
#define USB_REGFCOM (USBSIF_base+0x8FC) //RegFile Common Registers
#define USB_U2PHYACR0_RG_USB20_HSTX_SRCTRL_CLR (0x7<<16)
#define USB_U2PHYACR0_RG_USB20_HSTX_SRCTRL (0x5<<16)
#define USB_U2PHYACR0_RG_USB20_HSTX_SRCAL_EN (0x1<<23)
#define USB_U2PHYACR1_RG_USB20_DM_ABIST_SOURCE_EN (0x1<<15)
#define USB_U2PHYDTM0_force_uart_en (1<<26)
#define USB_U2PHYDTM0_force_suspendm (1<<18)
#define USB_U2PHYDTM0_RG_SUSPENDM (1<<3)
#define USB_U2PHYDTM1_RG_UART_EN (1<<16)
#define USB_U2PHYAC0_RG_USB20_USBPLL_FBDIV_6_0_CLR (0x7F<<16) //[6:0]
#define USB_U2PHYAC0_RG_USB20_USBPLL_FBDIV_6_0 (9<<16) //[6:0]
#define USB_U2PHYACR2_RG_USB20_OTG_VBUSCMP_EN (1<<27)
#define USB_U2PHYACR3_RG_USB20_PHY_REV_7 (1<<7)
#define USB_U2PHYACR3_RG_USB20_HS_TERM_EN_MODE (0x2<<13)
#define USB_U2PHYACR3_RG_USB20_HS_TERM_EN_MODE_CLR (0x3<<13)
#define USB_U2PHYACR4_RG_USB20_DP_100K_EN (1<<16)
#define USB_U2PHYACR4_RG_USB20_DM_100K_EN (1<<17)
#define USB_U2PHYDTM0_RG_DPPULLDOWN (1<<6)
#define USB_U2PHYDTM0_RG_DMPULLDOWN (1<<7)
#define USB_U2PHYDTM0_RG_XCVRSEL_1_0_CLR (0x3<<4) //[1:0]
#define USB_U2PHYDTM0_RG_XCVRSEL_1_0 (0x1<<4) //[1:0]
#define USB_U2PHYDTM0_RG_DATAIN_3_0_CLR (0xF<<10) //[3:0]
#define USB_U2PHYDTM0_force_dp_pulldown (1<<20)
#define USB_U2PHYDTM0_force_dm_pulldown (1<<21)
#define USB_U2PHYDTM0_force_termsel (1<<17)
#define USB_U2PHYDTM0_force_xcvrsel (1<<19)
#define USB_U2PHYDTM0_force_datain (1<<23)
#define USB_U2PHYDTM0_RG_TERMSEL (1<<2)
#define USB_U2PHYDCR1_RG_PLL_STABL (1<<19)
#define USB_U2PHYDMON1_USB20_LINE_STATE_DP (1<<22)
#define USB_U2PHYDMON1_USB20_LINE_STATE_DM (1<<23)
#define USB_U2PHYAC0_RG_USB20_INTR_EN (1<<14)
#endif
#elif (defined(DRV_USB_IP_V3))
//=============Controller===================//
#define USB_FADDR_HCD(_baseaddr) (_baseaddr+0x00) /* RW */
#define USB_POWER_HCD(_baseaddr) (_baseaddr+0x01)
#define USB_INTRTX_HCD(_baseaddr) (_baseaddr+0x02) /* 16-bit, status, read only */
#define USB_INTRRX_HCD(_baseaddr) (_baseaddr+0x04) /* 16-bit, status, read only */
#define USB_INTRTXE_HCD(_baseaddr) (_baseaddr+0x06) /* 16-bit, RW */
#define USB_INTRRXE_HCD(_baseaddr) (_baseaddr+0x08) /* 16-bit, RW */
#define USB_INTRUSB_HCD(_baseaddr) (_baseaddr+0x0A) /* 8-bit, status, read only*/
#define USB_INTRUSBE_HCD(_baseaddr) (_baseaddr+0x0B) /* 8-bit, RW */
#define USB_FRAME_HCD(_baseaddr) (_baseaddr+0x0C) /* 16-bit, read only */ /*Max Frame length = 11 bits*/
#define USB_INDEX_HCD(_baseaddr) (_baseaddr+0x0E) /* RW, 4bit available*/
#define USB_TESTMODE_HCD(_baseaddr) (_baseaddr+0x0F) /* RW, 8-bit */
#define USB_CSR0_HCD(_baseaddr) (_baseaddr+0x12) /* 16-bit */
#define USB_COUNT0_HCD(_baseaddr) (_baseaddr+0x18) /* RO, EP0 only*/
#define USB_NAKLIMIT0_HCD(_baseaddr) (_baseaddr+0x1B) /* RW, host mode only*/
#define USB_TXMAXP_HCD(_baseaddr) (_baseaddr+0x10) /* 16-bit, RW*/
#define USB_TXCSR_HCD(_baseaddr) (_baseaddr+0x12)
#define USB_RXMAXP_HCD(_baseaddr) (_baseaddr+0x14) /* 16-bit, RW*/
#define USB_RXCSR_HCD(_baseaddr) (_baseaddr+0x16)
#define USB_RXCOUNT_HCD(_baseaddr) (_baseaddr+0x18) /* RO, 14bits */
#define USB_TXTYPE_HCD(_baseaddr) (_baseaddr+0x1A) /* RW, host mode only */
#define USB_TXINTERVAL_HCD(_baseaddr) (_baseaddr+0x1B) /* RW, host mode only */
#define USB_RXTYPE_HCD(_baseaddr) (_baseaddr+0x1C) /* RW, host mode only */
#define USB_RXINTERVAL_HCD(_baseaddr) (_baseaddr+0x1D) /* RW, host mode only */
#define USB_EP0_HCD(_baseaddr) (_baseaddr+0x20) /* 4 byte as 1 queue */
#define USB_DEVCTL_HCD(_baseaddr) (_baseaddr+0x60) /* 8-bit */
#define USB_PWRUPCNT_HCD(_baseaddr) (_baseaddr+0x61) /* RW */
#define USB_TXFIFOSZ_HCD(_baseaddr) (_baseaddr+0x62) /* RW */
#define USB_RXFIFOSZ_HCD(_baseaddr) (_baseaddr+0x63) /* RW */
#define USB_TXFIFOADD_HCD(_baseaddr) (_baseaddr+0x64) /* RW */
#define USB_RXFIFOADD_HCD(_baseaddr) (_baseaddr+0x66) /* RW */
#define USB_SWRST_HCD(_baseaddr) (_baseaddr+0x70) /* RW */
#define USB_OPSTATE_HCD(_baseaddr) (_baseaddr+0x71) /* RW */
#define USB_VPLEN_HCD(_baseaddr) (_baseaddr+0x7B) /* RW, 8-bits */
#define USB_RSTINFO_HCD(_baseaddr) (_baseaddr+0x7F) /* RW */
#define USB_EPn_TXCSR_HCD(_baseaddr,_n) (_baseaddr+0x102+(0x10*(_n))) /* R */
#define USB_EPn_RXCSR_HCD(_baseaddr,_n) (_baseaddr+0x106+(0x10*(_n))) /* R */
#define USB_DMAINTR_HCD(_baseaddr) (_baseaddr+0x200) /* 8-bits, W0C */
#define USB_DMALIMITER_HCD(_baseaddr,_n) (_baseaddr+0x200+(0x10*(_n))) /* 8-bits, RW */
#define USB_DMACNTL_HCD(_baseaddr,_n) (_baseaddr+0x1F4+(0x10*(_n))) /* RW, _n = 1~6 */
#define USB_DMAADDR_HCD(_baseaddr,_n) (_baseaddr+0x1F8+(0x10*(_n))) /* RW, _n = 1~6 */
#define USB_DMACNT_HCD(_baseaddr,_n) (_baseaddr+0x1FC+(0x10*(_n))) /* RW, _n = 1~6 */
#define USB_RQPKTCOUNT_HCD(_baseaddr,_n) (_baseaddr+0x300+(0x04*(_n))) /* RW, 16bits, _n = 1~3, host mode RX ep only */
#define USB_DMA_REALCNT_HCD(_baseaddr,_n) (_baseaddr+0x3F0+(0x10*(_n))) /* RO, _n = 1~6, 32bits */
#define USB_DMA_TIMER_HCD(_baseaddr,_n) (_baseaddr+0x3F8+(0x10*(_n))) /* RW, _n = 1~6, 16bits */
#define USB_DMAPPCNTL_HCD(_baseaddr,_n) (_baseaddr+0x274+(0x10*(_n))) /* RW, _n = 1~6 */
#define USB_DMAPPADDR_HCD(_baseaddr,_n) (_baseaddr+0x278+(0x10*(_n))) /* RW, _n = 1~6 */
#define USB_DMAPPCNT_HCD(_baseaddr,_n) (_baseaddr+0x27C+(0x10*(_n))) /* RW, _n = 1~6 */
#define USB_DMA_PP_REALCNT_HCD(_baseaddr,_n) (_baseaddr+0x3F4+(0x10*(_n))) /* RO, _n = 1~6, 32bits */
//========================================================
#define USB_FADDR (USB_base+0x00) /* RW */
#define USB_POWER (USB_base+0x01)
#define USB_INTRTX (USB_base+0x02) /* 16-bit, status, read only */
#define USB_INTRRX (USB_base+0x04) /* 16-bit, status, read only */
#define USB_INTRTXE (USB_base+0x06) /* 16-bit, RW */
#define USB_INTRRXE (USB_base+0x08) /* 16-bit, RW */
#define USB_INTRUSB (USB_base+0x0A) /* 8-bit, status, read only*/
#define USB_INTRUSBE (USB_base+0x0B) /* 8-bit, RW */
#define USB_FRAME (USB_base+0x0C) /* 16-bit, read only */ /*Max Frame length = 11 bits*/
#define USB_INDEX (USB_base+0x0E) /* RW, 4bit available*/
#define USB_TESTMODE (USB_base+0x0F) /* RW, 8-bit */
#define USB_CSR0 (USB_base+0x12) /* 16-bit */
#define USB_COUNT0 (USB_base+0x18) /* RO, EP0 only*/
#define USB_NAKLIMIT0 (USB_base+0x1B) /* RW, host mode only*/
#define USB_TXMAXP (USB_base+0x10) /* 16-bit, RW*/
#define USB_TXCSR (USB_base+0x12)
#define USB_RXMAXP (USB_base+0x14) /* 16-bit, RW*/
#define USB_RXCSR (USB_base+0x16)
#define USB_RXCOUNT (USB_base+0x18) /* RO, 14bits */
#define USB_TXTYPE (USB_base+0x1A) /* RW, host mode only */
#define USB_TXINTERVAL (USB_base+0x1B) /* RW, host mode only */
#define USB_RXTYPE (USB_base+0x1C) /* RW, host mode only */
#define USB_RXINTERVAL (USB_base+0x1D) /* RW, host mode only */
#define USB_EP0 (USB_base+0x20) /* 4 byte as 1 queue */
#define USB_DEVCTL (USB_base+0x60) /* 8-bit */
#define USB_PWRUPCNT (USB_base+0x61) /* RW */
#define USB_TXFIFOSZ (USB_base+0x62) /* RW */
#define USB_RXFIFOSZ (USB_base+0x63) /* RW */
#define USB_TXFIFOADD (USB_base+0x64) /* RW */
#define USB_RXFIFOADD (USB_base+0x66) /* RW */
#define USB_SWRST (USB_base+0x70) /* RW */
#define USB_OPSTATE (USB_base+0x71) /* RW */
#define USB_VPLEN (USB_base+0x7B) /* RW, 8-bits */
#define USB_RSTINFO (USB_base+0x7F) /* RW */
#define USB_DUMMY (USB_base+0xF0) /* RW */
#define USB_EPn_TXCSR(_n) (USB_base+0x102+(0x10*(_n))) /* R */
#define USB_EPn_RXCSR(_n) (USB_base+0x106+(0x10*(_n))) /* R */
#define USB_DMAINTR (USB_base+0x200) /* 8-bits, W0C */
#define USB_DMALIMITER(_n) (USB_base+0x200+(0x10*(_n))) /* 8-bits, RW */
#define USB_DMACNTL(_n) (USB_base+0x1F4+(0x10*(_n))) /* RW, _n = 1~6 */
#define USB_DMAADDR(_n) (USB_base+0x1F8+(0x10*(_n))) /* RW, _n = 1~6 */
#define USB_DMACNT(_n) (USB_base+0x1FC+(0x10*(_n))) /* RW, _n = 1~6 */
#define USB_DMAPPCNTL(_n) (USB_base+0x274+(0x10*(_n))) /* RW, _n = 1~6 */
#define USB_DMAPPADDR(_n) (USB_base+0x278+(0x10*(_n))) /* RW, _n = 1~6 */
#define USB_DMAPPCNT(_n) (USB_base+0x27C+(0x10*(_n))) /* RW, _n = 1~6 */
#define USB_RQPKTCOUNT(_n) (USB_base+0x300+(0x04*(_n))) /* RW, 16bits, _n = 1~3, host mode RX ep only */
#define USB_DMA_REALCNT(_n) (USB_base+0x3F0+(0x10*(_n))) /* RO, _n = 1~6, 32bits */
#define USB_DMA_PP_REALCNT(_n) (USB_base+0x3F4+(0x10*(_n))) /* RO, _n = 1~6, 32bits */
#define USB_DMA_TIMER(_n) (USB_base+0x3F8+(0x10*(_n))) /* RW, _n = 1~6, 16bits */
//===================Controller variable===========================//
/* USB_POWER */
#define USB_POWER_ENABLESUSPENDM (0x01) /* RW */
#define USB_POWER_SUSPENDMODE (0x02) /* P: RO ; H: WO */ /*Read clear by the intr. register*/
#define USB_POWER_RESUME (0x04) /* RW */
#define USB_POWER_RESET (0x08) /* P: RO ; H: RW */
#define USB_POWER_HSMODE (0x10) /* RO */
#define USB_POWER_HSENAB (0x20) /* RW */
#define USB_POWER_SOFTCONN (0x40) /* RW */
#define USB_POWER_ISOUPDATE (0x80) /* RW */
/* USB_INTRTX */
#define USB_INTRTX_EP0 (0x01) /*RO*/
#define USB_INTRTX_EP1 (0x02) /*RO*/
#define USB_INTRTX_EP2 (0x04) /*RO*/
#define USB_INTRTX_EP3 (0x08) /*RO*/
#define USB_INTRTX_EP4 (0x10) /*RO*/
/* USB_INTRRX */
#define USB_INTRRX_EP1 (0x02) /*RO*/
#define USB_INTRRX_EP2 (0x04) /*RO*/
#define USB_INTRRX_EP3 (0x08) /*RO*/
/* USB_INTRTXE & USB_INTRRXE */
#define USB_INTRE_EPEN (0x01) /* RW */
#define USB_INTRE_EPDIS (0x00) /* RW */
/* USB_INTRUSB */
#define USB_INTRUSB_SUSPEND (0x01) /*RO*/
#define USB_INTRUSB_RESUME (0x02) /*RO*/
#define USB_INTRUSB_RESET (0x04) /*RO*/
#define USB_INTRUSB_BABBLE (0x04) /*RO*/
#define USB_INTRUSB_SOF (0x08) /*RO*/
#define USB_INTRUSB_CONN (0x10) /*RO*/
#define USB_INTRUSB_DISCON (0x20) /*RO*/
#define USB_INTRUSB_SESSREQ (0x40) /*RO*/
#define USB_INTRUSB_VBUSERROR (0x80) /*RO*/
/* USB_INTRUSBE */
#define USB_INTRUSBE_SUSPEND (0x01) /*RW*/
#define USB_INTRUSBE_RESUME (0x02) /*RW*/
#define USB_INTRUSBE_RESET (0x04) /*RW*/
#define USB_INTRUSBE_BABBLE (0x04) /*RW*/
#define USB_INTRUSBE_SOF (0x08) /*RW*/
#define USB_INTRUSBE_CONN (0x10) /*RW*/
#define USB_INTRUSBE_DISCON (0x20) /*RW*/
#define USB_INTRUSBE_SESSREQ (0x40) /*RW*/
#define USB_INTRUSBE_VBUSERROR (0x80) /*RW*/
/* USB_TESTMODE */
#define USB_TESTMODE_TESTSE0NAK (0x01) /* RW */
#define USB_TESTMODE_TESTJ (0x02) /* RW */
#define USB_TESTMODE_TESTK (0x04) /* RW */
#define USB_TESTMODE_TESTPACKET (0x08) /* RW */
#define USB_TESTMODE_FORCEHS (0x10) /* RW */
#define USB_TESTMODE_FORCEFS (0x20) /* RW */
#define USB_TESTMODE_FIFOACCESS (0x40) /* WO, AC */
#define USB_TESTMODE_FORCEHOST (0x80) /* RW */
/* USB_DEVCTL */
#define USB_DEVCTL_SESSION (0x01) /* RW */
#define USB_DEVCTL_HOSTREQ (0x02) /* RW */
#define USB_DEVCTL_HOSTMODE (0x04) /* RO */
#define USB_DEVCTL_VBUS (0x18) /* RO */
#define USB_DEVCTL_LSDEV (0x20) /* RO */
#define USB_DEVCTL_FSDEV (0x40) /* RO */
#define USB_DEVCTL_BDEVICE (0x80) /* RO */
#define USB_DEVCTL_ABOVE_VBUS_VALID (0x18)
#define USB_DEVCTL_ABOVE_A_VALID (0x10)
#define USB_DEVCTL_ABOVE_SESSION_END (0x01)
#define USB_DEVCTL_BELOW_SESSION_END (0x00)
/* USB_CSR0 */
#define USB_CSR0_RXPKTRDY (0x0001) /* RO */
#define USB_CSR0_TXPKTRDY (0x0002) /* RW, AC */
#define USB_CSR0_SENTSTALL (0x0004) /* RC */
#define USB_CSR0_DATAEND (0x0008) /* WO, AC */
#define USB_CSR0_SETUPEND (0x0010) /* RO */
#define USB_CSR0_SENDSTALL (0x0020) /* WO, AC */
#define USB_CSR0_SERVICEDRXPKTRDY (0x0040) /* WO, AC */
#define USB_CSR0_SERVICEDSETUPEND (0x0080) /* WO, AC */
#define USB_CSR0_FLUSHFIFO (0x0100) /* WO, AC */
/* in Host mode */
#define USB_CSR0_RXSTALL (0x0004)
#define USB_CSR0_SETUPPKT (0x0008)
#define USB_CSR0_ERROR (0x0010)
#define USB_CSR0_REQPKT (0x0020)
#define USB_CSR0_STATUSPKT (0x0040)
#define USB_CSR0_NAKTIMEOUT (0x0080)
#define USB_CSR0_FLUSHFIFO (0x0100)
#define USB_CSR0_DISPING (0x0800)
/* USB_TXMAXP */
#define USB_TXMAXP_MAXPAYLOAD_MASK (0x07FF)
#define USB_TXMAXP_HIGHSPEED_MASK (0xF800)
/* USB_TXCSR */
#define USB_TXCSR_TXPKTRDY (0x0001) /* RW */
#define USB_TXCSR_FIFONOTEMPTY (0x0002) /* RO */
#define USB_TXCSR_UNDERRUN (0x0004) /* RW */
#define USB_TXCSR_FLUSHFIFO (0x0008) /* WO */
#define USB_TXCSR_SENDSTALL (0x0010) /* RW */
#define USB_TXCSR_SENTSTALL (0x0020) /* RC */
#define USB_TXCSR_CLRDATATOG (0x0040) /* WO */
#define USB_TXCSR_INCOMPTX (0x0080) /* RC */
#define USB_TXCSR_AUTOSET_SPKT (0x0200) /* RW */
#define USB_TXCSR_DMAREQMODE (0x0400) /* RW */
#define USB_TXCSR_FRCDATATOG (0x0800) /* RW */
#define USB_TXCSR_DMAREQENAB (0x1000) /* RW */
#define USB_TXCSR_MODE (0x2000) /* RW */
#define USB_TXCSR_ISO (0x4000) /* RW */
#define USB_TXCSR_AUTOSET (0x8000) /* RW */
/* in Host mode */
#define USB_TXCSR_ERROR (0x0004)
#define USB_TXCSR_RXSTALL (0x0020)
#define USB_TXCSR_NAKTIMEOUT (0x0080)
/* USB_RXMAXP */
#define USB_RXMAXP_MAXPAYLOAD_MASK (0x07FF)
#define USB_RXMAXP_HIGHSPEED_MASK (0xF800)
/* USB_RXCSR */
#define USB_RXCSR_RXPKTRDY (0x0001) /* RC */
#define USB_RXCSR_FIFOFULL (0x0002) /* RO, AC */
#define USB_RXCSR_OVERRUN (0x0004) /* RC */
#define USB_RXCSR_DATAERROR (0x0008) /* RO */
#define USB_RXCSR_FLUSHFIFO (0x0010) /* WO, AC */
#define USB_RXCSR_SENDSTALL (0x0020) /* RW */
#define USB_RXCSR_SENTSTALL (0x0040) /* RC */
#define USB_RXCSR_CLRDATATOG (0x0080) /* WO */
#define USB_RXCSR_INCOMPRX (0x0100) /* RC */
#define USB_RXCSR_INCOMPRXINTREN (0x0200) /* RC */
#define USB_RXCSR_AUTOCLREN_SPKT (0x0400) /* RC */
#define USB_RXCSR_DMAREQMODE (0x0800) /* RW */
#define USB_RXCSR_DISNYET (0x1000) /* RW */
#define USB_RXCSR_PIDERROR (0x1000) /* RO */
#define USB_RXCSR_DMAREQENAB (0x2000) /* RW */
#define USB_RXCSR_ISO (0x4000) /* RW */
#define USB_RXCSR_AUTOCLEAR (0x8000) /* RW */
/* in Host mode */
#define USB_RXCSR_ERROR (0x0004)
#define USB_RXCSR_NAKTIMEOUT (0x0008)
#define USB_RXCSR_REQPKT (0x0020)
#define USB_RXCSR_RXSTALL (0x0040)
#define USB_RXCSR_PIDERROR (0x1000)
#define USB_RXCSR_AUTOREQ (0x4000)
/* USB_TXTYPE */
#define USB_TXTYPE_EPNUM_MASK (0x0f)
#define USB_TXTYPE_ISO (0x10)
#define USB_TXTYPE_BULK (0x20)
#define USB_TXTYPE_INTR (0x30)
#define USB_TXTYPE_PROTOCOL_MASK (0x30)
/* USB_RXTYPE */
#define USB_RXTYPE_EPNUM_MASK (0x0f)
#define USB_RXTYPE_ISO (0x10)
#define USB_RXTYPE_BULK (0x20)
#define USB_RXTYPE_INTR (0x30)
#define USB_RXTYPE_PROTOCOL_MASK (0x30)
/* USB_PWRUPCNT */
#define USB_PWRUPCNT_MASK (0x0f)
/* USB_FIFOSZ */
#define USB_FIFOSZ_SIZE_MASK (0x0F)
#define USB_FIFOSZ_DPB (0x10)
#define USB_FIFOSZ_SIZE_8 (0x00)
#define USB_FIFOSZ_SIZE_16 (0x01)
#define USB_FIFOSZ_SIZE_32 (0x02)
#define USB_FIFOSZ_SIZE_64 (0x03)
#define USB_FIFOSZ_SIZE_128 (0x04)
#define USB_FIFOSZ_SIZE_256 (0x05)
#define USB_FIFOSZ_SIZE_512 (0x06)
#define USB_FIFOSZ_SIZE_1024 (0x07)
#define USB_FIFOSZ_SIZE_2048 (0x08)
#define USB_FIFOSZ_SIZE_4096 (0x09)
/* USB_FIFOADD */
#define USB_FIFOADD_MASK (0x1FFF)
/* USB_RXFIFOADD */
#define USB_RXFIFOADD_DATAERRINTREN (0x8000)
#define USB_RXFIFOADD_OVERRUNINTREN (0x4000)
/* USB_FIFO2ADD */
#define USB_FIFO2ADD_MASK (0x1FFF)
#define USB_FIFO2ADD_EN (0x8000)
/* USB_SWRST */
#define USB_SWRST_DISUSBRESET (0x0001)
#define USB_SWRST_SWRST (0x0002)
#define USB_SWRST_FRC_VBUSVALID (0x0004)
#define USB_SWRST_UNDO_SRPFIX (0x0008)
#define USB_SWRST_REDUCE_DLY (0x0010)
/* USB_RSTINFO */
#define USB_RSTINFO_WTFSSE0 (0x00F0)
#define USB_RSTINFO_WTCHRP (0x000F)
/* USB_DMAINTR */
#define USB_DMA_INTR_MASK 0xFFFFFF00
#define USB_DMA_LIMITER_MASK 0xFFFF00FF
#define USB_DMA_PPFINISH_MASK 0x0000FFFF
/* USB_DMAPPINTR */
#define USB_PPA_FINISH1 (0x01) /*RO*/
#define USB_PPB_FINISH1 (0x02) /*RO*/
#define USB_PPA_FINISH2 (0x04) /*RO*/
#define USB_PPB_FINISH2 (0x08) /*RO*/
#define USB_PPA_FINISH3 (0x10) /*RO*/
#define USB_PPB_FINISH3 (0x20) /*RO*/
#define USB_PPA_FINISH4 (0x40) /*RO*/
#define USB_PPB_FINISH4 (0x80) /*RO*/
/* USB_DMACNTL */
#define USB_DMACNTL_DMAEN (0x0001)
#define USB_DMACNTL_DMADIR (0x0002)
#define USB_DMACNTL_DMAMODE (0x0004)
#define USB_DMACNTL_INTEN (0x0008)
#define USB_DMACNTL_EP_MASK (0x00F0)
#define USB_DMACNTL_BUSERR (0x0100)
#define USB_DMACNTL_BURSTMODE_MASK (0x0600)
#define USB_DMACNTL_PPEN (0x0800)
#define USB_DMACNTL_PPRST (0x1000)
#define USB_DMACNTL_ENDMAMODE2 (0x2000)
/* USB_DMAPPCNTL */
#define USB_DMAPPCNTL_DMAEN (0x0001)
/* USB_DMA_TIMER */
#define USB_DMA_TIMER_ENTIMER (0x0080)
#define USB_DMA_TIMER_TIMEOUT_MASK (0x007F)
#define USB_DMA_TIMER_TIMEOUT_STATUS (0x0100)
//========================definition of global value===================//
/* descriptor setting limitation */
#ifdef DRV_USB_COST_DOWN_CHIP
#define USB_MAX_FIFO_SIZE 2304 //64(EP0)+64(INT)+512x2(Bulk TX)+512x2(Bulk RX)
#else
#define USB_MAX_FIFO_SIZE 4096
#endif
#define USB_FIFO_START_ADDRESS 64
#define USB_BULK_FIFO_UNIT_SIZE 512
#ifdef __ISO_HB__
#define USB_ISO_FIFO_UNIT_SIZE 3072
#else
#define USB_ISO_FIFO_UNIT_SIZE 1024
#endif
#ifdef __INTR_HB__
#define USB_INTR_FIFO_UNIT_SIZE 3072
#else
#define USB_INTR_FIFO_UNIT_SIZE 32
#endif
//===================== PHY Version ==========================//
#if (defined(DRV_USB_PHY_COST_DOWN)) //MT6268 , MT6236 , MT6253
/* USB phy register */
#define USB_PHYCR1_0 (USB_base+0x600) /* RW */
#define USB_PHYCR1_1 (USB_base+0x601) /* RW */
#define USB_PHYCR1_2 (USB_base+0x602) /* RW */
#define USB_PHYCR1_3 (USB_base+0x603) /* RW */
#define USB_PHYCR2_0 (USB_base+0x604) /* RW */
#define USB_PHYCR2_1 (USB_base+0x605) /* RW */
#define USB_PHYCR2_2 (USB_base+0x606) /* RW */
#define USB_PHYCR2_3 (USB_base+0x607) /* RW */
#define USB_PHYCR3_0 (USB_base+0x608) /* RW */
#define USB_PHYCR3_1 (USB_base+0x609) /* RW */
#define USB_PHYCR3_2 (USB_base+0x60A) /* RW */
#define USB_PHYCR3_3 (USB_base+0x60B) /* RW */
#define USB_PHYCR4_0 (USB_base+0x60C) /* RW */
#define USB_PHYCR4_1 (USB_base+0x60D) /* RW */
#define USB_PHYCR4_2 (USB_base+0x60E) /* RW */
#define USB_PHYCR4_3 (USB_base+0x60F) /* RW */
#define USB_PHYCR5_0 (USB_base+0x610) /* RW */
#define USB_PHYCR5_1 (USB_base+0x611) /* RW */
#define USB_PHYCR5_2 (USB_base+0x612) /* RW */
#define USB_PHYCR5_3 (USB_base+0x613) /* RW */
#define USB_PHYIR1_0 (USB_base+0x614) /* RW */
#define USB_PHYIR1_1 (USB_base+0x615) /* RW */
#define USB_PHYIR1_2 (USB_base+0x616) /* RW */
#define USB_PHYIR1_3 (USB_base+0x617) /* RW */
#define USB_PHYIR2_0 (USB_base+0x618) /* RW */
#define USB_PHYIR2_1 (USB_base+0x619) /* RW */
#define USB_PHYIR2_2 (USB_base+0x61A) /* RW */
#define USB_PHYIR2_3 (USB_base+0x61B) /* RW */
#define USB_PHYIR3_0 (USB_base+0x61C) /* RW */
#define USB_PHYIR3_1 (USB_base+0x61D) /* RW */
#define USB_PHYIR3_2 (USB_base+0x61E) /* RW */
//#define USB_PHYIR3_3 (USB_base+0x61F) /* RW */
#define USB_PHYIR4_0 (USB_base+0x620) /* RW */
#define USB_PHYIR4_1 (USB_base+0x621) /* RW */
#define USB_PHYIR4_2 (USB_base+0x622) /* RW */
#define USB_PHYIR4_3 (USB_base+0x623) /* RW */
#define USB_PHYIR5_0 (USB_base+0x624) /* RW */
#define USB_PHYIR5_1 (USB_base+0x625) /* RW */
#define USB_PHYIR5_2 (USB_base+0x626) /* RW */
#define USB_PHYIR5_3 (USB_base+0x627) /* RW */
#define USB_PHYIR6_0 (USB_base+0x628) /* RW */
#define USB_PHYIR6_1 (USB_base+0x629) /* RW */
//#define USB_PHYIR6_2 (USB_base+0x62A) /* RW */
//#define USB_PHYIR6_3 (USB_base+0x62B) /* RW */
/* USB PHY variable*/
/* USB_PHY ALL*/
#define USB_PHY_CLEAR_MASK (0x00)
/* USB_PHYCR1_0 */
#define USB_PHYCR1_0_BGR_BGR_EN (0x01)
#define USB_PHYCR1_0_BGR_I_SRC_EN (0x02)
#define USB_PHYCR1_0_BGR_CHIP_EN (0x04)
#define USB_PHYCR1_0_IADJ_MASK (0x70)
#define USB_PHYCR1_0_IADJ_MASK2 (0x40)
#define USB_PHYCR1_0_IADJ_MASK3 (0x50)
#define USB_PHYCR1_0_IADJ_RESISTER_SET (0x60)
/* USB_PHYCR1_1 */
/* USB_PHYCR1_2 */
#define USB_PHYCR1_2_RG_PLL_DIV (0x0A)
#define USB_PHYCR1_2_RG_PLL_DIV2 (0x08)
#define USB_PHYCR1_2_RG_PLL_DIV3 (0x03)
/* USB_PHYCR1_3 */
/* USB_PHYCR2_0 */
/* USB_PHYCR2_1 */
/* USB_PHYCR2_2 */
#define USB_PHYCR2_2_HS_TRIM_TH (0x08)
#define USB_PHYCR2_2_HSDISC_DEGL (0x80)
#define USB_PHYCR2_2_HS_DISC_TH (0x40)
/* USB_PHYCR2_3 */
#define USB_PHYCR2_3_PLL_EN (0x02)
#define USB_PHYCR2_3_HS_TERMC (0x08)
/* USB_PHYCR3_0 */
#define USB_PHYCR3_0_CDR_FILT (0x02)
#define USB_PHYCR3_0_EARLY_HSTX_I (0x40)
#define USB_PHYCR3_0_HS_TX_ANA_SER_EN (0x80)
/* USB_PHYCR3_1 */
/* USB_PHYCR3_2 */
#define USB_PHYCR3_2_FORCE_DATA_IN (0x02)
#define USB_PHYCR3_2_FORCE_TX_VALID (0x01)
#define USB_PHYCR3_2_FORCE_DP_PULLDOWN (0x04)
#define USB_PHYCR3_2_FORCE_DM_PULLDOWN (0x08)
#define USB_PHYCR3_2_FORCE_DP_DM_PULLDOWN (0x0C)
#define USB_PHYCR3_2_FORCE_DRV_VBUS (0x10)
/* USB_PHYCR3_3 */
#define USB_PHYCR3_3_FORCE_OP_MODE (0x01)
#define USB_PHYCR3_3_FORCE_TERM_SELECT (0x02)
#define USB_PHYCR3_3_FORCE_SUSPENDM (0x04)
#define USB_PHYCR3_3_FORCE_XCVR_SELECT (0x08)
#define USB_PHYCR3_3_FORCE_DP_HIGH (0x0B)
#define USB_PHYCR3_3_FORCE_IDPULLUP (0x20)
#define USB_PHYCR3_3_UTMI_MUXSEL (0x10)
/* USB_PHYCR4_0 */
#define USB_PHYCR4_0_FORCE_USB_CLKOFF (0x20)
#define USB_PHYCR4_0_FORCE_AUX_EN (0x80)
#define USB_PHYCR4_0_FORCE_OTG_PROBE (0x40)
#define USB_PHYCR4_0_FORCE_BVALID (0x10)
#define USB_PHYCR4_0_FORCE_IDDIG (0x08)
#define USB_PHYCR4_0_FORCE_VBUSVALID (0x04)
#define USB_PHYCR4_0_FORCE_SESSEND (0x02)
#define USB_PHYCR4_0_FORCE_AVALID (0x01)
/* USB_PHYCR4_1 */
#define USB_PHYCR4_1_FORCE_BGR_ON (0x4F)
/* USB_PHYCR4_2 */
/* USB_PHYCR4_3 */
#define USB_PHYCR4_3_UART_MODE (0x08)
#define USB_PHYCR4_3_OTG_RESET_EN (0x80)
/* USB_PHYCR5_0 */
/* USB_PHYCR5_1 */
#define USB_PHYIR5_1_RG_SQTH0 (0x03)
#define USB_PHYIR5_1_RG_RG_RCVB0 (0x20)
#define USB_PHYIR5_1_RG_RG_SQB0 (0x40)
/* USB_PHYCR5_2 */
/* USB_PHYCR5_3 */
#define USB_PHYCR5_3_TERM_SELECT (0x04)
#define USB_PHYCR5_3_XCVR_SELECT_MASK (0x30)
#define USB_PHYCR5_3_XCVR_SELECT_L (0x10)
#define USB_PHYCR5_3_DP_PULL_DOWN (0x40)
#define USB_PHYCR5_3_DM_PULL_DOWN (0x80)
#define USB_PHYCR5_3_DP_DM_PULL_DOWN (0xC0)
#define USB_PHYCR5_3_OP_MODE (0x01)
#define USB_PHYCR5_3_SUSPENDM (0x08)
/* USB_PHYIR1_0 */
#define USB_PHYIR1_0_IDPULLUP (0x01)
#define USB_PHYIR1_0_DRVVBUS (0x02)
#define USB_PHYIR1_0_TX_VALID (0x04)
/* USB_PHYIR1_1 */
#define USB_PHYIR1_1_RG_DM1_ABIST_SELE (0x0A)
/* USB_PHYIR1_2 */
/* USB_PHYIR1_3 */
/* USB_PHYIR2_0 */
/* USB_PHYIR2_1 */
/* USB_PHYIR2_2 */
/* USB_PHYIR2_3 */
/* USB_PHYIR3_0 */
#define USB_PHYIR3_0_LINESTATE_DP (0x40)
#define USB_PHYIR3_0_LINESTATE_DM (0x80)
/* USB_PHYIR3_1 */
#define USB_PHYIR3_1_SESSEND (0x02)
#define USB_PHYIR3_1_IDDIG (0x08)
/* USB_PHYIR3_2 */
#define USB_PHYIR3_2_IDDIG (0x08)
/* USB_PHYIR3_3 */
/* USB_PHYIR4_0 */
#define USB_PHYIR4_0_HS_TERMC_MASK (0x70)
#define USB_PHYIR4_0_RG_CALIB_SELE0_ENABLE (0xC0)
#define USB_PHYIR4_0_RG_CALIB_SELE0_DISABLE (0x40)
#define USB_PHYIR4_0_RG_TX_I_TRIM0 (0x03)
#define USB_PHYIR4_0_RG_CALIB_SELE0 (0x50)
#define USB_PHYIR4_0_RG_CALIB_SELE0_2 (0x60)
/* USB_PHYIR4_1 */
/* USB_PHYIR4_2 */
#define USB_PHYIR4_2_RG_HSTX_SRCTRL0 (0x01)
#define USB_PHYIR4_2_RG_HSTX_DBIST0 (0xC0)
/* USB_PHYIR4_3 */
#define USB_PHYIR4_3_DEGLICH (0xAA)
#define USB_PHYIR4_3_RG_DISCD (0x02)
/* USB_PHYIR5_0 */
/* USB_PHYIR5_1 */
#define USB_PHYIR5_1_RG_SQTH0 (0x03)
/* USB_PHYIR5_2 */
/* USB_PHYIR5_3 */
/* USB_PHYIR6_0 */
#define USB_PHYIR6_0_RG_DP_100K_EN (0x01)
#define USB_PHYIR6_0_RG_DM_100K_EN (0x02)
/* USB_PHYIR6_1 */
#define USB_PHYIR6_1_BGR_DIV_L (0x10)
#define USB_PHYIR6_1_RG_OTG_VBUSTH (0x00)
#define USB_PHYIR6_1_VBUSCMP_EN (0x04)
/* USB_PHYIR6_2 */
/* USB_PHYIR6_3 */
#elif (defined(DRV_USB_PHY_U65_IP)) //MT62776 , MT6251 , MT6255
#ifdef __USB_HS_SLEW_RATE_CAL__
#define USB_HS_SLEW_RATE_CAL_TIME_WINDOW 0x400
#define USB_HS_SLEW_RATE_CAL_A 3
#define USB_HS_SLEW_RATE_CAL_FRA (66)
#define USB_FMCR0 (USB_base+0xF00) /* RW */
#define USB_FMCR1 (USB_base+0xF04) /* RW */
#define USB_FMCR2 (USB_base+0xF08) /* RW */
#define USB_FMMONR0 (USB_base+0xF0C) /* RW */
#define USB_FMMONR1 (USB_base+0xF10) /* RW */
#endif //USB_HS_SLEW_RATE_CAL
/* USB phy register */
#define USB_U2PHYAC0_0 (USB_base+0x800) /* RW */
#define USB_U2PHYAC0_1 (USB_base+0x801) /* RW */
#define USB_U2PHYAC0_2 (USB_base+0x802) /* RW */
#define USB_U2PHYAC0_3 (USB_base+0x803) /* RW */
#define USB_U2PHYAC1_0 (USB_base+0x804) /* RW */
#define USB_U2PHYAC1_1 (USB_base+0x805) /* RW */
#define USB_U2PHYAC1_2 (USB_base+0x806) /* RW */
#define USB_U2PHYAC1_3 (USB_base+0x807) /* RW */
#define USB_U2PHYACR0_0 (USB_base+0x810) /* RW */
#define USB_U2PHYACR0_1 (USB_base+0x811) /* RW */
#define USB_U2PHYACR0_2 (USB_base+0x812) /* RW */
#define USB_U2PHYACR0_3 (USB_base+0x813) /* RW */
#define USB_U2PHYACR1_0 (USB_base+0x814) /* RW */
#define USB_U2PHYACR1_1 (USB_base+0x815) /* RW */
#define USB_U2PHYACR1_2 (USB_base+0x816) /* RW */
#define USB_U2PHYACR1_3 (USB_base+0x817) /* RW */
#define USB_U2PHYACR2_0 (USB_base+0x818) /* RW */
#define USB_U2PHYACR2_1 (USB_base+0x819) /* RW */
#define USB_U2PHYACR2_2 (USB_base+0x81A) /* RW */
#define USB_U2PHYACR2_3 (USB_base+0x81B) /* RW */
#define USB_U2PHYACR3_0 (USB_base+0x81C) /* RW */
#define USB_U2PHYACR3_1 (USB_base+0x81D) /* RW */
#define USB_U2PHYACR3_2 (USB_base+0x81E) /* RW */
#define USB_U2PHYACR3_3 (USB_base+0x81F) /* RW */
#define USB_U2PHYACR4_0 (USB_base+0x820) /* RW */
#define USB_U2PHYACR4_1 (USB_base+0x821) /* RW */
#define USB_U2PHYACR4_2 (USB_base+0x822) /* RW */
#define USB_U2PHYACR4_3 (USB_base+0x823) /* RW */
#define USB_U2PHYACHG_0 (USB_base+0x824) /* RW */
#define USB_U2PHYACHG_1 (USB_base+0x825) /* RW */
#define USB_U2PHYACHG_2 (USB_base+0x826) /* RW */
#define USB_U2PHYACHG_3 (USB_base+0x827) /* RW */
#define USB_U2PHYDCR0_0 (USB_base+0x860) /* RW */
#define USB_U2PHYDCR0_1 (USB_base+0x861) /* RW */
#define USB_U2PHYDCR0_2 (USB_base+0x862) /* RW */
#define USB_U2PHYDCR0_3 (USB_base+0x863) /* RW */
#define USB_U2PHYDCR1_0 (USB_base+0x864) /* RW */
#define USB_U2PHYDCR1_1 (USB_base+0x865) /* RW */
#define USB_U2PHYDCR1_2 (USB_base+0x866) /* RW */
#define USB_U2PHYDCR1_3 (USB_base+0x867) /* RW */
#define USB_U2PHYDTM0_0 (USB_base+0x868) /* RW */
#define USB_U2PHYDTM0_1 (USB_base+0x869) /* RW */
#define USB_U2PHYDTM0_2 (USB_base+0x86A) /* RW */
#define USB_U2PHYDTM0_3 (USB_base+0x86B) /* RW */
#define USB_U2PHYDTM1_0 (USB_base+0x86C) /* RW */
#define USB_U2PHYDTM1_1 (USB_base+0x86D) /* RW */
#define USB_U2PHYDTM1_2 (USB_base+0x86E) /* RW */
#define USB_U2PHYDTM1_3 (USB_base+0x86F) /* RW */
#define USB_U2PHYDMON0_0 (USB_base+0x870) /* RW */
#define USB_U2PHYDMON0_1 (USB_base+0x871) /* RW */
#define USB_U2PHYDMON0_2 (USB_base+0x872) /* RW */
#define USB_U2PHYDMON0_3 (USB_base+0x873) /* RW */
#define USB_U1PHYCR0_0 (USB_base+0x8C0) /* RW */
#define USB_U1PHYCR0_1 (USB_base+0x8C1) /* RW */
#define USB_U1PHYCR0_2 (USB_base+0x8C2) /* RW */
#define USB_U1PHYCR0_3 (USB_base+0x8C3) /* RW */
#define USB_U1PHYCR1_0 (USB_base+0x8C4) /* RW */
#define USB_U1PHYCR1_1 (USB_base+0x8C5) /* RW */
#define USB_U1PHYCR1_2 (USB_base+0x8C6) /* RW */
#define USB_U1PHYCR1_3 (USB_base+0x8C7) /* RW */
#define USB_U1PHYCR2_0 (USB_base+0x8C8) /* RW */
#define USB_U1PHYCR2_1 (USB_base+0x8C9) /* RW */
#define USB_U1PHYCR2_2 (USB_base+0x8CA) /* RW */
#define USB_U1PHYCR2_3 (USB_base+0x8CB) /* RW */
#define USB_U1PHYACHG_0 (USB_base+0x8CC) /* RW */
#define USB_U1PHYACHG_1 (USB_base+0x8CD) /* RW */
#define USB_U1PHYACHG_2 (USB_base+0x8CE) /* RW */
#define USB_U1PHYACHG_3 (USB_base+0x8CF) /* RW */
#define USB_REGFPPC_0 (USB_base+0x8E0) /* RW */
#define USB_REGFPPC_1 (USB_base+0x8E1) /* RW */
#define USB_REGFPPC_2 (USB_base+0x8E2) /* RW */
#define USB_REGFPPC_3 (USB_base+0x8E3) /* RW */
#define USB_VERSIONC_0 (USB_base+0x8F0) /* RW */
#define USB_VERSIONC_1 (USB_base+0x8F1) /* RW */
#define USB_VERSIONC_2 (USB_base+0x8F2) /* RW */
#define USB_VERSIONC_3 (USB_base+0x8F3) /* RW */
#define USB_REGFCOM_0 (USB_base+0x8FC) /* RW */
#define USB_REGFCOM_1 (USB_base+0x8FD) /* RW */
#define USB_REGFCOM_2 (USB_base+0x8FE) /* RW */
#define USB_REGFCOM_3 (USB_base+0x8FF) /* RW */
/* USB PHY variable*/
/* USB_U2PHYAC0_0 */
#define USB_U2PHYAC0_0_RG_BGR_BGR_EN (0x01)
#define USB_U2PHYAC0_0_RG_BGR_ISRC_EN (0x02)
#define USB_U2PHYAC0_0_RG_BGR_CHP_EN (0x04)
#define USB_U2PHYAC0_0_RG_REF_INTR_EN (0x80)
/* USB_U2PHYAC0_1 */
/* USB_U2PHYAC0_2 */
#define USB_U2PHYAC0_2_RG_PLL_DIV (0x0A)
#define USB_U2PHYAC0_2_RG_PLL_DIV_MASK (0x3F)
/* USB_U2PHYAC0_3 */
/* USB_U2PHYAC1_0 */
/* USB_U2PHYAC1_1 */
/* USB_U2PHYAC1_2 */
/* USB_U2PHYAC1_3 */
/* USB_U2PHYACR0_0 */
#define USB_U2PHYACR0_0_RG_LS_CROSS (0x08)
#define USB_U2PHYACR0_0_RG_FS_CROSS (0x02)
#define USB_U2PHYACR0_0_RG_FS_CROSS_MASK (0x03)
#define USB_U2PHYACR0_0_RG_LS_CROSS_MASK (0x0C)
#define USB_U2PHYACR0_0_RG_PUPD_BIST_EN (0x10)
/* USB_U2PHYACR0_1 */
#define USB_U2PHYACR0_1_RG_EN_PU_DP (0x80)
#define USB_U2PHYACR0_1_RG_EN_PD_DP (0x40)
/* USB_U2PHYACR0_2 */
/* USB_U2PHYACR0_3 */
/* USB_U2PHYACR1_0 */
#define USB_U2PHYACR1_0_RG_EN_PU_DM (0x80)
#define USB_U2PHYACR1_0_RG_EN_PD_DM (0x40)
#define USB_U2PHYACR1_0_RG_HS_TERM_EN_MODE (0x20)
/* USB_U2PHYACR1_1 */
#define USB_U2PHYACR1_1_RG_HSTX_SRCTRL_MASK (0x07)
#define USB_U2PHYACR1_1_RG_HSTX_SRCTRL (0x01)
/* USB_U2PHYACR1_2 */
#define USB_U2PHYACR1_2_RG_DISCD_MASK (0x03)
#define USB_U2PHYACR1_2_RG_DISCD (0x02)
/* USB_U2PHYACR1_3 */
/* USB_U2PHYACR2_0 */
#define USB_U2PHYACR2_0_RG_SQTH (0x03)
#define USB_U2PHYACR2_0_RG_SQTH_MASK (0x07)
#define USB_U2PHYACR2_0_RG_SQB (0x40)
#define USB_U2PHYACR2_0_RG_RCVB (0x20)
#define USB_U2PHYACR2_0_RG_DISCB (0x10)
/* USB_U2PHYACR2_1 */
#define USB_U2PHYACR2_1_RG_DP_ABIST_SOURCE_EN (0x20)
/* USB_U2PHYACR2_2 */
#define USB_U2PHYACR2_2_RG_DM_ABIST_SOURCE_EN (0x20)
/* USB_U2PHYACR2_3 */
#define USB_U2PHYACR2_3_RG_OTG_VBUSCMP_EN (0x04)
#define USB_U2PHYACR2_3_RG_DM_100K_EN (0x02)
#define USB_U2PHYACR2_3_RG_DP_100K_EN (0x01)
/* USB_U2PHYACR3_0 */
#define USB_U2PHYACR3_0_RG_OTG_VBUSTH (0x40)
/* USB_U2PHYACR3_1 */
#define USB_U2PHYACR3_2_RG_USBRESERVED_6 (0x40)
/* USB_U2PHYACR3_2 */
#define USB_U2PHYACR3_2_RG_USBRESERVED_10 (0x04)
/* USB_U2PHYACR3_3 */
#define USB_U2PHYACR3_3_RG_USBRESERVED (0x20)
/* USB_U2PHYACR4_0 */
/* USB_U2PHYACR4_1 */
/* USB_U2PHYACR4_2 */
/* USB_U2PHYACR4_3 */
/* USB_U2PHYACHG_0 */
#define USB_U2PHYACHG_0_RG_CHGDT_IOUT_SEL (0x03)
#define USB_U2PHYACHG_0_RG_CHGDT_IUP_SEL_MASK (0x0C)
#define USB_U2PHYACHG_0_RG_CHGDT_IUP_SEL (0x04)
#define USB_U2PHYACHG_0_RG_CHGDT_IDN_SEL (0x30)
#define USB_U2PHYACHG_0_RG_CHGDT_COMP_SEL (0xC0)
/* U2PHYACHG_1 */
#define USB_U2PHYACHG_1_RG_CHGDT_VREF_SEL (0x03)
#define USB_U2PHYACHG_1_RG_CHGDT_OPOUT_SEL (0x0C)
#define USB_U2PHYACHG_1_RG_CHGDT_IREF_SEL (0x30)
/* U2PHYACHG_2 */
#define USB_U2PHYACHG_2_RG_CHGDT_EN_SEL_MASK (0x0F)
#define USB_U2PHYACHG_2_RG_CHGDT_EN_SEL (0x08)
#define USB_U2PHYACHG_2_RG_EN_CHGDT (0x10)
/* U2PHYACHG_3 */
#define USB_U2PHYACHG_3_RG_CHGDT_RESERVED (0xFF)
#define USB_U2PHYACHG_3_RG_CHGDT_IREF_EN (0x40)
#define USB_U2PHYACHG_3_RG_CHGDT_ISINK_EN (0x20)
/* USB_U2PHYDCR0_0 */
#define USB_U2PHYDCR0_0_RG_EARLY_HSTX_I (0x40)
#define USB_U2PHYDCR0_0_RG_HSTX_ANA_SER_EN (0x80)
/* USB_U2PHYDCR0_1 */
/* USB_U2PHYDCR0_2 */
/* USB_U2PHYDCR0_3 */
#define USB_U2PHYDCR0_3_RG_PLL_STABLE (0x02)
/* USB_U2PHYDCR1_0 */
/* USB_U2PHYDCR1_1 */
/* USB_U2PHYDCR1_2 */
#define USB_U2PHYDCR1_2_RG_UART_EN (0x40)
#define USB_U2PHYDCR1_2_RG_USB_CLKEN (0x20)
/* USB_U2PHYDCR1_3 */
#define USB_U2PHYDCR1_3_RG_PHYD_RESERVE_2 (0x04)
/* USB_U2PHYDTM0_0 */
#define USB_U2PHYDTM0_0_RG_DMPULLDOWN (0x80)
#define USB_U2PHYDTM0_0_RG_DPPULLDOWN (0x40)
#define USB_U2PHYDTM0_0_RG_XCVRSEL_MASK (0x30)
#define USB_U2PHYDTM0_0_RG_RG_XCVRSEL (0x10)
#define USB_U2PHYDTM0_0_RG_SUSPENDM (0x08)
#define USB_U2PHYDTM0_0_RG_TERMSEL (0x04)
#define USB_U2PHYDTM0_0_RG_OPMODE (0x01)
/* USB_U2PHYDTM0_1 */
#define USB_U2PHYDTM0_1_UTMI_MUSEL (0x80)
#define USB_U2PHYDTM0_1_RG_DATAIN_MASK (0x3C)
#define USB_U2PHYDTM0_1_RG_DATAIN (0x00)
/* USB_U2PHYDTM0_2 */
#define USB_U2PHYDTM0_2_FORCE_DATAIN (0x80)
#define USB_U2PHYDTM0_2_FORCE_DM_PULLDOWN (0x20)
#define USB_U2PHYDTM0_2_FORCE_DP_PULLDOWN (0x10)
#define USB_U2PHYDTM0_2_FORCE_XCVRSEL (0x08)
#define USB_U2PHYDTM0_2_FORCE_SUSPENDM (0x04)
#define USB_U2PHYDTM0_2_FORCE_TERMSEL (0x02)
/* USB_U2PHYDTM0_3 */
#define USB_U2PHYDTM0_3_FORCE_UART_EN (0x04)
/* USB_U2PHYDTM1_0 */
#define USB_U2PHYDTM1_0_RG_SESSEND (0x10)
#define USB_U2PHYDTM1_0_RG_IDPULLUP (0x01)
/* USB_U2PHYDTM1_1 */
#define USB_U2PHYDTM1_1_FORCE_IDPULLUP (0x01)
/* USB_U2PHYDTM1_2 */
/* USB_U2PHYDTM1_3 */
/* USB_U2PHYDMON0_0 */
/* USB_U2PHYDMON0_1 */
/* USB_U2PHYDMON0_2 */
#define USB_U2PHYDMON0_2_LINESTATE_DP (0x40)
#define USB_U2PHYDMON0_2_LINESTATE_DM (0x80)
/* USB_U2PHYDMON0_3 */
#define USB_U2PHYDMON0_3_VBUSVALID_MAC (0x04)
#define USB_U2PHYDMON0_3_IDDIG_MAC (0x08)
/* USB_U1PHYCR0_0 */
/* USB_U1PHYCR0_1 */
#define USB_U1PHYCR0_1_RG_USB11_FSLS_ENBGRI (0x08)
/* USB_U1PHYCR0_2 */
/* USB_U1PHYCR0_3 */
/* USB_U1PHYCR1_0 */
/* USB_U1PHYCR1_1 */
#define USB_U1PHYCR1_1_RG_USB11_USBRESERVED (0x01)
#define USB_U1PHYCR1_1_RG_USB11_USBRESERVED_PMU (0x80)
/* USB_U1PHYCR1_2 */
/* USB_U1PHYCR1_3 */
/* USB_U1PHYCR2_0 */
/* USB_U1PHYCR2_1 */
/* USB_U1PHYCR2_2 */
/* USB_U1PHYCR2_3 */
/* USB_U1PHYACHG_0 */
/* USB_U1PHYACHG_1 */
/* USB_U1PHYACHG_2 */
/* USB_U1PHYACHG_3 */
/* USB_REGFPPC_0 */
/* USB_REGFPPC_1 */
/* USB_REGFPPC_2 */
/* USB_REGFPPC_3 */
/* USB_VERSIONC_0 */
/* USB_VERSIONC_1 */
/* USB_VERSIONC_2 */
/* USB_VERSIONC_3 */
/* USB_REGFCOM_0 */
/* USB_REGFCOM_1 */
/* USB_REGFCOM_2 */
/* USB_REGFCOM_3 */
#elif (defined(DRV_USB_PHY_M60_IP)) //MT6256E2
#ifdef __USB_HS_SLEW_RATE_CAL__
#define USB_HS_SLEW_RATE_CAL_TIME_WINDOW 0x400
#define USB_HS_SLEW_RATE_CAL_A 28
#define USB_HS_SLEW_RATE_CAL_FRA (1000)
#define USB_FMMONR1_RG_FRCK_EN (1<<8)
#define USB_FMCR0 (USB_base+0xF00) /* RW */
#define USB_FMCR1 (USB_base+0xF04) /* RW */
#define USB_FMCR2 (USB_base+0xF08) /* RW */
#define USB_FMMONR0 (USB_base+0xF0C) /* RW */
#define USB_FMMONR1 (USB_base+0xF10) /* RW */
#endif //USB_HS_SLEW_RATE_CAL
#define USB_U2PHYAC0 (USB_base+0x800) //USB2.0 PHYA Common Registers
#define USB_U2PHYAC1 (USB_base+0x804) //USB2.0 PHYA Common Registers
#define USB_U2PHYAC2 (USB_base+0x808) //USB2.0 PHYA Common Registers
#define USB_U2PHYACR0 (USB_base+0x810) //USB2.0 PHYA Control Registers
#define USB_U2PHYACR1 (USB_base+0x814) //USB2.0 PHYA Control Registers
#define USB_U2PHYACR2 (USB_base+0x818) //USB2.0 PHYA Control Registers
#define USB_U2PHYACR3 (USB_base+0x81C) //USB2.0 PHYA Control Registers
#define USB_U2PHYACR4 (USB_base+0x820) //USB2.0 PHYA Control Registers
#define USB_U2PHYDCR0 (USB_base+0x860) //USB2.0 PHYD Control Registers
#define USB_U2PHYDCR1 (USB_base+0x864) //USB2.0 PHYD Control Registers
#define USB_U2PHYDTM0 (USB_base+0x868) //USB2.0 PHYD TestMode Registers
#define USB_U2PHYDTM1 (USB_base+0x86C) //USB2.0 PHYD TestMode Registers
#define USB_U2PHYDMON0 (USB_base+0x870) //USB2.0 PHYD Monitor Registers
#define USB_U2PHYDMON1 (USB_base+0x874) //USB2.0 PHYD Monitor Registers
#define USB_U2PHYDMON2 (USB_base+0x878) //USB2.0 PHYD Monitor Registers
#define USB_U1PHYCR0 (USB_base+0x8C0) //USB1.1 PHY Control Registers
#define USB_U1PHYCR1 (USB_base+0x8C4) //USB1.1 PHY Control Registers
#define USB_U1PHYCR2 (USB_base+0x8C8) //USB1.1 PHY Control Registers
#define USB_REGFPPC (USB_base+0x8E0) //RegFile Per-Page Common Registers
#define USB_VERSIONC (USB_base+0x8F0) //Version Code
#define USB_REGFCOM (USB_base+0x8FC) //RegFile Common Registers
#define USB_U2PHYACR0_RG_USB20_HSTX_SRCTRL_CLR (0x7<<16)
#define USB_U2PHYACR0_RG_USB20_HSTX_SRCTRL (0x5<<16)
#define USB_U2PHYACR0_RG_USB20_HSTX_SRCAL_EN (0x1<<23)
#define USB_U2PHYACR1_RG_USB20_DM_ABIST_SOURCE_EN (0x1<<15)
#define USB_U2PHYDTM0_force_uart_en (1<<26)
#define USB_U2PHYDTM0_force_suspendm (1<<18)
#define USB_U2PHYDTM0_RG_SUSPENDM (1<<3)
#define USB_U2PHYDTM1_RG_UART_EN (1<<16)
#define USB_U2PHYAC0_RG_USB20_USBPLL_FBDIV_6_0_CLR (0x7F<<16) //[6:0]
#define USB_U2PHYAC0_RG_USB20_USBPLL_FBDIV_6_0 (9<<16) //[6:0]
#define USB_U2PHYACR2_RG_USB20_OTG_VBUSCMP_EN (1<<27)
#define USB_U2PHYACR3_RG_USB20_PHY_REV_7 (1<<7)
#define USB_U2PHYACR3_RG_USB20_HS_TERM_EN_MODE (0x2<<13)
#define USB_U2PHYACR3_RG_USB20_HS_TERM_EN_MODE_CLR (0x3<<13)
#define USB_U2PHYACR4_RG_USB20_DP_100K_EN (1<<16)
#define USB_U2PHYACR4_RG_USB20_DM_100K_EN (1<<17)
#define USB_U2PHYDTM0_RG_DPPULLDOWN (1<<6)
#define USB_U2PHYDTM0_RG_DMPULLDOWN (1<<7)
#define USB_U2PHYDTM0_RG_XCVRSEL_1_0_CLR (0x3<<4) //[1:0]
#define USB_U2PHYDTM0_RG_XCVRSEL_1_0 (0x1<<4) //[1:0]
#define USB_U2PHYDTM0_RG_DATAIN_3_0_CLR (0xF<<10) //[3:0]
#define USB_U2PHYDTM0_force_dp_pulldown (1<<20)
#define USB_U2PHYDTM0_force_dm_pulldown (1<<21)
#define USB_U2PHYDTM0_force_termsel (1<<17)
#define USB_U2PHYDTM0_force_xcvrsel (1<<19)
#define USB_U2PHYDTM0_force_datain (1<<23)
#define USB_U2PHYDTM0_RG_TERMSEL (1<<2)
#define USB_U2PHYDCR1_RG_PLL_STABL (1<<19)
#define USB_U2PHYDMON1_USB20_LINE_STATE_DP (1<<22)
#define USB_U2PHYDMON1_USB20_LINE_STATE_DM (1<<23)
#define USB_U2PHYAC0_RG_USB20_INTR_EN (1<<14)
#elif (defined(DRV_USB_PHY_U40_IP)) //future chip
#else // Old PHY (MT6235 / MT6238 /MT6516 /MT6268A / MT6253T)
/* USB phy register */
#define USB_PHYCR1_0 (USB_base+0x600) /* RW */
#define USB_PHYCR1_1 (USB_base+0x601) /* RW */
#define USB_PHYCR1_2 (USB_base+0x602) /* RW */
#define USB_PHYCR1_3 (USB_base+0x603) /* RW */
#define USB_PHYCR2_0 (USB_base+0x604) /* RW */
#define USB_PHYCR2_1 (USB_base+0x605) /* RW */
#define USB_PHYCR2_2 (USB_base+0x606) /* RW */
#define USB_PHYCR2_3 (USB_base+0x607) /* RW */
#define USB_PHYCR3_0 (USB_base+0x608) /* RW */
#define USB_PHYCR3_1 (USB_base+0x609) /* RW */
#define USB_PHYCR3_2 (USB_base+0x60A) /* RW */
#define USB_PHYCR3_3 (USB_base+0x60B) /* RW */
#define USB_PHYCR4_0 (USB_base+0x60C) /* RW */
#define USB_PHYCR4_1 (USB_base+0x60D) /* RW */
#define USB_PHYCR4_2 (USB_base+0x60E) /* RW */
#define USB_PHYCR4_3 (USB_base+0x60F) /* RW */
#define USB_PHYCR5_0 (USB_base+0x610) /* RW */
#define USB_PHYCR5_1 (USB_base+0x611) /* RW */
#define USB_PHYCR5_2 (USB_base+0x612) /* RW */
#define USB_PHYCR5_3 (USB_base+0x613) /* RW */
#define USB_PHYIR1_0 (USB_base+0x614) /* RW */
#define USB_PHYIR1_1 (USB_base+0x615) /* RW */
#define USB_PHYIR1_2 (USB_base+0x616) /* RW */
#define USB_PHYIR1_3 (USB_base+0x617) /* RW */
#define USB_PHYIR2_0 (USB_base+0x618) /* RW */
#define USB_PHYIR2_1 (USB_base+0x619) /* RW */
#define USB_PHYIR2_2 (USB_base+0x61A) /* RW */
#define USB_PHYIR2_3 (USB_base+0x61B) /* RW */
/* USB PHY variable*/
/* USB_PHY ALL*/
#define USB_PHY_CLEAR_MASK (0x00)
/* USB_PHYCR1_0 */
#define USB_PHYCR1_0_PLL_EN (0x80)
/* USB_PHYCR1_1 */
#define USB_PHYCR1_1_PLL_CCP_SET (0x30)
#define USB_PHYCR1_1_PLL_CCP_MASK (0xF0)
/* USB_PHYCR1_2 */
#define USB_PHYCR1_2_PLL_VCOG_H (0x08)
#define USB_PHYCR1_2_HS_RCVB (0x40)
/* USB_PHYCR2_0 */
#define USB_PHYCR2_0_HS_SQB_MASK (0x0F)
#define USB_PHYCR2_0_HS_SQD_MASK (0xF0)
#define USB_PHYCR2_0_HS_SQD_SET (0xA0)
/* USB_PHYCR2_2 */
#define USB_PHYCR2_2_FORCE_DATA_IN (0x40)
#define USB_PHYCR2_2_FORCE_TX_VALID (0x20)
#define USB_PHYCR2_2_HS_DISCP (0x01)
/* USB_PHYCR2_3 */
#define USB_PHYCR2_3_HS_TERMC_MASK (0x1F)
#define USB_PHYCR2_3_FORCE_DP_PULLDOWN (0x20)
#define USB_PHYCR2_3_FORCE_DM_PULLDOWN (0x40)
#define USB_PHYCR2_3_FORCE_DP_DM_PULLDOWN (0x60)
#define USB_PHYCR2_3_FORCE_DRV_VBUS (0x80)
#define USB_PHYCR2_3_HS_TERMC (0x08)
#define USB_PHYCR2_3_HS_TERMC2 (0x0B)
#define USB_PHYCR2_3_FORCE_SUSPENDM (0x04)
/* USB_PHYCR3_0 */
#define USB_PHYCR3_0_IADJ_MASK (0x07)
#define USB_PHYCR3_0_IADJ_MASK2 (0x04)
#define USB_PHYCR3_0_IADJ_RESISTER_SET (0x06)
#define USB_PHYCR3_0_CLEAR_MASK (0x00)
/* USB_PHYCR3_2 */
#define USB_PHYCR3_2_TEST_CTRL_MASK (0x0F)
#define USB_PHYCR3_2_TEST_CTRL1_SET (0x02)
#define USB_PHYCR3_2_TEST_CTRL2_SET (0x04)
#define USB_PHYCR3_2_CLK_MODE (0x80)
/* USB_PHYCR4_1 */
#define USB_PHYCR4_1_BGR_BGR_EN (0x01)
#define USB_PHYCR4_1_BGR_CLK_EN (0x02)
#define USB_PHYCR4_1_BGR_I_SRC_EN (0x04)
#define USB_PHYCR4_1_BGR_CHIP_EN (0x08)
#define USB_PHYCR4_1_BGR_SELPH (0x10)
#define USB_PHYCR4_1_BGR_DIV_L (0x40)
#define USB_PHYCR4_1_FORCE_BGR_ON (0x4F)
/* USB_PHYCR5_0 */
#define USB_PHYCR5_0_VBUSCMP_EN (0x80)
#define USB_PHYCR5_0_CDR_FILT (0x02)
/* USB_PHYCR5_2 */
#define USB_PHYCR5_2_FORCE_OP_MODE (0x01)
#define USB_PHYCR5_2_FORCE_TERM_SELECT (0x02)
#define USB_PHYCR5_2_FORCE_SUSPENDM (0x04)
#define USB_PHYCR5_2_FORCE_XCVR_SELECT (0x08)
#define USB_PHYCR5_2_FORCE_DP_HIGH (0x0B)
#define USB_PHYCR5_2_FORCE_IDPULLUP (0x80)
#define USB_PHYCR5_2_UTMI_MUXSEL (0x40)
/* USB_PHYCR5_3 */
#define USB_PHYCR5_3_TERM_SELECT (0x04)
#define USB_PHYCR5_3_XCVR_SELECT_MASK (0x30)
#define USB_PHYCR5_3_XCVR_SELECT_L (0x10)
#define USB_PHYCR5_3_DP_PULL_DOWN (0x40)
#define USB_PHYCR5_3_DM_PULL_DOWN (0x80)
#define USB_PHYCR5_3_DP_DM_PULL_DOWN (0xC0)
#define USB_PHYCR5_3_OP_MODE (0x01)
#define USB_PHYCR5_3_SUSPENDM (0x08)
/* USB_PHYIR1_0 */
#define USB_PHYIR1_0_IDPULLUP (0x01)
#define USB_PHYIR1_0_DRVVBUS (0x02)
#define USB_PHYIR1_0_TX_VALID (0x04)
/* USB_PHYIR1_3 */
#define USB_PHYIR1_3_LINESTATE_DP (0x40)
#define USB_PHYIR1_3_LINESTATE_DM (0x80)
/* USB_PHYIR2_0 */
#define USB_PHYIR2_0_SESSEND (0x02)
/* USB_PHYIR2_3 */
#define USB_PHYIR2_3_FORCE_USB_CLKOFF (0x20)
#define USB_PHYIR2_3_FORCE_AUX_EN (0x80)
#endif // PHY
//USB IP V3
#if (defined(DRV_USB_PHY_COST_DOWN))
#define USB_LINE_STATE USB_PHYIR3_0
#elif (defined(DRV_USB_PHY_U65_IP))
#define USB_LINE_STATE USB_U2PHYDMON0_2
#elif (defined(DRV_USB_PHY_M60_IP))
#define USB_LINE_STATE USB_U2PHYDMON1
#elif (defined(DRV_USB_PHY_U40_IP)) //future chip
#else
#define USB_LINE_STATE USB_PHYIR1_3
#endif
#elif (defined(DRV_USB_IP_V2))
#define OTG_INT_STAT (USB_base+0x10)
#define OTG_INT_EN (USB_base+0x14)
#define OTG_STATUS (USB_base+0x18)
#define OTG_CTRL (USB_base+0x1c)
#define USB_FM_PKT_NUML (USB_base+0x20)
#define USB_FM_PKT_NUMH (USB_base+0x24)
#define USB_FM_ERR_STAT (USB_base+0x28)
#define USB_FM_CTL (USB_base+0x2c)
#define USB_FM_PKT_CNTL (USB_base+0x30)
#define USB_FM_PKT_CNTH (USB_base+0x34)
#define USB_FM_TIMEOUT (USB_base+0x38)
#define USB_FM_STATUS (USB_base+0x3c)
#define USB_FM_ADDITNL_STAT (USB_base+0x50)
#define USB_FM_ENDPT (USB_base+0x68)
#define USB_FM_INT_MASK (USB_base+0x6c)
#define USB_PHY_EXTRA (USB_base+0x70)
#define USB_INT_STAT (USB_base+0x80)
#define USB_INT_ENB (USB_base+0x84)
#define USB_ERR_STAT (USB_base+0x88)
#define USB_ERR_ENB (USB_base+0x8c)
#define USB_STAT (USB_base+0x90)
#define USB_CTL (USB_base+0x94)
#define USB_ADDR (USB_base+0x98)
#define USB_BDT_PAGE_01 (USB_base+0x9c)
#define USB_BDT_PAGE_02 (USB_base+0xb0)
#define USB_BDT_PAGE_03 (USB_base+0xb4)
#define USB_FRM_NUML (USB_base+0xa0)
#define USB_FRM_NUMH (USB_base+0xa4)
#define USB_TOKEN (USB_base+0xa8)
#define USB_SOF_THLD (USB_base+0xac)
#define USB_ENDPT_CTL_BASE (USB_base+0xc0)
#define USB_ENDPT_CTL(n) (USB_ENDPT_CTL_BASE+4*n)
#define USB_DMA_ENB (USB_base+0x410)
#define USB_DMA_DIS (USB_base+0x414)
#define USB_DMA_ADDR_CNTER_CLR (USB_base+0x418)
#define USB_DMA_FM_SELECT (USB_base+0x41c)
#define USB_SOFT_RST (USB_base+0x420)
#define USB_PHY_CTL (USB_base+0x450)
#define USB_FIFO_RX0_EVEN (USB_base+0x200)
#define USB_FIFO_RX0_ODD (USB_base+0x208)
#define USB_FIFO_TX0_EVEN (USB_base+0x210)
#define USB_FIFO_TX0_ODD (USB_base+0x218)
#define USB_FIFO_RX1 (USB_base+0x220)
#define USB_FIFO_TX1 (USB_base+0x260)
#define USB_FIFO_RX2 (USB_base+0x2a0)
#define USB_FIFO_TX2 (USB_base+0x2e0)
#define USB_FIFO_RX3 (USB_base+0x320)
#define USB_FIFO_TX3 (USB_base+0x328)
#define USB_BDT_RX0_EVEN (USB_base+0x330)
#define USB_BDT_RX0_ODD (USB_base+0x338)
#define USB_BDT_TX0_EVEN (USB_base+0x340)
#define USB_BDT_TX0_ODD (USB_base+0x348)
#define USB_BDT_RX1 (USB_base+0x350)
#define USB_BDT_TX1 (USB_base+0x358)
#define USB_BDT_RX2 (USB_base+0x360)
#define USB_BDT_TX2 (USB_base+0x368)
#define USB_BDT_RX3 (USB_base+0x370)
#define USB_BDT_TX3 (USB_base+0x378)
/* VUSB Endpoint control register masks */
/* Define the bits within the endpoint control register */
#define VUSB_ENDPT_HSHK_BIT (0x01)
#define VUSB_ENDPT_STALL_BIT (0x02)
#define VUSB_ENDPT_TX_EN_BIT (0x04)
#define VUSB_ENDPT_RX_EN_BIT (0x08)
#define VUSB_ENDPT_CTL_EP_CTL_DIS (0x10)
#define VUSB_ENDPT_CTL_RETRY_DIS (0x40)
#define VUSB_ENDPT_CTL_HOST_WO_HUB (0x80)
#define VUSB_ENDPT_DISABLE (0x00)
#define VUSB_ENDPT_CONTROL (VUSB_ENDPT_HSHK_BIT | VUSB_ENDPT_TX_EN_BIT | \
VUSB_ENDPT_RX_EN_BIT | VUSB_ENDPT_CTL_RETRY_DIS)
#define VUSB_ENDPT_BULK_RX (VUSB_ENDPT_HSHK_BIT | VUSB_ENDPT_RX_EN_BIT | \
VUSB_ENDPT_CTL_EP_CTL_DIS | VUSB_ENDPT_CTL_RETRY_DIS)
#define VUSB_ENDPT_BULK_TX (VUSB_ENDPT_HSHK_BIT | VUSB_ENDPT_TX_EN_BIT | \
VUSB_ENDPT_CTL_EP_CTL_DIS | VUSB_ENDPT_CTL_RETRY_DIS)
#define VUSB_ENDPT_BULK_BIDIR (VUSB_ENDPT_HSHK_BIT | VUSB_ENDPT_TX_EN_BIT | \
VUSB_ENDPT_RX_EN_BIT | VUSB_ENDPT_CTL_EP_CTL_DIS | VUSB_ENDPT_CTL_RETRY_DIS)
#define VUSB_ENDPT_ISO_RX (VUSB_ENDPT_RX_EN_BIT | VUSB_ENDPT_CTL_EP_CTL_DIS | \
VUSB_ENDPT_CTL_RETRY_DIS)
#define VUSB_ENDPT_ISO_TX (VUSB_ENDPT_TX_EN_BIT | VUSB_ENDPT_CTL_EP_CTL_DIS | \
VUSB_ENDPT_CTL_RETRY_DIS)
#define VUSB_ENDPT_ISO_BIDIR (VUSB_ENDPT_RX_EN_BIT | VUSB_ENDPT_TX_EN_BIT | \
VUSB_ENDPT_CTL_EP_CTL_DIS | VUSB_ENDPT_CTL_RETRY_DIS)
/* VUSB Control register masks */
#define VUSB_CTL_USB_EN (0x01)
#define VUSB_CTL_SOF_EN (0x01)
#define VUSB_CTL_ODD_RST (0x02)
#define VUSB_CTL_RESUME (0x04)
#define VUSB_CTL_HOST_MODE_EN (0x08)
#define VUSB_CTL_RESET (0x10)
#define VUSB_CTL_TOKEN_BUSY (0x20)
#define VUSB_CTL_TXD_SUSPEND (0x20)
#define VUSB_CTL_SINGLE_ENDED_0 (0x40)
#define VUSB_CTL_JSTATE (0x80)
/* VUSB Interrupt status register masks */
#define VUSB_INT_STAT_RESET (0x01)
#define VUSB_INT_STAT_ERROR (0x02)
#define VUSB_INT_STAT_SOF (0x04)
#define VUSB_INT_STAT_TOKEN_DONE (0x08)
#define VUSB_INT_STAT_SLEEP (0x10)
#define VUSB_INT_STAT_RESUME (0x20)
#define VUSB_INT_STAT_ATTACH (0x40)
#define VUSB_INT_STAT_STALL (0x80)
/* VUSB Interrupt enable register masks*/
#define VUSB_INT_ENB_RESET (0x01)
#define VUSB_INT_ENB_ERROR (0x02)
#define VUSB_INT_ENB_SOF (0x04)
#define VUSB_INT_ENB_TOKEN_DONE (0x08)
#define VUSB_INT_ENB_SLEEP (0x10)
#define VUSB_INT_ENB_RESUME (0x20)
#define VUSB_INT_ENB_ATTACH (0x40)
#define VUSB_INT_ENB_STALL (0x80)
/* VUSB Fast mode error status register masks */
#define USB_FM_ERR_STA_OVR_FLW (0x80)
#define VUSB_FM_ERR_STAT_TOKEN_DONE (0x40)
#define VUSB_FM_ERR_SUC_ERR (0x04)
#define VUSB_FM_ERR_NAK_ERR (0x02)
#define VUSB_FM_ERR_SHORT_ERR (0x01)
/* VUSB Fast mode control register masks */
#define VUSB_FM_CTL_FMENB (0x1)
#define VUSB_FM_CTL_SUCERREN (0x8)
#define VUSB_FM_CTL_EP_RX_ODD_SHIFT 1
#define VUSB_FM_CTL_EP_TX_ODD_SHIFT 2
#define VUSB_FM_CTL_EP_TOG_BIT_SHIFT 6
/* VUSB Fast mode endpoint register masks*/
#define VUSB_FM_EP_TX (0x10)
#define VUSB_FM_EP_TX_RES (0x80)
#define VUSB_FM_EP_ENDPT_MASK (0x0f)
/* VUSB FM DMA index */
#define VUSB_FM_DMA_RX1 0
#define VUSB_FM_DMA_TX1 1
#define VUSB_FM_DMA_RX2 2
#define VUSB_FM_DMA_TX2 3
/* VUSB EXTRA register masks*/
#define VUSB_PHY_RESUME_INT (0x80)
#define VUSB_PHY_RESUME_INT_ENB (0x04)
#define VUSB_PHY_SUSPEND (0x02)
/* VUSB SOFT RST register masks*/
#define VUSB_SOFT_RST_EN (0x01)
/* VUSB BDT masks */
#define VUSB_BDT_OWNS_BIT (1 << 7)
#define VUSB_BDT_DATA01_BIT (1 << 6)
#define VUSB_BDT_KEEP_BIT (1 << 5)
#define VUSB_BDT_NINC_BIT (1 << 4)
#define VUSB_BDT_DTS_BIT (1 << 3)
#define VUSB_BDT_STALL_BIT (1 << 2)
#define VUSB_BDT_BC_SHIFT 16
#define VUSB_BDT_DATA01_SHIFT 6
#define VUSB_BDT_BC_MASK 0x03ff0000
#define VUSB_BDT_PID_MASKS (0x3C)
#define VUSB_BDT_NAK_PID (0x28)
#define VUSB_BDT_ERROR_PID (0x3c)
#define VUSB_BDT_STALL_PID (0x38)
#define VUSB_BDT_BUS_TIMEOUT_PID (0x00)
/* OTG Interrupt Status Register Bit Masks */
#define OTG_INT_STATUS_A_VBUS (0x01)
#define OTG_INT_STATUS_B_SESS_END (0x04)
#define OTG_INT_STATUS_SESS_VLD (0x08)
#define OTG_INT_STATUS_LINE_STATE_CHANGE (0x20)
#define OTG_INT_STATUS_1_MSEC (0x40)
#define OTG_INT_STATUS_ID (0x80)
/* OTG Interrupt Enable Register Bit Masks */
#define OTG_INT_ENABLE_A_VBUS (0x01)
#define OTG_INT_ENABLE_B_SESS_END (0x04)
#define OTG_INT_ENABLE_SESS_VLD (0x08)
#define OTG_INT_ENABLE_1_MSEC (0x40)
#define OTG_INT_ENABLE_ID (0x80)
/*OTG Status register masks*/
#define OTG_STATUS_A_VBUS (0x01)
#define OTG_STATUS_B_SESS_END (0x04)
#define OTG_STATUS_SESS_VLD (0x08)
#define OTG_STATUS_LINE_STATE_CHANGE (0x20)
#define OTG_STATUS_1_MSEC (0x40)
#define OTG_STATUS_ID (0x80)
/*OTG Control register masks*/
#define OTG_CTL_VBUS_DSCHG (0x01)
#define OTG_CTL_VBUS_CHG (0x02)
#define OTG_CTL_OTG_ENABLE (0x04)
#define OTG_CTL_VBUS_ON (0x08)
#define OTG_CTL_DM_LOW (0x10)
#define OTG_CTL_DP_LOW (0x20)
#define OTG_CTL_DM_HIGH (0x40)
#define OTG_CTL_DP_HIGH (0x80)
#define OTG_CTL_RESET_DP_DM (~(OTG_CTL_DM_LOW|OTG_CTL_DP_LOW|OTG_CTL_DM_HIGH|OTG_CTL_DP_HIGH))
#define OTG_CTL_J_STATE (OTG_CTL_DP_HIGH|OTG_CTL_DM_LOW)
#define OTG_CTL_K_STATE (OTG_CTL_DM_HIGH|OTG_CTL_DP_LOW)
#define OTG_CTL_DP_DM_HIGH (OTG_CTL_DP_HIGH|OTG_CTL_DM_HIGH)
#define OTG_CTL_DP_DM_LOW (OTG_CTL_DP_LOW|OTG_CTL_DM_LOW)
/* Token register masks */
#define VUSB_TOKEN_ENDPT (0x0f)
#define VUSB_TOKEN_PID (0xf0)
#define VUSB_TOKEN_OUT (0x10)
#define VUSB_TOKEN_IN (0x90)
#define VUSB_TOKEN_SETUP (0xd0)
#elif (defined(DRV_USB_IP_V1)||defined(DRV_USB_IP_V1_PLUS))
#define USB_FADDR (USB_base+0x0)
#define USB_POWER (USB_base+0x1)
#define USB_INTRIN1 (USB_base+0x2) /*status, read only*/
#define USB_INTRIN2 (USB_base+0x3) /*status, read only*/
#define USB_INTROUT1 (USB_base+0x4) /*status, read only*/
#define USB_INTROUT2 (USB_base+0x5) /*status, read only*/
#define USB_INTRUSB (USB_base+0x6) /*status, read only*/
#define USB_INTRIN1E (USB_base+0x7)
#define USB_INTRIN2E (USB_base+0x8)
#define USB_INTROUT1E (USB_base+0x9)
#define USB_INTROUT2E (USB_base+0xa)
#define USB_INTRUSBE (USB_base+0xb)
#define USB_FRAME1 (USB_base+0xc) /*read only*/
#define USB_FRAME2 (USB_base+0xd) /*read only*/ /*Max Frame length = 11 bits*/
#define USB_INDEX (USB_base+0xe) /*RW, 4bit available*/
#define USB_RSTCTRL (USB_base+0xf)
#define USB_INMAXP (USB_base+0x10) /*RW*/
#define USB_CSR0 (USB_base+0x11)
#define USB_INCSR1 (USB_base+0x11)
#define USB_INCSR2 (USB_base+0x12)
#define USB_OUTMAXP (USB_base+0x13) /*RW*/
#define USB_OUTCSR1 (USB_base+0x14)
#define USB_OUTCSR2 (USB_base+0x15)
#define USB_COUNT0 (USB_base+0x16) /*RO, EP0 only*/
#define USB_OUTCOUNT1 (USB_base+0x16)
#define USB_OUTCOUNT2 (USB_base+0x17) /*RO,11bits*/
#define USB_EP0 (USB_base+0x20) /*4 byte as 1 queue*/
#define USB_ENABLE (USB_base+0x230)
#define USB_DUMMY (USB_base+0x244) /* RW */
#if defined(DRV_USB_IP_V1_PLUS)
#define USB_PHY_CONTROL (USB_base+0x240)
#define USB_PHY_CONTROL_PUB (0x01)
#define USB_PHY_CONTROL_TOF (0x10)
#endif
/*USB_FADDR*/
#define USB_FADDR_ADDRMASK (0x7f) /*RO*/
#define USB_FADDR_UPDATE (0x80) /*RW*/
/*USB_POWER*/
#define USB_POWER_SETSUSPEND (0x01) /*RW*/
#define USB_POWER_SUSPENDSTAT (0x02) /*RO*/ /*Read clear by the intr. register*/
#define USB_POWER_RESUME (0x04) /*RW*/
#define USB_POWER_RESET (0x08) /*RO*/
#define USB_POWER_SWRSTENAB (0x10) /*RW*/
#define USB_POWER_ISOUPDATE (0x80) /*RW*/
/*USB_RSTCTRL*/
#define USB_RSTCTRL_SWRST (0x80) /*RW*/
/*USB_INTRIN1, USB_INTRIN2 is not needed*/
#define USB_INTRIN1_EP0 (0x01) /*RO*/
#define USB_INTRIN1_EP1 (0x02) /*RO*/
#define USB_INTRIN1_EP2 (0x04) /*RO*/
#define USB_INTRIN1_EP3 (0x08) /*RO*/
/*USB_INTROUT1, USB_INTROUT2 is not needed*/
#define USB_INTROUT1_EP1 (0x02) /*RO*/
#define USB_INTROUT1_EP2 (0x04) /*RO*/
/*USB_INTRUSB*/
#define USB_INTRUSB_SUSPEND (0x01) /*RO*/
#define USB_INTRUSB_RESUME (0x02) /*RO*/
#define USB_INTRUSB_RESET (0x04) /*RO*/
#define USB_INTRUSB_SOF (0x08) /*RO*/
/*USB_INTRIN1E, USB_INTRIN2E is not needed*/
#define USB_INTRIN1E_EPEN (0x01) /*RW*/
/*USB_INTROUT1E, USB_INTROUT2E is not needed*/
#define USB_INTROUT1E_EPEN (0x01) /*RW*/
/*USB_INTRUSBE*/
#define USB_INTRUSBE_SUSPEND (0x01) /*RW*/
#define USB_INTRUSBE_RESUME (0x02) /*RW*/
#define USB_INTRUSBE_RESET (0x04) /*RW*/
#define USB_INTRUSBE_SOF (0x08) /*RW*/
/*USB_INMAXP*/
#define USB_INMAXP_MASK (0xff) /*RW*/
/*USB_OUTMAXP*/
#define USB_OUTMAXP_MASK (0xff) /*RW*/
/*USB_CSR0*/
#define USB_CSR0_OUTPKTRDY (0x01) /*RO*/
#define USB_CSR0_INPKTRDY (0x02) /*RW,AC*/
#define USB_CSR0_SENTSTALL (0x04) /*RC*/
#define USB_CSR0_DATAEND (0x08) /*WO,AC*/
#define USB_CSR0_SETUPEND (0x10) /*RO*/
#define USB_CSR0_SENDSTALL (0x20) /*WO,AC*/
#define USB_CSR0_SERVICEDOUTPKTRDY (0x40) /*WO,AC*/
#define USB_CSR0_SERVICESETUPEND (0x80) /*WO,AC*/
/*USB_INCSR1*/
#define USB_INCSR1_INPKTRDY (0x01) /*RW*/
#define USB_INCSR1_FIFONOTEMPTY (0x02) /*RC*/
#define USB_INCSR1_UNDERRUN (0x04) /*RC*/
#define USB_INCSR1_FLUSHFIFO (0x08) /*WO*/
#define USB_INCSR1_SENDSTALL (0x10) /*RW*/
#define USB_INCSR1_SENTSTALL (0x20) /*RC*/
#define USB_INCSR1_CLRDATATOG (0x40) /*WO*/
/*USB_INCSR2*/
#define USB_INCSR2_FRCDATATOG (0x08) /*RW*/
#define USB_INCSR2_DMAENAB (0x10) /*RW*/
#define USB_INCSR2_MODE (0x20) /*RW*/
#define USB_INCSR2_ISO (0x40) /*RW*/
#define USB_INCSR2_AUTOSET (0x80) /*RW*/
/*USB_OUTCSR1*/
#define USB_OUTCSR1_OUTPKTRDY (0x01) /*RC*/
#define USB_OUTCSR1_FIFOFULL (0x02) /*R,AC*/
#define USB_OUTCSR1_OVERRUN (0x04) /*RC*/
#define USB_OUTCSR1_DATAERROR (0x08) /*RO*/
#define USB_OUTCSR1_FLUSHFIFO (0x10) /*WO,AC*/
#define USB_OUTCSR1_SENDSTALL (0x20) /*RW*/
#define USB_OUTCSR1_SENTSTALL (0x40) /*RC*/
#define USB_OUTCSR1_CLRDATATOG (0x80) /*WO*/
/*USB_OUTCSR2*/
#define USB_OUTCSR2_DMAMODE (0x10) /*RW*/
#define USB_OUTCSR2_DMAENAB (0x20) /*RW*/
#define USB_OUTCSR2_ISO (0x40) /*RW*/
#define USB_OUTCSR2_AUTOCLEAR (0x80) /*RW*/
/*USB_ENABLE*/
#define USB_ENABLE_EN (0x1) /*WO*/
#define USB_ENABLE_DIS (0x0) /*WO*/
#if (defined(DRV_USB_PHY_U65_IP)) //MT6276 , MT6251
/* USB phy register */
#define USB_U1PHYCR0_0 (USB_base+0x8C0) /* RW */
#define USB_U1PHYCR0_1 (USB_base+0x8C1) /* RW */
#define USB_U1PHYCR0_2 (USB_base+0x8C2) /* RW */
#define USB_U1PHYCR0_3 (USB_base+0x8C3) /* RW */
#define USB_U1PHYCR1_0 (USB_base+0x8C4) /* RW */
#define USB_U1PHYCR1_1 (USB_base+0x8C5) /* RW */
#define USB_U1PHYCR1_2 (USB_base+0x8C6) /* RW */
#define USB_U1PHYCR1_3 (USB_base+0x8C7) /* RW */
#define USB_U1PHYCR2_0 (USB_base+0x8C8) /* RW */
#define USB_U1PHYCR2_1 (USB_base+0x8C9) /* RW */
#define USB_U1PHYCR2_2 (USB_base+0x8CA) /* RW */
#define USB_U1PHYCR2_3 (USB_base+0x8CB) /* RW */
#define USB_U1PHYACHG_0 (USB_base+0x8CC) /* RW */
#define USB_U1PHYACHG_1 (USB_base+0x8CD) /* RW */
#define USB_U1PHYACHG_2 (USB_base+0x8CE) /* RW */
#define USB_U1PHYACHG_3 (USB_base+0x8CF) /* RW */
#define USB_REGFPPC_0 (USB_base+0x8E0) /* RW */
#define USB_REGFPPC_1 (USB_base+0x8E1) /* RW */
#define USB_REGFPPC_2 (USB_base+0x8E2) /* RW */
#define USB_REGFPPC_3 (USB_base+0x8E3) /* RW */
#define USB_VERSIONC_0 (USB_base+0x8F0) /* RW */
#define USB_VERSIONC_1 (USB_base+0x8F1) /* RW */
#define USB_VERSIONC_2 (USB_base+0x8F2) /* RW */
#define USB_VERSIONC_3 (USB_base+0x8F3) /* RW */
#define USB_REGFCOM_0 (USB_base+0x8FC) /* RW */
#define USB_REGFCOM_1 (USB_base+0x8FD) /* RW */
#define USB_REGFCOM_2 (USB_base+0x8FE) /* RW */
#define USB_REGFCOM_3 (USB_base+0x8FF) /* RW */
/* USB PHY variable*/
/* USB_U1PHYCR0_0 */
/* USB_U1PHYCR0_1 */
#define USB_U1PHYCR0_1_RG_USB11_PUPD_BIST_EN (0x01)
#define USB_U1PHYCR0_1_RG_USB11_FSLS_ENBGRI (0x08)
/* USB_U1PHYCR0_2 */
#define USB_U1PHYCR0_2_RG_USB11_EN_PD_DP (0x01)
#define USB_U1PHYCR0_2_RG_USB11_EN_PU_DP (0x02)
#define USB_U1PHYCR0_2_RG_USB11_EN_PD_DM (0x04)
#define USB_U1PHYCR0_2_RG_USB11_EN_PU_DM (0x08)
#define USB_U1PHYCR0_2_RG_USB11_DP_100K_EN (0x10)
#define USB_U1PHYCR0_2_RG_USB11_DM_100K_EN (0x20)
/* USB_U1PHYCR0_3 */
#define USB_U1PHYCR0_3_RG_USB11_DP_ABIST_SOURCE_EN (0x80)
/* USB_U1PHYCR1_0 */
#define USB_U1PHYCR1_0_RG_USB11_DM_ABIST_SOURCE_EN (0x80)
/* USB_U1PHYCR1_1 */
#define USB_U1PHYCR1_1_RG_USB11_USBRESERVED (0x01)
#define USB_U1PHYCR1_1_RG_USB11_USBRESERVED_PMU (0x80)
/* USB_U1PHYCR1_2 */
/* USB_U1PHYCR1_3 */
/* USB_U1PHYCR2_0 */
/* USB_U1PHYCR2_1 */
#define USB_U1PHYCR2_1_AD_USB11_RXP (0x01)
#define USB_U1PHYCR2_1_AD_USB11_RXM (0x02)
/* USB_U1PHYCR2_2 */
/* USB_U1PHYCR2_3 */
/* USB_U1PHYACHG_0 */
/* USB_U1PHYACHG_1 */
/* USB_U1PHYACHG_2 */
/* USB_U1PHYACHG_3 */
/* USB_REGFPPC_0 */
/* USB_REGFPPC_1 */
/* USB_REGFPPC_2 */
/* USB_REGFPPC_3 */
/* USB_VERSIONC_0 */
/* USB_VERSIONC_1 */
/* USB_VERSIONC_2 */
/* USB_VERSIONC_3 */
/* USB_REGFCOM_0 */
/* USB_REGFCOM_1 */
/* USB_REGFCOM_2 */
/* USB_REGFCOM_3 */
#elif defined(DRV_USB_PHY_T55_IP)
#ifndef USBSIF_base
/*MT6260 using USBSIF_base, but MT6250 using USB_base*/
#ifdef USB_SIFSLV_base
#define USBSIF_base USB_SIFSLV_base
#else
#define USBSIF_base USB_base /*MT6260 using USBSIF_base, but MT6250 using USB_base*/
#endif
#endif
#define USB_U1PHYCR0 (USBSIF_base+0x8C0) //USB1.1 PHY Control Registers
#define USB_U1PHYCR1 (USBSIF_base+0x8C4) //USB1.1 PHY Control Registers
#define USB_U1PHYCR2 (USBSIF_base+0x8C8) //USB1.1 PHY Control Registers
#define U1PHYCR0_RG_USB11_RST (1<<23) //BIT15
#define U1PHYCR0_RG_USB11_FSLS_ENBGRI (1<<11) //BIT11
#define U1PHYCR1_RG_USB11_PHY_REV_7 (1<<15) //BIT15
#endif //DRV_USB_PHY_U65_IP
#endif //(defined(DRV_USB_IP_V1)||defined(DRV_USB_IP_V1_PLUS))
#define USB_MAX_FEATURE_NUM 4
#if (defined(DRV_USB_PHY_CALIBRATION)&& defined(DRV_USB_PHY_COST_DOWN))
#define ABIST_FMTR_CON0 (MIXED_base+0xF80)
#define ABIST_FMTR_CON1 (MIXED_base+0xF84)
#define ABIST_FMTR_DATA (MIXED_base+0xF88)
#define TIME_WINDOW 0x200
#define FRA (65.8)
#endif //SR_Calibration
#ifdef __IC_USB_ENABLE__
#define ICUSB_MAX_TX_EP_NUM 3
#define ICUSB_MAX_RX_EP_NUM 4
#define ICUSB_MAX_EP_NUM 4
#define ICUSB_MAX_DMA_NUM 4
#define ICUSB_MAX_FIFO_SIZE 1024
#define ICUSB_FIFO_START_ADDRESS 64
#define ICUSB_BULK_FIFO_UNIT_SIZE 64
#define MAX_ICUSB_NUM 1
#endif
#endif /* USB_HW_H */